Data Sheet 1999-02-02 Edition 1999-02-02 Published Siemens Bereic
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24C164/P Kbit (2048 bit) Serial CMOS-EEPROM with Synchronous 2-Wire Page Protection Mode
Data Sheet 1999-02-02
Edition 1999-02-02 Published Siemens Bereich Halbleiter, MarketingKommunikation, 81541 Siemens 1999. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
24C164/P Revision History: Previous Version: Page Page previous current Version) Version)
Current Version: 1999-02-02 06.97 Subjects (major changes since last revision)
Changes complete P-DIP-8-4 changed P-DIP-8-3, P-DSO-8-3 changed P-DSO-8-2. document Text changed "Typical programming time bytes". 24C164-D-3/P 24C164-S-3/P deleted. Voltage changed from V.5.5 V.5.5 Package (TSSOP, die, wafer delivery) added. protects upper half entire memory. Footnote added "Values temperature Text changed "The device with voltage range 5.5. available erase/write cycle finished latest after Text added "(see figure 10)". Figure second command byte CSW. Figure "CSW" changed "CSR". write erase cycle finished latest after Figure "ACK" deleted before "STOP". Line "Supply voltage": Text deleted. "Capacitive load added. Some timings changed. line "erase/write cycle" removed. Chapter "Erase Write Characteristics" added.
Page Protection Modeis trademark Siemens
Purchase Siemens components conveys license under Philips patent components system provided system conforms specifications defined Philips.
Kbit (2048 bit) Serial CMOS EEPROMs, Synchronous 2-Wire Bus, Page Protection Mode
24C164/P
Overview Features
Data EEPROM internally organized 2048 bytes pages bytes Page protection mode, flexible page-by-page hardware write protection Additional protection EEPROM bits, data page Protection setting each data page writing protection Protection management without switching power CMOS operation wire serial interface bus, I2C-Bus compatible Three chip select pins address devices
P-DIP-8-3
P-DSO-8-2
Filtered inputs noise suppression with Schmitt trigger Clock frequency High programming flexibility Internal programming voltage Self timed programming cycle including erase Byte-write page-write programming, between bytes Typical programming time bytes High reliability Endurance cycles1) Data retention years1) protection 4000 pins DIP/DSO packages Available extended temperature ranges Industrial: Automotive: 40°C
Values temperature dependent, further information please refer your Siemens Sales office.
Semiconductor Group
1999-02-02
24C164/P
Ordering Information Type 24C164-D/P 24C164-S/P 24C164-D/P 24C164-S/P Ordering Code Q67100-H3504 Q67100-H3499 Q67100-H3503 Q67100-H3497 Package P-DIP-8-3 P-DIP-8-3 Temperature Voltage
V.5.5 40°C V.5.5
P-DSO-8-2 V.5.5 P-DSO-8-2 40°C V.5.5
Other types available request Temperature range Package (TSSOP, die, wafer delivery) Configuration P-DIP-8-3
IEP02125
P-DSO-8-2
IEP02124
Figure Configuration (top view) Definitions Functions Table Symbol CS0, CS1, Function Chip select inputs Ground Serial bidirectional data Serial clock input Write protection input Supply voltage
Semiconductor Group
1999-02-02
24C164/P
Description Serial Clock (SCL) input used clock data into device rising edge clock data device falling edge. Serial Data (SDA) bidirectional used transfer addresses, data control information into device transfer data device. output open drain, performing wired function with number other open drain open collector devices. requires pull-up resistor VCC. Chip Select (CS0, CS1, CS2) CS0, pins chip select inputs either hard wired actively driven VSS. These inputs allow selection eight possible devices sharing common bus. Write Protection (WP) switched allows normal read/write operations. switched protects entire EEPROM against changes (hardware write protection). Additionally write protection managed protection associated each page. (refer chapter Page Protection ModeTM)
Semiconductor Group
1999-02-02
24C164/P
Description
24C164/P device serial electrically erasable programmable read only memory (EEPROM), organized 2048 bit. data memory divided into pages. bytes page programmed simultaneously. Each page protected individually against changes associated protection bit. device conforms specification 2-wire serial I2C-Bus. Three chip select pins allow addressing devices I2C-Bus. voltage design permits operation down with active standby currents. devices have minimum endurance erase/write cycles1). device operates with maximum clock frequency with maximum clock frequency kHz. device with voltage range 5.5. available temperature ranges industrial automotive applications. EEPROMs mounted eight-pin packages also supplied chips.
Values temperature dependent, further information please refer your Siemens Sales office.
Semiconductor Group
1999-02-02
24C164/P
Chip Address Control Logic Start/ Stop Logic Serial Control Logic
Programming Control H.V. Pump
Address Logic
EEPROM
Page Prot. EEPROM
Page Logic
Dout/ACK
IEB02271
Figure Block Diagram
Semiconductor Group
1999-02-02
24C164/P
I2C-Bus Characteristics
24C164/P devices support master/slave bidirectional oriented protocol which EEPROM always takes role slave.
Slave Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
IES02183
Figure Configuration Master Slave Device that initiates transfer data provides clock both transmit receive operations. Device addressed master, capable receiving transmitting data.
Transmitter device with output defined transmitter. open drain characteristic output device applying level wins. Receiver device with input defined receiver.
Semiconductor Group
1999-02-02
24C164/P
conventions serial clock line bidirectional data line shown figure
START Condition Data allowed Change
Acknowledge
STOP Condition
IED02128
Figure I2C-Bus Timing Conventions START Condition, STOP Condition, Data Validation Transfer Acknowledge Standby Mode which busy serial transmission, programming): both clock (SCL) data line (SDA) high state. device enters standby mode after STOP condition after programming cycle. High transition when high, preceding commands. high transition when high, terminating communications. STOP condition initiates EEPROM programming cycle. STOP condition after reading data byte from EEPROM initiates Standby mode. successful reception eight data bits indicated receiver pulling down line during following clock cycle (ACK). transmitter other hand release line after transmission eight data bits. EEPROM receiving device responds with acknowledge, when addressed. master, other side, acknowledges each data byte transmitted EEPROM time read operation releasing line ACK) followed STOP condition. Data must change only during state, data remains valid during high state. Nine clock pulses required transfer data byte, most significant (MSB) transmitted first.
1999-02-02
START Condition STOP Condition
Acknowledge
Data Transfer
Semiconductor Group
24C164/P
Device Addressing EEPROM Addressing
After START condition, master always transmits Command Byte CSR. After acknowledge EEPROM Control Byte follows, content transmitter depend previous Command Byte. description Command Control Bytes shown table Command Byte Selects addressable devices: chip select bits (bit positions compared their corresponding hard wired input pins CS2, CS0, respectively complement pin). Selects operation: least significant write operation (Chip Select Write Command Byte CSW) high read operation (Chip Select Read Command Byte CSR). Contains address information: Command Byte, positions decoded three uppermost EEPROM address bits A10, Command Byte, positions left undefined). Control Byte Following contains eight lower bits EEPROM address (EEA) additional command byte handling protection bit. Following contains data read out, transmitted EEPROM. EEPROM data read long master pulls down after each byte order acknowledge transfer. read operation stopped master releasing acknowledge applied) followed STOP condition. Table Command Control Byte I2C-Bus Addressing Chip EEPROM Definition Chip Select Write Chip Select Read Function
EEPROM address
device internal address counter which points current EEPROM address. address counter incremented after data byte written been acknowledged, during entry further data byte during byte read, thus address counter points following address after reading data byte.
Semiconductor Group 1999-02-02
24C164/P
timing conventions read write operations described figures
Command Byte (CSW)
Data Transfer EEPROM
START from Master
Acknowledge from EEPROM
Acknowledge from EEPROM
IED02184
Figure Timing Command Byte
Command Byte (CSR)
Data Transfer from EEPROM
START from Master
Acknowledge from EEPROM
Acknowledge from Master
IED02275
Figure Timing Command Byte
Semiconductor Group
1999-02-02
24C164/P
Write Operations
Changing EEPROM data initiated master with command byte CSW. Depending state Write Protection Protection Bits (refer chapter Page Protection ModeTM) either byte (Byte Write) byte (Page Write) modified programming procedure. Byte Write After START condition master transmits Chip Select Write byte CSW. EEPROM acknowledges byte during ninth clock cycle. following byte with EEPROM address loaded into address counter EEPROM acknowledged EEPROM. Finally master transmits data byte which also acknowledged EEPROM into internal buffer. Then master applies STOP condition which starts internal programming procedure. data bytes written memory location addressed byte byte A10). programming procedure consists internally timed erase/write cycle. first step, selected byte erased "1". With next internal step, addressed byte written according contents buffer.
Command Byte EEPROM Address
IED02129
Address Setting
Transmission Data Programming Cycle
Activity Master Line Activity EEPROM
Data Byte
Figure Byte Write Sequence erase/write cycle finished latest after Acknowledge polling used speed enhancement order indicate erase/write cycle (refer chapter Acknowledge Polling).
Semiconductor Group
1999-02-02
24C164/P
Page Write page write procedure same byte write procedure first data byte. page write instruction however, entry EEPROM address byte followed sequence maximum sixteen data bytes with data programmed. These bytes transferred internal page buffer EEPROM. first entered data byte will stored according EEPROM address given A10). internal address counter incremented automatically after entered data byte been acknowledged. next data byte then stored next higher EEPROM address. EEPROM addresses within same page have common page address bits through A10. Only respective four least significant address bits through incremented, data bytes programmed simultaneously have within same page. master stops data entry applying STOP condition, which also starts internally timed erase/write cycle. first step, selected bytes erased "1". With next internal step, addressed bytes written according contents page buffer.
Address Setting
Transmission Data
Programming Cycle
Those bytes page that have been addressed included programming.
Command Byte EEPROM Address
IED02140
Activity Master Line Activity EEPROM
Data Byte
Data Byte
Data Byte n+15
Figure Page Write Sequence erase/write cycle finished latest after Acknowledge polling used speed enhancement order indicate erase/write cycle (refer chapter Acknowledge Polling).
Semiconductor Group 1999-02-02
24C164/P
Acknowledge Polling
During erase/write cycle EEPROM will respond command byte until internal write procedure completed. active programming chip returns standby mode last entered EEPROM byte remains addressed address counter. determine internal erase/write cycle acknowledge polling initiated master sending START condition followed command byte (read with write with internal erase/ write cycle completed, device will acknowledge transmission. internal erase/write cycle completed, device acknowledges received command byte protocol activities continue (see figure 10).
Internal Programming Procedure
Send Start
Send CS-Byte
Acknowledge from EEPROM received? Next Operation
IED02131
Figure Flow Chart "Acknowledge Polling"
Semiconductor Group
1999-02-02
24C164/P
STOP from Master initiates erase/write cycle START from Master
Acknowledge EEPROM indicates complete erase/ write cycle STOP from Master initiates erase/write cycle START from Master e.g. STOP condition
Acknowledge EEPROM indicates complete erase/ write cycle
IED02166
Figure Principle Acknowledge Polling
Semiconductor Group
1999-02-02
24C164/P
Read Operations
Reading EEPROM data initiated Master with command byte CSR. Random Read
Random read operations allow master access memory location. Address Setting master generates START condition followed command byte CSW. receipt CSW-byte acknowledged EEPROM with line. master transmits EEPROM address (EEA) EEPROM internal address counter loaded with desired address. After acknowledge EEPROM address received, master generates START condition, which terminates initiated write operation. Then master transmits command byte read, which acknowledged EEPROM. During next eight clock pulses EEPROM transmits data byte increments internal address counter. During following clock cycle masters releases then transmits STOP condition.
Transmission
Transmission EEPROM Data STOP Condition from Master
Activity Master Line Activity EEPROM
Command Byte EEPROM Address
Command Byte Data Byte
IED02133
Figure Random Read
Semiconductor Group
1999-02-02
24C164/P
Current Address Read
EEPROM content read without setting EEPROM address, this case current content address counter will used (e.g. continue previous read operation after Master served interrupt).
Transmission
current address read master generates START condition, which followed command byte (chip select read). receipt CSR-byte acknowledged EEPROM with line. During next eight clock pulses EEPROM transmits data byte increments internal address counter. During following clock cycle masters releases then transmits STOP condition.
Transmission EEPROM Data STOP Condition from Master
Activity Master Line Activity EEPROM
Command Byte Data Byte
IED02132
Figure Current Address Read
Semiconductor Group
1999-02-02
24C164/P
Sequential Read
sequential read initiated same current read random read except that master acknowledges data byte transmitted EEPROM. EEPROM then continues data transmission. internal address counter incremented during each data byte transmission. sequential read allows entire memory read during read operation. After highest addressable memory location reached, internal address pointer "rolls over" address sequential read continues. transmission terminated master releasing line acknowledge) generating STOP condition (see figure 13).
Activity Master Line Activity EEPROM
Command Byte Data Byte
Data Byte
Data Byte
IED02134
Figure Sequential Read
Semiconductor Group
1999-02-02
24C164/P
Page Protection Mode
Each page byte) Data Memory protected against unintended data changes associated protection bit. protection memory consists additional EEPROM (figure 14). Data Data Memory modified only assigned protection erased (logical state "1"). After writing data bytes page, protection achieved writing associated protection (logical state "0"). Further changes data protected page possible only after erasing protection bit.
Data Memory Area
Page Page Page Page Byte
IED02272
Figure Data Page Assigned Protection Memory special procedure write erase protection guarantees proper activation deactivation respectively page protection. protection write erase, data bytes respective page have entered second time. data then compared internally with data protected, case identity protection written erased respectively.
Semiconductor Group
Protection Memory Area
Page
1999-02-02
24C164/P
Protection Handling
bits protection memory addressed directly reading programming. protection address corresponds lowest address within respective page A10, zero). status each protection sensed internally. written state ("0") prevents programming associated page. already protected memory page accidentally addressed programming, programming procedure suppressed. conventional I2C-Bus protocol allows data bytes read programmed only. Therefore independent instruction sequence addressing manipulation protection bits implemented. protection instructions, command byte with preceding START condition followed associated control byte entered twice (figures through 17). first command byte (with A10) followed control byte with bit/page address through always zero. second required entering control byte protection manipulation. three control bytes read, write erase protection listed below (table Table Control Byte Protection Manipulation Address Name Definition Protection read Protection write Protection erase Function
Semiconductor Group
1999-02-02
24C164/P
Protection Write Erase
writing erasing protection bit, data respective page have known master. data page affected write erase procedure protection bit. I2C-Bus protocol shown figure protection write figure protection erase.
Activity Master Line Activity EEPROM
Command Byte
EEPROM Address
0000
Command Byte
Control Byte
Data Byte
Data Data Byte Byte n+15
IED02273
Figure Sequence Protection Write
Activity Master Line Activity EEPROM
Command Byte
EEPROM Address
0000
Command Byte
Control Byte
Data Byte
Data Data Byte Byte n+15
IED02274
Figure Sequence Protection Erase first command byte followed control byte addresses page protected. second command byte (identical content first CSW) followed control byte protection write protection erase. Depending CTx, addressed protection will either written erased.
Semiconductor Group
1999-02-02
24C164/P
control byte followed parameter bytes identical data bytes page protected unprotected. data first entered byte must identical data byte stored lowest address current page. other bytes have identical bytes stored ascending address order within same page. successful verification each byte indicated EEPROM pulling line (acknowledge ACK). After verification last byte, programming procedure initiated STOP condition. Programming started only bits page have been verified successfully. programming taken place, address counter points uppermost address respective page. write erase cycle finished latest after Acknowledge polling used speed enhancement order indicate write erase cycle (refer chapter Acknowledge Polling).
Semiconductor Group
1999-02-02
24C164/P
Protection Read
byte sequence random read shown figure
Activity Master Line Activity EEPROM
Command Byte
EEPROM Address
0000
Command Byte
Control Byte
IED02139
Data Byte
Data Byte
Protection
Figure Byte Sequence Protection Read first command byte followed control byte addresses protection read. second command byte followed control byte protection read. first (MSB) transferred byte protection addressed page. other bits valid. page protection status indicated following Protection normal write operation changes data associated page Protection data associated page protected against changes. master acknowledges byte with state line, protection next page read first following byte. master releases line, STOP condition complete read procedure. number bytes with page protection status first position requested master. uppermost page been addressed, counter overflow lowest address according first page.
Semiconductor Group
1999-02-02
24C164/P
Electrical Characteristics
listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage. Absolute Maximum Ratings
Stresses above those listed here cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this data sheet implied. Exposure absolute maximum ratings extended periods affect device reliability. Parameter Operating temperature Storage temperature Supply voltage inputs outputs with respect ground protection (human body model) Characteristics Symbol min. Supply voltage Supply current1) (write) Standby current2) Input leakage current Output leakage current Input voltage Input high voltage Limit Values typ. max. Units Test Condition range (industrial) range (automotive) Limit Values 4000 Units
Parameter
Inputs
VOUT
Semiconductor Group
1999-02-02
24C164/P
Characteristics (cont'd) Symbol min. Limit Values typ. max. Units Test Condition
Parameter Output voltage Input/output capacitance (SDA) Input capacitance (other pins)
CI/O
Capacitive load each line
values maximum peak values Valid over whole temperature range This parameter characterized only
Semiconductor Group
1999-02-02
24C164/P
Characteristics Symbol Limit Values Limit Values Units
Parameter
2.7-5.5
min. max. 1000
4.5-5.5
min.
max.
fSCL tlow Clock pulse width thigh Clock pulse width high rise time fall time tSU.STA Start set-up time tHD.STA Start hold time tSU.DAT Data set-up time tHD.DAT Data hold time data valid Data hold time tSU.STO Stop set-up time Time must free before tBUF
clock frequency transmission start spike suppression time constant inputs
minimum rise fall times calculated follows: (0.1/pF) [ns] Example: [ns]
Erase Write Characteristics Symbol Limit Values 2.7-5.5 typ. max. Limit Values Units 4.5-5.5 typ. max.
Parameter
Erase write cycle (per page) Erase page protection Write page protection
Semiconductor Group
1999-02-02
24C164/P
HIGH
SU.STA HD.STA
SU.DAT HD.DAT SU.STO
Start Condition
Stop Condition
IED02127
Figure Timing Data
Semiconductor Group
1999-02-02
24C164/P
Package Outlines P-DIP-8-3 (Plastic Dual In-line Package)
P-DSO-8-2 (Plastic Dual Small Outline Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Semiconductor Group
Dimensions 1999-02-02
GPS05473
GPD05696
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