SST39VF400 FEATURES: Organized Single 2.7-3.6V Read Write Operati

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SST39VF400 FEATURES: Organized Single 2.7-3.6V Read Write Operati

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Megabit (256K 16-Bit) Multi-Purpose Flash
SST39VF400
FEATURES: Organized Single 2.7-3.6V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Auto Power Mode: (typical) Small Sector-Erase Capability (128 sectors) Uniform KWord sectors Block-Erase Capability blocks) Uniform KWord blocks Fast Read Access Time: Latched Address Data Fast Erase Word-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 48-Pin TSOP (12mm 20mm) 48-Ball TFBGA
PRODUCT DESCRIPTION SST39VF400 device 256K CMOS MultiPurpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39VF400 writes (Programs Erases) with 2.7-3.6V power supply. SST39VF400 conforms JEDEC standard pinouts memories. Featuring high performance Word-Program, SST39VF400 device provides typical Word-Program time µsec. entire memory typically erased programmed word-by-word seconds, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, SST39VF400 on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST39VF400 offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39VF400 device suited applications that require convenient economical updating program, configuration, data memory. system applications, SST39VF400 significantly improves performance reliability, while lowering power consumption. SST39VF400 inherently uses less energy during Erase Program than alternative flash tech-
nologies. When programming flash device, total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. SST39VF400 also improves flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39VF400 offered 48-pin TSOP 48-ball TFBGA packages. Figures pinouts. Device Operation Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
1999 Silicon Storage Technology, Inc.The logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. 342-06 7/99 These specifications subject change without notice.
Megabit Multi-Purpose Flash SST39VF400
Advance Information SST39VF400 also Auto Power mode which puts device near standby mode after data been accessed with valid Read operation. This reduces active read current from typically typically Auto Power mode reduces typical active read current range mA/MHz read cycle time. device exits Auto Power mode with address transition control signal transition used initiate another read cycle, with access time penalty. Read Read operation SST39VF400 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure Word-Program Operation SST39VF400 programmed word-by-word basis. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored. Sector/Block-Erase Operation Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block) basis. SST39VF400 offers both small Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. address lines A11-A17 used determine sector address. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H)
1999 Silicon Storage Technology, Inc.
block address (BA) last cycle. address lines A15-A17 used determine block address. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase operation determined using either Data# Polling Toggle methods. Figures timing waveforms. commands issued during Sector Block-Erase operation ignored. Chip-Erase Operation SST39VF400 provides Chip-Erase operation, which allows user erase entire memory array state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. Write Operation Status Detection SST39VF400 provides software means detect completion Write (Program Erase) cycle, order optimize system write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST39VF400 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. device then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal
342-06 7/99
Megabit Multi-Purpose Flash SST39VF400
Advance Information Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector, Block Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart. Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 0's, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector, Block Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart. Data Protection SST39VF400 provides both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST39VF400 provides JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST39VF400 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 "Don't Care" during command sequence. Common Flash Memory Interface (CFI) SST39VF400 also contains information describe characteristics device. order enter Query mode, system must write three-byte sequence, same Software Entry command with (CFI Query command) address 5555H last byte sequence. Once device enters Query mode, system read data addresses given tables through system must write Exit command return Read mode from Query mode. Product Identification Product Identification mode identifies device SST39VF400 manufacturer SST. This mode accessed hardware software operations. hardware operation typically used programmer identify correct algorithm SST39VF400. Users wish Software Product Identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code 0000H 0001H Data 00BFH 2780H
T1.0
Product Identification Mode Exit/CFI Mode Exit order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/CFI Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
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342-06 7/99
Megabit Multi-Purpose Flash SST39VF400
Advance Information FUNCTIONAL BLOCK DIAGRAM
4,194,304 EEPROM Cell Array
X-Decoder
Address Buffer Latches Y-Decoder
DQ15
B1.1
Control Logic
Buffers Data Latches
Standard Pinout View
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 ILL1a.0
SST39VF400
FIGURE ASSIGNMENTS 48-PIN TSOP PACKAGES
VIEW
DQ15
DQ14 DQ13 DQ12 DQ10 DQ11
SST39VF400
ILL2a.4
FIGURE ASSIGNMENTS 48-BALL TFBGA
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Megabit Multi-Purpose Flash SST39VF400
Advance Information TABLE DESCRIPTION Symbol Name A17-A0 Address Inputs Functions provide memory addresses. During Sector-Erase A17-A11 address lines will select sector. During Block-Erase A17-A15 address lines will select block. output data during read cycles receive input data during write cycles. Data internally latched during write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide 3-volt supply (2.7-3.6V) Unconnected pins.
T2.1
DQ15-DQ0
Data Input/output
Chip Enable Output Enable Write Enable Power Supply Ground Connection
TABLE OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Hardware Mode Software Mode
DOUT High High DOUT High DOUT Manufacturer Code (00BF) Device Code (2780)
Address Sector Block address, Chip-Erase VIL, VIL, Table
T3.0
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Megabit Multi-Purpose Flash SST39VF400
Advance Information TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Addr(1) Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Addr(1) Data WA(3) 5555H 5555H 5555H Data Write Cycle Addr(1) Data Write Cycle Addr(1) Data
Word-Program Sector-Erase Block-Erase Chip-Erase Software Entry Query Entry Software Exit/ Exit Software Exit/ Exit Notes:
2AAAH 2AAAH 2AAAH
SAx(2) BAx(2) 5555H
2AAAH
5555H
T4.0
Address format A14-A0 (Hex), Addresses A15, A16, "Don't Care" Command sequence. Sector-Erase; uses A17-A11 address lines BAx, Block-Erase; uses A17-A15 address lines Program word address Both Software Exit operations equivalent DQ15 "Don't Care" Command sequence
Notes Software Entry Command Sequence With Manufacturer Code 00BFH, read with SST39VF400 Device Code 2780H, read with device does remain Software Product Mode powered down.
TABLE QUERY IDENTIFICATION STRING1 Address Data Data 0051H 0052H Query Unique ASCII string "QRY" 0059H 0001H Primary command 0007H 0000H Address Primary Extended Table 0000H 0000H Alternate command (00H none exists) 0000H 0000H Address Alternate extended Table (00H none exits) 0000H
Note Refer publication more details.
T5.1
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Megabit Multi-Purpose Flash SST39VF400
Advance Information TABLE SYSTEM INTERFACE INFORMATION Address Data Data 0027H Min. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts 0036H Max. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts 0000H min. (00H pin) 0000H max. (00H pin) 0004H Typical time Word-Program 0000H Typical time min. size buffer program (00H supported) 0004H Typical time individual Sector/Block-Erase 0006H Typical time Chip-Erase 0001H Maximum time Word-Program times typical 0000H Maximum time buffer program times typical 0001H Maximum time individual Sector/Block-Erase times typical 0001H Maximum time Chip-Erase times typical
T6.2
TABLE DEVICE GEOMETRY INFORMATION Address Data Data 0013H Device size Byte (13H KBytes) 0001H Flash Device Interface description; 0001H x16-only asynchronous interface 0000H 0000H Maximum number byte multi-Byte-Write (00H supported) 0000H 0002H Number Erase Sector/Block sizes supported device 007FH Sector Information Number sectors; 256B sector size) 0000H sectors (007FH 127) 0010H 0000H Bytes KBytes/sector (0010H 0007H Block Information Number blocks; 256B block size) 0000H blocks (0007H 0000H 0001H Bytes KBytes/block (0100H 256)
T7.2
1999 Silicon Storage Technology, Inc.
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Megabit Multi-Purpose Flash SST39VF400
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial Industrial
3.6V 3.6V
CONDITIONS TEST Input Rise/Fall Time Output Load Figures
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Megabit Multi-Purpose Flash SST39VF400
Advance Information TABLE OPERATING CHARACTERISTICS 2.7-3.6V Limits Symbol Parameter Power Supply Current Read Program Erase Standby Current Auto Power Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage Supervoltage 11.4 Supervoltage Current
Units
Test Conditions CE#=OE#=VIL,WE#=VIH I/Os open, Address input VIL/VIH, f=1/TRC Min. CE#=WE#=VIL, OE#=VIH, VDD=VDD Max. CE#=VIHC, Max. CE#=VILC, I/O=VILC/VIHC, Max. =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Max. Min. -100 Min. =VIL, VIL, VIH, Max.
T9.3
T10.0
IALP VILC VIHC
12.6
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
Minimum
Units
Power-up Read Operation Power-up Program/Erase Operation
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O
Maximum
T11.1
Capacitance Input Capacitance
VI/O
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Units Cycles Years Volts Volts Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T12.1
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
10,000 1000
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
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Megabit Multi-Purpose Flash SST39VF400
Advance Information CHARACTERISTICS TABLE SST39VF400 READ CYCLE TIMING PARAMETERS 2.7-3.6V SST39VF400-70 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time TCLZ Active Output TOLZ Active Output TCHZ(1) High High-Z Output TOHZ High High-Z Output Output Hold from Address Change
SST39VF400-90
Units
T13.3
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Word-Program Time Address Setup Time Address Hold Time Setup Time Hold Time TOES High Setup Time TOEH High Hold Time Pulse Width Pulse Width TWPH Pulse Width High TCPH Pulse Width High Data Setup Time Data Hold Time TIDA Software Access Exit Time Sector-Erase Block-Erase TSCE Chip-Erase
Units
T14.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
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Megabit Multi-Purpose Flash SST39VF400
ADDRESS A17-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
ILL3.0
DQ15-0
HIGH-Z
TCLZ
DATA VALID
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) TWPH 2AAA 5555 ADDR
ILL4.1
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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Megabit Multi-Purpose Flash SST39VF400
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) TCPH 2AAA 5555 ADDR
ILL5.1
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A17-0 TOEH TOES
DATA
DATA#
DATA#
DATA
ILL6.2
FIGURE DATA# POLLING TIMING DIAGRAM
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Megabit Multi-Purpose Flash SST39VF400
ADDRESS A17-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS ILL7.2
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE TSCE 5555
ADDRESS A17-0
5555
2AAA
5555
5555
2AAA
DQ7-0
ILL8.2
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minmum timings met. (See Table
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
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Megabit Multi-Purpose Flash SST39VF400
SIX-BYTE CODE BLOCK-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA
DQ7-0
F17.2
Note: This device also supports controlled Block-Erase operation. signals interchageable long minmum timings met. (See Table Block Address
FIGURE CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA
DQ7-0
ILL18.2
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minmum timings met. (See Table Sector Address
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
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Megabit Multi-Purpose Flash SST39VF400
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
TIDA
TWPH DQ15-0 XXAA XX55 XX90
ILL9.1
00BF 2780
FIGURE SOFTWARE ENTRY READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
TWPH DQ15-0 XXAA XX55 XX98
ILL20.1
TIDA
FIGURE QUERY ENTRY READ
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Megabit Multi-Purpose Flash SST39VF400
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
ILL10.0
FIGURE SOFTWARE EXIT/CFI EXIT
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Megabit Multi-Purpose Flash SST39VF400
VIHT
INPUT REFERENCE POINTS
OUTPUT
ILL11.0
VILT
test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Inputs rise fall times (10% 90%)
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
ILL12.0
FIGURE TEST LOAD EXAMPLE
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Megabit Multi-Purpose Flash SST39VF400
Start
Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 5555
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
ILL13.2
FIGURE WORD-PROGRAM ALGORITHM
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Megabit Multi-Purpose Flash SST39VF400
Internal Timer Program/Erase Initiated Toggle Program/Erase Initiated Data# Polling
Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Read same word true data? Does match? Program/Erase Completed Program/Erase Completed
Program/Erase Completed
ILL14.1
FIGURE WAIT OPTIONS
1999 Silicon Storage Technology, Inc.
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Megabit Multi-Purpose Flash SST39VF400
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAA Address: 5555
Load data: XXAA Address: 5555
Load data: XXAA Address: 5555
Load data: XXF0 Address:
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Wait TIDA
Load data: XX98 Address: 5555
Load data: XX90 Address: 5555
Load data: XXF0 Address: 5555
Return normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
ILL15.1
FIGURE SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
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Megabit Multi-Purpose Flash SST39VF400
Chip-Erase Command Sequence Load data: XXAA Address: 5555
Sector-Erase Command Sequence Load data: XXAA Address: 5555
Block-Erase Command Sequence Load data: XXAA Address: 5555
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Load data: XX80 Address: 5555
Load data: XX80 Address: 5555
Load data: XX80 Address: 5555
Load data: XXAA Address: 5555
Load data: XXAA Address: 5555
Load data: XXAA Address: 5555
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Load data: XX55 Address: 2AAA
Load data: XX10 Address: 5555
Load data: XX30 Address:
Load data: XX50 Address:
Wait TSCE
Wait
Wait
Chip erased
Sector erased
Block erased
ILL16.3
FIGURE ERASE COMMAND SEQUENCE
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Megabit Multi-Purpose Flash SST39VF400
Advance Information Device SST39VF400 Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type TSOP (12mm 20mm) TFBGA (0.8 pitch; 10mm) Unencapsulated Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed Voltage 2.7-3.6V
SST39VF400 Valid combinations SST39VF400-70-4C-EK SST39VF400-70-4C-BK SST39VF400-90-4C-EK SST39VF400-90-4C-BK SST39VF400-70-4I-EK SST39VF400-90-4I-EK SST39VF400-70-4I-BK SST39VF400-90-4I-BK
SST39VF400-90-4C-U1
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
1999 Silicon Storage Technology, Inc.
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Megabit Multi-Purpose Flash SST39VF400
Advance Information PACKAGING DIAGRAMS
IDENTIFIER 1.05 0.95
.270 .170
12.20 11.80
18.50 18.30
0.15 0.05
0.70 0.50 20.20 19.80
BOTTOM VIEW
CORNER 0.30 0.05 (48X)
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05) 48.TSOP-EK-ILL.2
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
VIEW CORNER
10.00 0.20 5.60 0.80
SIDE VIEW
0.15
0.80 4.00 8.00 0.20
SEATING PLANE 0.21 0.05 1.10 0.10
48pn TFBGA.8x10-ILL.3
Note:
Complies with JEDEC publication MO-210, (proposed) dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05)
48-BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) PACKAGE CODE:
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Megabit Multi-Purpose Flash SST39VF400
SALES OFFICES
Area Offices
Customer Service Northwest USA, Rocky Mtns. West Canada Southwest East East Canada Corporate Accounts North America Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7754 (408) 523-7661 (949) 495-6437 (978) 356-3845 (727) 771-8819 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000
International Sales Representatives Distributors
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(61) 3-762 7644 (43) 2-236236-21 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (45) 7010-4888 (358)9 8880 (33) 0414 (33) 7900
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Revised 8-9-99
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
342-06 7/99

SST39VF400 FEATURES: Organized Single 2.7-3.6V Read Write Operati

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