SST39LH512 SST39LH010 SST39LH020 SST39LH040 FEATURES: Organized 1

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SST39LH512 SST39LH010 SST39LH020 SST39LH040 FEATURES: Organized 1

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Kbit Mbit Mbit Mbit High Speed Multi-Purpose Flash
SST39LH512 SST39LH010 SST39LH020 SST39LH040
FEATURES: Organized 128K 256K 512K Single 3.0-3.6V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector Erase Capability Uniform KByte sectors Fast Read Access Time: SST39LH512 SST39LH010 SST39LH512 SST39LH010 SST39LH020 SST39LH040 Latched Address Data Fast Sector Erase Byte Program: Sector Erase Time: typical Chip Erase Time: typical Byte Program time: typical Chip Rewrite Time: second typical SST39LH512 seconds typical SST39LH010 seconds typical SST39LH020 seconds typical SST39LH040 Automatic Write Timing Internal Generation Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-Pin PLCC 32-Pin TSOP (8mm 14mm) nologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. SST39LHxxx device also improves flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose erase program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39LHxxx device offered 32-pin TSOP 32pin PLCC packages. Figures pinouts. Device Operation Commands used initiate memory operation functions device. Commands issued device using standard microprocessor write sequences. command loaded asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
PRODUCT DESCRIPTION SST39LHxxx CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39LHxxx device writes (Program Erase) with 3.0-3.6V power supply. SST39LHxxx device conforms JEDEC standard pinouts memories. Featuring high performance byte program, SST39LHxxx device provides maximum byte-program time µsec. device uses Toggle Data# Polling detect completion Program Erase operations. protect against inadvertent write, SST39LHxxx device on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST39LHxxx device offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39LHxxx device suited applications that require convenient economical updating program, configuration, data memory. system applications, SST39LHxxx device significantly improves performance reliability, while lowering power consumption. SST39LHxxx inherently uses less energy during erase program than alternative flash tech-
1999 Silicon Storage Technology, Inc.The logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. 351-04 5/99 These specifications subject change without notice.
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information Read Read operation SST39LHxxx device controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure Byte Program Operation SST39LHxxx device programmed byte-bybyte basis. Program operation consists three steps. first step three-byte-load sequence Software Data Protection. second step load byte address byte data. During Byte Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored. Sector Erase Operation Sector Erase operation allows system erase device sector sector basis. sector architecture based uniform sector size KByte. Sector Erase operation initiated executing six-byte-command load sequence Software Data Protection with Sector Erase command (30H) sector address (SA) last cycle. sector address latched falling edge sixth pulse while command (30H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase operation determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Sector Erase operation will ignored. Chip Erase Operation SST39LHxxx device provides Chip Erase operation, which allows user erase entire memory array "1's" state. This useful when entire device must quickly erased. Chip Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth CE#, whichever occurs first. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip Erase operation will ignored. Write Operation Status Detection SST39LHxxx device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST39LHxxx device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. device then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector Chip Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector Chip Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart. Data Protection SST39LHxxx device provides both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST39LHxxx provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three byte sequence. three byte-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion byte load sequence. SST39LHxxx device shipped with Software Data FUNCTIONAL BLOCK DIAGRAM SST39LHXXX
EEPROM Cell Array
Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC. Product Identification Product Identification mode identifies device SST39LHxxx manufacturer SST. This mode accessed hardware software operations. hardware operation typically used programmer identify correct algorithm SST39LHxxx device. Users wish Software Product Identification operation identify part (i.e., using device code) when using multiple manufacturers' devices same socket. details, Table hardware operation Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code SST39LH512 Device Code SST39LH010 Device Code SST39LH020 Device Code SST39LH040 0000H 0001H 0001H 0001H 0001H Data
T1.1
Product Identification Mode Exit/Reset order return standard Read mode, Software Product Identification mode must exited. Exiting accomplished issuing Software Exit command sequence, which returns device Read mode. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
X-Decoder
Memory Address
Address Buffers Latches Y-Decoder
B1.1
Control Logic
Buffers Data Latches
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
SST39LH512 SST39LH010 SST39LH020 SST39LH040
SST39LH040 SST39LH020 SST39LH010 SST39LH512
Standard Pinout View
FIGURE ASSIGNMENTS 32-PIN TSOP PACKAGE (8mm 14mm)
F01.2
SST39LH040 SST39LH020 SST39LH010 SST39LH512
SST39LH512 SST39LH010 SST39LH020 SST39LH040
SST39LH040 SST39LH020 SST39LH010 SST39LH512
SST39LH512 SST39LH010 SST39LH020 SST39LH040
32-Lead PLCC View
F02.2
FIGURE ASSIGNMENTS 32-PIN PLCC
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information TABLE DESCRIPTION Symbol Name AMS-A0 Address Inputs DQ7-DQ0 Data Input/output Functions provide memory addresses. During sector erase AMS-A12 address lines will select sector. output data during read cycles receive input data during write cycles. Data internally latched during write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control write operations. provide 3.0-3.6V supply
T2.2
Note:
Chip Enable Output Enable Write Enable Power Supply Ground
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
TABLE OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Hardware Mode Software Mode
Notes:
DOUT High High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code Code
Address Sector address, chip erase AMS(2) VIL, AMS(2) VIL, Table
T3.2
SST39LH512, SST39LH010, SST39LH020, SST39LH040 Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information TABLE SOFTWARE COMMAND SEQUENCE
Write Cycle Addr(1) Data Byte Program 5555H Sector Erase 5555H Chip Erase 5555H Software Entry 5555H Software Exit(4) Software Exit(4) 5555H
Notes: Address format A14-A0 (Hex), Address "Don't Care" Command sequence SST39LH512. Addresses "Don't Care" Command sequence SST39LH010. Addresses A15, "Don't Care" Command sequence SST39LH020. Addresses A15, A16, "Don't Care" Command sequence SST39LH040. sector erase; uses address lines, SST39LH512, SST39LH010, SST39LH020, SST39LH040, Most significant address Program Byte address Both Software Exit operations equivalent Notes Software Entry Command Sequence With Manufacturer Code BFH, read with SST39LH512 Device Code D4H, read with SST39LH010 Device Code D5H, read with SST39LH020 Device Code D6H, read with SST39LH040 Device Code D7H, read with device does remain Software Product Mode powered down.
Command Sequence
Write Cycle Addr(1) Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H
Write Cycle Addr(1) Data BA(3) Data 5555H 5555H
Write Cycle Addr(1) Data 2AAAH 2AAAH
Write Cycle Addr(1) Data SAx(2) 5555H
T4.2
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial
CONDITIONS TEST 3.6V Input Rise/Fall Time Output Load Figures
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information TABLE OPERATING CHARACTERISTICS 3.0-3.6V Limits Symbol Parameter Power Supply Current Read Write Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage VDD-0.2 Supervoltage 11.4 Supervoltage Current
Units
Test Conditions CE#=OE#=VIL,WE#=VIH I/Os open, Address input VIL/VIH, f=1/TRC Min., VDD=VDD CE#=WE#=VIL, OE#=VIH, =VDD Max. CE#=VIHC, Max. =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Min. -100µA, Min. =VIL, VIL, VIH, Max.
T5.2
VIHC
12.6
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
Minimum
Units
T6.0
Power-up Read Operation Power-up Write Operation
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O(1) CIN(1) Capacitance Input Capacitance VI/O
Maximum
T7.0
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.1
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
10,000 2000
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information CHARACTERISTICS TABLE READ CYCLE TIMING PARAMETERS 3.0-3.6V SST39LH512-55 SST39LH010-55 SST39LH020-55 SST39LH040-55
Units
T9.2
Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1)
Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST39LH512-45 SST39LH010-45
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Byte Program time Address Setup Time Address Hold Time Setup Time Hold Time TOES High Setup Time TOEH High Hold Time Pulse Width Pulse Width TWPH Pulse Width High TCPH Pulse Width High Data Setup Time Data Hold Time TIDA Software Access Exit Time Sector Erase TSCE Chip Erase
Note:
(1)This
Units
T10.0
parameter measured only initial qualification after design process change that could affect this parameter.
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
ADDRESS AMS-
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
DATA VALID
F03.2
Note:
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS 5555 DQ7-0 DATA BYTE (ADDR/DATA) TWPH 2AAA 5555 ADDR
F04.2
Note:
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
INTERNAL PROGRAM OPERATION STARTS ADDRESS 5555 DQ7-0 DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.2
Note:
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS TOEH TOES
F06.2
Note:
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE DATA# POLLING TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
ADDRESS TOEH TOES
READ CYCLES WITH SAME OUTPUTS F07.2
Note:
Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR ERASE ADDRESS 5555 2AAA 5555 5555 2AAA
DQ7-0
Note:
F08.2
This device also supports controlled Sector Erase operation. signals interchageable long minmum timings met. (See Table Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE CONTROLLED SECTOR ERASE TIMING DIAGRAM
1999 Silicon Storage Technology, Inc. 351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
SIX-BYTE CODE CHIP ERASE ADDRESS 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ7-0
Note:
F17.2
This device also supports controlled Chip Erase operation. signals interchageable long minmum timings met. (See Table Most significant address SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE CONTROLLED CHIP ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0
F09.1
TIDA
Device
Note:
Device SST39LH512, SST39LH010, SST39LH020, SST39LH040
FIGURE SOFTWARE ENTRY READ
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
F10.0
FIGURE SOFTWARE EXIT
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
VIHT
INPUT REFERENCE POINTS
OUTPUT
F11.0
VILT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.7 VDD) (0.8 Input rise fall times (10% 90%)
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.0
FIGURE TEST LOAD EXAMPLE
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Start
Write data: Address: 5555
Write data: Address: 2AAA
Write data: Address: 5555
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F13.0
FIGURE BYTE PROGRAM ALGORITHM
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Internal Timer Byte Program/Erase Initiated Toggle Byte Program/Erase Initiated Data# Polling Byte Program/Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Read same byte true data? Does match?
Program/Erase Completed
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Write data: Address: 5555
Write data: Address: 5555
Write data: Address:
Write data: Address: 2AAA
Write data: Address: 2AAA
Wait TIDA
Write data: Address: 5555
Write data: Address: 5555
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.0
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Chip Erase Command Sequence
Write data: Address: 5555
Sector Erase Command Sequence
Write data: Address: 5555
Write data: Address: 2AAA
Write data: Address: 2AAA
Write data: Address: 5555
Write data: Address: 5555
Write data: Address: 5555
Write data: Address: 5555
Write data: Address: 2AAA
Write data: Address: 2AAA
Write data: Address: 5555
Write data: Address:
Wait TSCE
Wait
Chip erased Sector erased
F16.0
FIGURE ERASE COMMAND SEQUENCE
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information Device SST39LHXXX Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type PLCC TSOP (die (8mm 14mm) Temperature Range Commercial 70°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Kilobit Megabit Megabit Megabit Family High Speed Family Voltage 3.0-3.6V
SST39LH512 Valid combinations SST39LH512-45-4C-WH SST39LH512-45-4C-NH SST39LH512-55-4C-WH SST39LH512-55-4C-NH SST39LH010 Valid combinations SST39LH010-45-4C-WH SST39LH010-45-4C-NH SST39LH010-55-4C-WH SST39LH010-55-4C-NH SST39LH020 Valid combinations SST39LH020-55-4C-WH SST39LH020-55-4C-NH SST39LH040 Valid combinations SST39LH040-55-4C-WH SST39LH040-55-4C-NH
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information PACKAGING DIAGRAMS
VIEW
SIDE VIEW
BOTTOM VIEW
Optional Identifier
.485 .495 .447 .453 .042 .048
.106 .112 .020 MAX. .023 .029 .030 .040
.490 .530
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
32.PLCC.NH-ILL.1
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
1.05 0.95
IDENTIFIER
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.2
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
Advance Information NOTES:
1999 Silicon Storage Technology, Inc.
351-04 5/99
High Speed Multi-Purpose Flash SST39LH512 SST39LH010 SST39LH020 SST39LH040
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(49) 4192-897910 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (47) (65) 748-4844 (65) 280-0200 (27) 845-5011 (34) 371-7768 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 5-4-99
India Team Technology Bangalore Team Technology Hyderabad Team Technology Delhi Ireland Curragh Technology Israel Spectec Electronics Italy Carlo Gavazzi Cefra Japan Asahi Electronics Co., Ltd. Tokyo Asahi Electronics Co., Ltd. Kitakyushu
Microtek, Inc. Osaka Microtek, Inc. Tokyo Ryoden Trading Co., Ltd. Osaka Ryoden Trading Co., Ltd. Tokyo Silicon Technology Co., Ltd.
Korea Bigshine Korea Co., Ltd. Malaysia MetaTech
Serial System Serial System Kuala Lumpur
Netherlands Memec Benelux Norway Endrich Elektronikk Singapore MetaTech Ltd.
Serial System Ltd. (HQ)
South Africa Distributors Spain Tekelec Espana S.A. Switzerland Leading Technologies Taiwan, R.O.C. GCH-Sun Systems Co., Ltd. (GSS) Limited Tonsam Corporation United Kingdom Ambar Components, Ltd.
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
351-04 5/99

SST39LH512 SST39LH010 SST39LH020 SST39LH040 FEATURES: Organized 1

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