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MPC860 Table Contents
Welcome! Getting Started CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER MPC860 Architecture, Part EPPC Programming Accessing Operands Memory Using Caches Memory Management Unit EPPC Exception Processing MPC860 Architecture, Part Serial Communications Controller (SCC), Parameter RAM, Buffer Descriptors, UART Example More UART Protocol HDLC Protocol Ethernet Protocol Serial Interface with Time Slot Assigner Mode 860MH MPC860 Serial Management Channel (SMC) MPC860 Serial Peripheral Interface (SPI) Port Configuration Virtual IDMA Interrupt Controller Interrupt Controller
CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER
CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER
Memory Controller MPC860 Reset Controller General Purpose Timer Other Timers Clocks Power Control Pins Development Support
Welcome
Slide Welcome!
Motorola would like welcome MPC860 Training CDROM! hope that this will valuable tool educating yourself operation MPC860. Certainly train yourself before begin your design, should also prove handy reference once your design underway. This training should introduce wealth information designer well serve collection insights reinforce knowledge experienced engineer.
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through training sequentially were taking class random access reference sure take advantage useful functions Before starting your design review "Getting Started"
There many ways which might want this training. information been arranged sequential fashion, desire, proceed through course from start finish though were actually taking class. also possible Table Contents Keyword Index randomly access material were thumbing through manual. this application, sure make additional functions such playback control. Have ever through class which instructor' last comment simply didn' sink Now, playback control restart audio given slide many times wish. even want back presentation several slides make sure fully understand subject. lecture moving slow you? Jump ahead next slide you' sure current holds knowledge you. taking little while comprehend current diagram? Pause'button review slide until comfortable with Then proceed with narration. also provide reference materials chapter. current slide discussing something that want more detail about, then bringing reference file allows look over relevant sections user manuals application notes Another useful function ability print slide currently files script slides also included this you, perhaps want hard copy what looking right now, take into reference. Then option print bitmapped slide from within program. There more functionality available than just examples using here. Please sure review instructions program well readme file included with this training become familiar with functionality available you. Before device training begins, included collection thoughts that help guide your design. Getting Started with MPC860'chapter contains information acquire
different resources that available engineers MPC860 applications, includes step-by-step tips factors consider before begin your design.
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sincere hope that will find this training program beneficial some ways attending class; perhaps given random access reference nature, even more wish best luck with your design, thank choosing Motorola. now, training!
GETTING STARTED WITH
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Getting Started with MPC860 Once again, welcome designing with Motorola' MPC860 PowerQUICC! would like thank choosing Motorola processor. Motorola understands that field integrated communications controllers, have choice. proud have your business. Before proceed with training course, like introduce some resources available designer. Then offer step-by-step guide developing hardware software 860, point materials that support your efforts.
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http://www.mot.com/netcomm best keep with resources availble you!
World Wide fast become most efficient provide wide variety support materials customers. invite visit home http://www.mot.com/netcomm main NetComm home page tends highlight additions page also contains links other sections site. designer, more likely that will find three other areas page most valuable: Engineer's Toolbox, Publications Library, Support area. ENGINEER'S TOOLBOX Click TOOLBOX example code, schematics, monitor packages, part models, initialization tools, more. Files tend provided ZIP-compressed format format Adobe's Acrobat Reader. PUBLICATIONS LIBRARY Click PUBLICATIONS LIBRARY collection users manuals, technical summaries, application notes "appnotes"), user manual errata (listed manual addendums). Also this section will find user's manuals software, downloadable microcode packages, development systems. SUPPORT Click SUPPORT find latest device errata, well find information subscribe Mailing Lists which periodically broadcasts device news.
Frequently Asked Questions (FAQ) page provides search engine that gives power parse through actual helpline database issues products, accumulated over years experience. lose valuable time-to-market investigating your design someone already asked about same issue? When doubt, check using FAQ. Bookmark link http://www.mot.com/netcommfaq directly search engine.
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Available Literature
MPC860 User's Manual
most comprehensive guide device Document MPC860UM/AD PowerPC Microprocessor Family: Programming Environments 32-Bit Microprocessors Document MPCFPE32B/AD
NetComm General Information CDROM
Item CDRONETCOM/D
Available Literature MPC860 PowerQUICC USER'S MANUAL MPC860 User's Manual provides most detailed information about part operation. From capabilities programming models interfaces, this must-have anyone working with 860. manual's document number MPC860UM/AD manual obtained electronic format from Publications Area page through Literature Distribution Center (discussed shortly). pleased announce that time this training CDROM's release, making available edition User's Manual. This edition updated tables diagrams, improved organization material, sections that better illustrate operation part reader. PowerPC 32-Bit MICROPROCESSOR MANUAL This manual complements MPC860 PowerQUICC User's Manual going into great detail such topics PowerPC register set, exceptions, PowerPC instruction set. document number MPCFPE32B/AD.
NETCOMM GENERAL INFORMATION CD-ROM Tired downloading large documents from web-site? offer user's manuals large software packages such MCUinit processor initialization tool CD-ROM format. While everything that contained this CD-ROM also located web, this disc more convenient those customers with low-bandwidth access internet. This disc obtained contacting Motorola's Literature Distribution Center using methods described moment, requesting item CDRONETCOM/D. downloading smaller documents, documents which could change frequently.
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Literature Distribution Center (LDC)
(subject change)
USA/Europe/Locations Listed P.O. 5405, Denver, Colorado 80217 1-800-441-2447 1-303-675-2140 Japan Nippon Motorola Ltd.: Strategic Planning Office 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan 81-3-5487-8488 Asia/Pacific Motorola Semiconductors H.K. Ltd. Ping Industrial park Ting Road, Hong Kong 852-26629298
Literature Distribution Center Hard copies manuals CD-ROMs obtained contacting Motorola Semiconductor Product Sector's Literature Distribution Center (LDC). LDC's page currently accessed through Literature Retrieval area Additional contact information shown here.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
MPC860 right your application?
Look MPC860 variations
"Products" area webpage
Obtain User Manuals
Derivatives MPC860 still need main MPC860UM well appropriate supplement Derivatives MPC850 should main MPC850 manual well appropropriate supplement Contains overview featuresets
Read introduction section
Step-by-Step Guide Designing with MPC860 RIGHT YOUR APPLICATION? With complexity chips these days, take time make sure that given chip right your board. Here some steps take make sure MPC860 right you. Look MPC860 variations. http://www.mot.com/netcomm click PRODUCTS icon. PRODUCTS page will list MPC860 variations. Click variations will table that illustrates differences between versions. Obtain right user's manuals. MPC860 family members require MPC860UM/AD which available from web, from ROM, from Literature Distribution Center. want information MPC860MH, MPC860DH will also need User's Manual supplement. need MPC860SAR, will want supplement. want MPC860T, will want supplement that shows differences between base MPC860 that particular device. looking MPC850 family members, would start with base MPC850 manual instead MPC860 manual. Read introduction section user's manuals. This will give overview features chips. looking MPC860DC (dual channel device) MPC860DE (dual Ethernet) devices, then MPC860 base manual still applies, only SCC1 SCC2 available. SCC3 SCC4 pins still used parallel ports, SCC3 SCC4 non-functional.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
MPC860 right your application?
Choose right part your communication functions
Let's want Ethernet, HDLC UART This rules plain MPC860 does have Ethernet HDLC multi-channel need MPC860MH, MPC860DH, MPC850DH because these have QUICC Multichannel Protocol functionality MPC860MH does more than need, MPC850DH have performance Let's MPC860DH example (SCC1=Ethernet,SCC2=QMC, SMC1 SMC2=UART)
STEP STEP: RIGHT YOUR APPLICATION? Choose Right Part your Communications Functions next area investigate whether communications functions MPC860 right your application. Decide what serial functions want accomplish same time. example want Ethernet, HDLC UART. could assign Ethernet SCC1, HDLC SCC2, UART SCC3. Since Ethernet choices, this rules "MPC860", leaving MPC860DC, MPC860DE, MPC860DH, MPC860EN MPC860MH. HDLC support multi-channel such 24/32 time slots fractional T1/E1 several ISDN BRI's, this narrows choice MPC860DH MPC860MH. This protocol called Quicc Multichannel Controller (QMC) documentation. choices become: MPC860MH using Ethernet SCC1, Multi-channel HDLC (also called QMC) SCC2, UART SCC3. wait, MPC860DH only SCCs! used? Yes, because SMCs also, which capable speed UARTs! MPC860DH also possible with Ethernet SCC1, Multichannel HDLC SCC2, UART either SMC1 SMC2. Finally, should noted that functions SCC1 SCC2 switched needed parts that offer Ethernet more than channel such MPC860MH MPC860DH.
What about MPC850? used. MPC850DH offers less performance less capable communications functions, necessary functions still mapped similar MPC860DH. From reading section MPC850DH manual, will that even though this part SCCs, they actually "SCC2 SCC3" since SCC1 replaced with dedicated controller. addition MPC850DH only that connected pins, only SMC1 possible. Conclusion: far, most realistic options this application MPC860DH MPC850DH. both used? probably depends performance required, which discussed later. now, let's stick with MPC860DH example. Slide GS-7
STEP-BY STEP GUIDE DESIGNING WITH MPC860
MPC860 right your application?
Check Pinout Desired Part
Ethernet requires:
TXD1 TENA RTS1) TCLK unused from CLK1-CLK4) RXD1 RENA CD1) RCLK unused from CLK1-CLK4) CLSN CTS1)
requires (where
L1TXDx L1RXDx L1TCLKx L1RCLKx L1TSYNCx L1RSYNCx
SMC1 requires: SMTXD1, SMRXD1 SMC2 requires: SMTXD2, SMRXD2
We'll requires CLK1 CLK3 pins Therefore, Ethernet will CLK2 CLK4 pins We'll arbitrarily pick SMC1
STEP STEP: RIGHT YOUR APPLICATION? Check Pinout Desired Part example, need make sure that MPC860DH will allow pins operating simultaneously support configuration. reading Ethernet section manual shows that following pins required Ethernet used SCC1: TXD1 TENA which mapped onto RTS1 TCLK which must mapped CLK1, CLK2, CLK3 CLK4 RXD1 RENA which mapped onto RCLK which must mapped CLK1, CLK2, CLK3 CLK4, must different than used TCLK above
CLSN which mapped onto CTS1 Signals Description Manual look those signals circle them. Multi-Channel HDLC support. This requires time-slot assigner time-slot assigner Which should use? either whichever makes rest assignment easier. this example, lets assume that receive transmit sides completely independent therefore require their separate clocks synchronization pins. Then pins need follows: Choice requires L1TXDA L1RXDA L1TCLKA L1RCLKA L1TSYNCA L1RSYNCA Choice requires L1TXDB L1RXDB L1TCLKB L1RCLKB L1TSYNCB L1RSYNCB Note that these pins easily distinguished from other functions because they start with (Layer only clock sync needed then only L1RCLKx L1RSYNCx would used. Signals Description manual look these signals circle them. example, will choose rather than What will notice that L1RCLKA alternate function CLK1 L1TCLKA alternate function CLK3. Thus, should back Ethernet selections above, choose CLK2 CLK4 there conflict. Another interesting thing note that L1TSYNCA L1RSYNCA available places device! pick either location, select later your software initialization. this? case studies did, found that certain applications required this kind flexibility, otherwise would have added this extra complication device! Lastly, need select UART. Either SMC1 SMC2. Thus choices are: SMTXD1and SMRXD1, SMTXD2 SMRXD2. Note that SMCs means that have RTS, functions. must have those functions, software interrupts sufficient, then must used, putting application back MPC860MH rather than MPC860DH.) examination pinout reveals that indeed, everything fits MPC860DH, really didn't matter which chose, which chose this case. start more channels, more "optional" signals certain interfaces, chances contention increases.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
MPC860 right your application?
Check Dual-port Desired Part
Certain complex protocols DPRAM other functions Check microcodes that patch situation
Check Performance
Performance spreadsheet web! Performance Appendix Example Calculations:
10/22 (Ethernet) (HDLC) ~.70 This will work!
0.064)/2.1 (QMC) (HDLC) =1.22 1.22 25/33 0.92
This greater than definitely will work!
greater operating speed, just squeeze
STEP STEP: RIGHT YOUR APPLICATION? Check Dual-port Desired Part know that MPC860DH supports simultaneous pins need. What next resource that could problem? answer Dual-port RAM. Each protocol requires certain parameters that stored dual-port RAM. case certain complicated protocols like Ethernet Multi-HDLC parameter requirement large that actually overruns parameter other protocols. example Ethernet SCC1 overruns area, SCC2 overruns area. solve this have several downloadable microcodes that "patch" this problem moving parameter other locations. This called "Microcode Patch Relocating 12C/SPI Parameters" available from ENGINEERS TOOLBOX web-site.
Check Performance that pins dual-port requirements checked application, need check that Communications Processor Module (CPM) performance sufficient application. method used determine this illustrated User's Manual Appendix involves simple equation based upon system clock speed 860, well protocols required their speeds. This Appendix lists maximum expected performance each kind functionality provides. This chart scales linearly, example, intend 50MHz, then these maximum bandwidth numbers also double. also offer Excel spreadsheet called "CPM Performance Spreadsheet" that performs these loading calculations located Engineer's Toolbox page. This very useful tool!
perform these calculations hand, simply divide intended bandwidth certain protocol maximum, repeat additional functions will using, these fractions together, exceed This topic covered more detail training, let's quick example illustrate what describing. were operating 25MHz, would using 10Mbit Ethernet channel half duplex 2Mbit HDLC channel, would take these bandwidths, divide them each protocol, them follows: 10/22 0.70 which comes close does exceed processor would overloaded. were attempt channels Kbit each additional 2Mbit channel with 25MHz, following equation applies: 0.064)/2.1 =1.22 This arrangement will work. can, however, keep this arrangement increase operating speed 33MHz, example.
1.22 25/33 0.92
overloaded.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
MPC860 right your application?
Check PowerPCCPU Performance
Mhz, performed Dhrystone MIPS MHz, performed Dhrystone MIPS MHz, performed 52.8 Dhrystone MIPS MHz, performed 43.56 Dhrystone MIPS MHz, performed Dhrystone MIPS These numbers were obtained with Diab Compiler.
Price Availability
Check with your local distributor Motorola representative
STEP STEP: RIGHT YOUR APPLICATION? Check PowerPC Performance last main area concern Core Performance. offers following Dhrystone MIPS performance shown here. These numbers were obtained with Diab Compiler. good news about Dhrystone benchmark that results available from wide variety processors. news about Dhrystone benchmark that fits completely internal cache instructions greater. Thus, Dhrystone benchmark shows 4K/4K (instruction cache/data cache size) MPC860 family same speed 2K/1K MPC850 family. actuality performance MPC860 10-35% greater than MPC850 family same clock speed. Another metric commonly used MPC860 that this processor about faster than 68040 processor same clock speed (which also 4K/4K cache). Finally, TOOLBOX offers benchmark "shell" which allows benchmark your code processor. This shell code initializes chip, turns Caches, starts timer you. also shows where place your "test code" long takes run. example code that included this shell Dhrystone code.
Price Availability This information available site, check with your local distributor Motorola representative. Motorola's main distributors Arrow, Future, Hamilton-Hallmark Wyle. site does contain press releases which show "direct from Motorola" pricing time device announcement, however pricing does change drastically with volume with time.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
Hardware Designers
Determine Memory System Will Need
Appnote: MPC860 Interface Fast Page Mode DRAM Appnote: Appnote: MPC860 Interface DRAM Appnote: Appnote: MPC860 Interface Synchronous DRAM Appnote:
STEP-BY-STEP GUIDE HARDWARE DESIGNERS that have decided actually MPC860 design, following steps recommended. Determine memory system will need. MPC860 bursting device thus obtains best performance when memory connected also able burst. MPC860 burst comprised four 32-bit words. length burst written 4-2-2-2, then first 32-bits were read/written clocks, next 32-bits clocks, total burst length clocks. following table shows some example burst lengths BURST READ operation. (BURST WRITES usually slightly better). Note that faster memory yield better results. Also note that devices device used half speed mode) actual speed only half processor speed. Thus device might only have external bus. Whether 66/33 (internal/external) device faster than 50/50 device will depend cache rate external memory speed. More information various memory types obtained following collection appnotes: MPC860 Interface Fast Page Mode DRAM MPC860 Interface DRAM MPC860 Interface Synchronous DRAM (SDRAM)
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
Hardware Designers
Obtain Example Schematics
-Check Web: MPC860FADS Schematics, MPC860 Part Symbol, Footprint
Obtain User's Manual Errata Device Errata Remember Tolerance Look Clocking Issues
-Appnote: Crystal Note 302, 360, Family
Look Termination
-Pin Termination MPC860 white paper
Look Timing Issues
-Electronic Data Book MPC860 timings
Check Hardware Configuration Register Carefully Read MPC860 Design Checklist Part Running Having Trouble? Search MPC860 Update List Email Server
STEP-BY-STEP GUIDE HARDWARE DESIGNERS Obtain Example Schematics site offers several sources example schematics available ORCAD format. most useful probably SAMBA schematics, which shows interface entire MPC860 family memory Flash EPROM, DRAM, SDRAM. addition, shows MPC860T connected external 10/100baseT Transceiver. addition, schematics MPC860FADS boards also available, however, this board designed very flexible, represent most efficient system design. PART SYMBOL: electronic part symbol ORCAD Capture format also web. FOOTPRINT: documents AN1231 AN1232 in-depth discussions about factors regarding package that uses includes footprint design purposes. Obtain User's Manual Errata Device Errata This information available site PUBLICATIONS SUPPORT sections respectively. Remember Tolerance Although MPC860 family 3.3V supply device, tolerant used with compatible components. Look Clocking Issues
Although part allows both crystals oscillators used, recommend oscillators used possible. Oscillators reduce risk process variations process shrinks from causing clocking circuit cease operation. those that must crystals, recommend that engineers inquire their crystal manufacturer determine best capacitor crystal characteristics. They best position estimate values needed circuit. provide appnote "Crystal Note 302, Family." This paper written assist engineers production reliable clock circuits which used with devices such MPC860, MC68360 MC68302 their derivatives. discusses general terms various methods generation system clock. Look Termination frequent issue concern proper termination signal pins. This most common reason MPC860 board does work power-up. Which pins should pulled down proper operation 860? have produced white paper this very subject found Publications Area web. Look Timing Issues When designing your circuits involving will obviously take care meet timing specifications 860. addition timing diagrams manual, also provide some additional tools help understand your timing needs. web, Publications Area, MPC860 Electrical Specifications Spreadsheet. This Excel document dynamically calculates timing specifications based upon operation speed capacitive loading. program exact frequency your system bus, this tool will customize MPC860 timings you. addition, program capacitive loading pins, tool will customize timings. also have available electronic data book timings that used with Chronology's TimingDesigner tool. This software aids visualizing signal waveforms timings. Check Hardware Configuration Register Carefully MPC860 number different modes that programmed hardware. select modes driving certain voltage levels onto Data pins during reset. Data pins that drive will take default configuration. pins, will probably only need drive rest defaults. Please read this section manual very carefully making very basic decisions about operation part. Read Design Checklist When think have everything under control, back read MPC860 Design Checklist which resides PUBLICATIONS section site. This gives number helpful hints lists some common mistakes. part running. When boards back, first thing should bring part debug mode. debug mode, control part through debug port without requiring device execute software board itself. debug port pins MPC860 should brought simple header that described APPLICATIONS section MPC860 User's Manual. This will allow many standard debuggers access device. fact, purchased MPC860 FADS board, MPC8bug host control your target board through MPC860 FADS board. MPC860FADS manual more information this option.
Having Trouble? Don't forget check searchable http://www.mot.com/netcommfaq hints what might wrong. MPC860-Update List Server SUPPORT section site subscribe real-time updates late breaking news MPC860.
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STEP-BY STEP GUIDE DESIGNING WITH MPC860
Mechanical Component Engineers
Read Packaging Appnote
http://www.mot.com/pbga
Look Thermal Considerations
Appnote: Thermal Considerations Measurements Appnote:
Look Power Dissipation
MPC860 varies from 0.4W 0.8W depending frequency
Qualification Data
STEP-BY-STEP GUIDE MECHANICAL COMPONENT ENGINEERS Here some additional steps consider. Read Packaging Appnote MPC860 family resides lead Plastic Ball Grid Array (PBGA) package. appnote this package PBGAs general found http://www.mot.com/pbga Look Thermal Considerations NetComm available Publications Area appnote covering thermal considerations measurements packages.
extended temperature (-40 +85) required, offered speed grades, require heat sinks highest speed grades. Look Power Dissipation MPC860 family tends vary from 0.4W 0.8W depending frequency. power dissipation given frequency decreasing device undergoes shrinks. Meanwhile offered frequency increasing over time. result that power dissipation highest speed versions tend 0.8W range. first MPC860 User's Manual showed option running internal circuitry MPC860 family 2.2V (rather than 3.3V) save power. This option been productized MPC860 MPC850 family, available. Qualification Data Qualification reports available devices, however they only obtained through Motorola Sales office. SLIDE GS-13
STEP-BY STEP GUIDE DESIGNING WITH MPC860
Software Designers
Determine Your Tool
-Visit MPC860 Third Party Support Page
Review Motorola Application Development System Materials
-MPC8bug: Motorola's command line monitor/debugger
Acquire MCUinit
-MCUinit: Motorola's GUI-based initialization code generating package
Study Exception Processing Interrupts Obtain Basic Chip Initialization Code Obtain Device Drivers Example Code Read Performance Appnote
-Appnote: MPC8xx Performance Driven Optimization Caches MMUs
Scan Performance Checklist Having Trouble? Search
-http://www.mot.com/netcommfaq
MPC860 Update List Email Server
STEP-BY-STEP GUIDE SOFTWARE DESIGNERS Determine Your Tool incredible amount support also available many forms from companies outside Motorola. list those companies organized category support, their contact information links their sites available) located site. various pages throughout site will links Third Party Support Page.
Categories support include: Board Test Consultants, Chip Drivers (Software), Generators Tools, Companion Support Chips, Development Systems, Emulators, Hardware Models, Network Software, Operating Systems, Package Socket Adapters. highly encourage investigate these companies' products services your efforts your product market. Review Motorola Application Development System Materials Among most important support materials available customers MPC8xx Family Application Development System (8xxFADS). This package meant serve platform software hardware development around family devices. Using board resource associated MPC8bug debugger/monitor, developer able load their code, breakpoints, display memory registers connect developer's proprietary hardware expansion connectors. FADS just effective testing purposes also serve demonstration tool. Contact your local Motorola Sales office details purchase systems. Information find most appropriate sales channel found web. MPC8BUG Motorola provides command line debugger/monitor program called MPC8bug. This package provides excellent simple methods observing debugging your code performing diagnostics. even write your diagnostics with release software. This software shipped with 860ADS 8xxFADS, also available web. Download MCUinit Interested using graphic interface tool quickly produce initialization code 860? need check MCUinit, menu-driven initialization code generating program 32-bit Windows compatible computers. This software package located both NetComm General CDROM. Study Exception Processing Interrupts There also MPC860 EPPC Exception Processing Application Note with deals with exception processing more detail. addition, appnotes provided interrupts CPM. Obtain Basic Chip Initialization Code Look ENGINEERS TOOLBOX obtain latest MPC860 Initialization code. This shows bring device from power-up including programming clocking modes chip selects. Obtain Device Drivers Example Code Engineers' Toolbox your best resource freeware available from Motorola with 860. will find both simple tutorial-style examples, some complex drivers well, that demonstrate wide variety protocols modes operation from setting timers running Ethernet. list code available being updated time, check often. currently have drivers example code HDLC, Ethernet, UART, Transparent, Real-time clock, I2C, PowerPC Timebase, ASAR MPC860SAR. Drivers also available from third parties such AISYS, Inverness, Trillium often included with purchase RTOS MPC860. Read Performance Appnote
MPC860 core Memory Management Units caches, each data instructions. invite study Cache appnote package, available Publications area NetComm site, which explains efficiently caches MMU. includes appnote itself, special version debugger/monitor NetComm offers with cache simulation ability, some scripts (given examples appnote) that used with debugger. appnote named "MPC8XX Performance Driven Optimization Caches MMUs". Scan Performance Checklist Publications Library MPC860 Performance checklist. This document basically quick summary most important facets Performance Appnote mentioned above. Topics that covered include dealing with DRAM, interrupts their handlers, core operation modes more. getting performance expect, this place start. MPC860 many debug assist modes that uncommon customers performance improvement, after following guidelines this checklist. Having Trouble? having trouble getting your serial protocols work looking appnote "Hints Debugging CPM". This shows determine where problem resides, showing trace flow data from system memory pins, from pins back system memory. Also, don't forget check searchable Frequently Asked Questions http://www.mot.com/netcommfaq MPC860-Update List Server SUPPORT section site subscribe real-time updates late breaking news MPC860.
Chapter MPC860 Architecture, Part
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MPC860 Architecture, Part
What Identify basic blocks MPC860 their functions will learn Describe function each component Describe internal data flows Identify groups Describe example application
this chapter will learn Identify basic blocks MPC860 their functions Describe function each component Describe internal data flows Identify groups Describe example application
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What Basic Components?
Cache Core Cache U-bus System Interface Unit Memory Controller System Functions Real Time clock PCMCIA Interface Internal General Interrupt Memory Purpose Controller Serial Space Timers DMAs; 32-Bit RISC µController Virtual IDMA Program Internal Timers Peripheral SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI1 Serial Interface Time Slot Assigner Communications Processor Module
PowerPCParallel Baud Rate Generators Parallel Interface Port
What basic components MPC860? This block diagram MPC860. consists three major blocks: PowerPC core, System Interface Unit SIU), Communications Processor Module CPM). PowerPC main processor unit, commonly referred Embedded PowerPC Core EPPC short [pronounced "epic"]). includes caches Memory Management Unit (also known MMU). performance capability mips with megahertz clock. second major block System Interface Unit. primary functions provide interface between internal Unified external bus. also provides number other functions shown here. Finally, third major block Communications Processor Module. sends receives data over eight different communication devices, such Serial Communication Channels (SCC) Serial Management Channels (SMC). devices used individually, SCCs SMCs used Time Division Multiplexed Bus. Notice that within Communications Processor Module, there 32-bit RISC micro-controller. MPC860 contains CPUs: PowerPC 32-bit RISC. PowerPC executes code higher layers maximize throughput. RISC takes care low-level aspects communication such moving characters from memory, handling actual communication. course, processors must have some means coordinating efforts. primary means internal memory space. this memory area, each processor control bits, read status bits which other processor then respond. Also this diagram, there serial DMAs Direct Memory Access units. Each eight communication devices transmit receive DMA. 32-bit RISC directs these serial DMAs transfer data between communications devices memory, usually external memory. When MPC860 receives data, serial obtains data from communication
device moves this data into memory. data transmission, sequence occurs reverse, with data originating memory, serial transferring that data communication device. serial DMAs used exclusively RISC; however, there virtual IDMAs available user requirements.
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Data Flows
System PowerPC2 U-bus Interface Unit
Serial DMAs Virtual IDMA Communications Processor Module
Internal Memory Space Peripheral
does data flow? This diagram shows major paths data flow within 860. first path shown from data flows from PowerPC SIU. core uses this path when executing load store instructions that miss cache, that cacheable. cache controllers within PowerPC also this path when loading flushing cache. processes addresses used this path. second path shown from data flows from PowerPC internal memory space; this path occurs accesses registers dual-port within internal memory. processes these addresses, because both processors write this memory, this data area should cached. third path shown here from data flows from peripherals from external bus. This path that used moving data between external memory communications peripherals. does process addresses, data should cached. final path shown here from data flows from peripherals internal memory space. This path occurs data transfers between peripherals dual-port RAM. This path used often, although wish occasionally. Normally, data buffers placed external memory; however, possible place buffers dual-port area internal memory space. limitation that internal memory space very large. does process addresses, data should cached.
SLIDE
What Pinouts?
Power Pins VDDSYN, VSSSYN VDDH,VDDL,VSS, KAPWR Port PA0-PA15 Port PB14-PB31 Port PC4-PC15 Port PD3-PD15 JTAG/Dev. Supp. Group Diagram PCMCIA Port Dev. Supp., Program Tracking MPC860 Address (0:31) Data (0:31) Control Interrupts Memory Control Reset Crystal/Oscillator PCMCIA Port
What pinouts? Here summary diagram groups MPC860. more detailed diagram available User Manual. Here shown 32-bit address bus, 32-bit data bus, control pins. Most users support their memory interface requirements with memory controller pins, since these pins provide direct interface almost device. However, chip select pins use, rare device that memory controller cannot support, then user implement control pins interface device. user will need provide additional logic interface they implement control pins. There eight interrupt pins, and, mentioned, memory controller pins. There also pins associated with hard soft reset. Additionally, there pins that allow user supply clock. possible supply clock with crystal, external oscillator, both. MPC860 supports PCMCIA ports. pins PCMCIA Port standalone; that pins PCMCIA Port dedicated that function. pins PCMCIA Port however, shared with Development Support capability program tracking functions. might call right side diagram shown here system side, while might call left side diagram communications side. most part, communications side consists four ports: Port Each these pins general-purpose support least alternate function associated with communications device, such receive transmit. Part designer's task determine each these shared pins. There also pins associated with JTAG, Development Support shares these pins.
SLIDE
What Example Application?
Optional Ethernet RS-422 Localtalk T1/E1 Line T1/E1 Transceiver TDM-A SCC2 32-bit RISC Memory Cntrlr Qspan-860 Port Port RJ-45 EEST MC68160 Glue MPC860 Power Core 32-bit Boot
SCC1
DRAM SIMM bits
SCC3 Time SCC4 ISDN-Basic Primary Slot SMC1 S/T/U S/T/U TDM-B Assigner Transcvr IDMA IDMA RS-232 Local SMC2 PCMCIA Terminal Serial EEPROM MCM2814
Peripheral Peripheral Buffers Peripheral
What example application? This diagram shows ideas user might implement some devices MPC860. SCCs capable supporting number protocols. Here, example, upper left-hand corner, SCC1 shown connected Ethernet transceiver Ethernet network. SCCs support Ethernet protocol, however. Here, example, SCC2 supports interface LocalTalk network. Furthermore, also possible provide interface Time Division Multiplexed buses: TDM-A TDM-B. Here connections shown T1/E1 line, ISDN interface examples. such case, timeslot assigner routes data buses SCCs, SMCs total devices which data routed. Serial management controllers have much capability SCCs, very common implementation SMCs with local terminal shown here. Serial Peripheral Interface available communicating with variety peripheral devices, including number transceivers, which programmed through bus. Here show Serial Peripheral Interface with double EEPROM. There also InterIntegrated Circuit (I2C) controller providing interface number peripherals. good device consider user intends SIMMs example, which presence detect function implemented using EEPROM with interface. Additionally, PCMCIA controller supports PCMCIA boards. External buffers PCMCIA transceivers must provide electrical isolation between sockets system bus. MPC860 3.3-volt device, with exception clock input 5volt friendly; therefore voltage conversion required inputs other than those clock.
have mentioned previously that there IDMA devices; these devices available transfer data from peripherals, well transfers from memory memory. Finally there memory controller. possible program memory controller boot from 16-, 32-bit ROM; likewise, memory controller provide interface DRAM SIMM, wide variety other memory devices. memory controller also connect using devices available from 3rd-party manufacturers.
SLIDE What Basic PowerPC core Components
What Basic EPPC Components
I-cache/I-MMU interface Core Sequencer Address generation control write back slots/clock) Special Regs source busses slots/clock) 32x32 history IMUL/ IDIV ALU/ LDST address LDST data Branch unit Instruction queue D-cache/D-MMU interface L-addr L-data
turn attention PowerPC core MPC860. Here have block diagram, focus sequencer. sequencer provides centralized control instruction flow execution units, shown lower portion block diagram. Address Generation unit supplies address fetch next instruction based information from sequencer from Branch Prediction Unit. Branch Prediction Unit extracts branch instructions from sequencer, uses static branch prediction unresolved conditional branches allow instruction unit fetch instructions. instruction queue holds next instructions distributed. Branch Prediction Unit examines instruction determine branch instruction not. Branch Prediction Unit then passes instruction instruction queue. instruction queue moves instruction from Branch Prediction Unit head queue, then dispatches appropriate execution unit. Branch Prediction Unit does take action instruction branch instruction. instruction branch instruction, Branch Prediction Unit makes static prediction whether branch will taken not. Based Branch Prediction Unit's decision, Address Generation Block obtains instruction either from next sequential address, instruction location which branch will Static branch prediction performed according user programmed
branch instruction. times that prediction wrong, instruction queue will have flushed out, instructions from other location will have brought into instruction queue. Here three execution units. execution units supports general-purpose registers. These registers temporary, pointer, index data. There thirty-two, 32-bit general-purpose registers, they operate essentially same way. special purpose registers used control status data, well save restore data. There actually more special purpose registers than general-purpose registers. There also history buffer (GPR History). core dispatches each instruction, instruction enters history buffer. core sets various status bits showing progress instruction executes. When instruction completes, exits history buffer. While instruction history buffer, perhaps partially executed, exception could occur, which case MPC860 capability back machine instruction that caused exception, then handle exception. Integer Multiply Divide Unit executes integer multiply divide instructions. There Arithmetic Logic Unit with Field Logic Unit combined, which executes other integer instructions. Next, there units associated with load store, address data. Both units consist two-entry 32-bit queue. load store instructions share Load Store Address queue. Load Store Fixed-Point Data Queue holds fixed-point data.
Chapter EPPC Programming
SLIDE
EPPC Programming
What will learn Learn Write program loops Write subroutines Test manipulate bits devices Implement signed unsigned arithmetic algorithms
this chapter, will learn Write program loops Write subroutines Test manipulate bits devices Implement signed unsigned arithmetic algorithms
SLIDE
Overview Programming Model
User Programming Model (same EPPC implementations) General Purpose Registers GPR0 GPR1 GPR30 GPR31 Condition Register Special Purpose Registers
Program Counter
Supervisor Programming Model changes different EPPC implementations) Machine State Register Standard SPRs DSISR SRR0 SRR1 SPRG0 Additional SPRs SPR80-82: SPR560-570: SPRG1 manipulation Icache Dcache SPRG2 MSR[RI&EE] control/status SPR784-826: SPR144-630: SPRG3 Debug TB(to write) development programming model support TBU(to write)
Overview Programming Model This slide illustrates general view programming model MPC860. divided into parts: user programming model, supervisor programming model. user programming model essentially subset supervisor model.
SLIDE
Overview Programming Model
User Programming Model (same EPPC implementations) GPR0 GPR1 SPR1 SPR8 SPR9 contain data addresses SPR268 task execution SPR269 arithmetic OV,CA,SO Subroutine return address Goto address/loop count Free running TimeBase count (read only)
GPR30 GPR31 Condition Register fields condition evaluation Program Counter
directly accessible
User Programming Model First, discuss user programming model. Note that when discuss user model, this synonymous with problem state operation. Within user programming model, there thirty-two general-purpose registers. Each register bits wide. these registers operate essentially same way. EPPC computations register register. Information saved restored from, registers. PowerPC, there stacking mechanism, therefore dedicated stack pointer. Although hardware provides stacking mechanism, user implement stacking functions through software. While there dedicated stack pointer register, convention, General Purpose Register (GP(R1)) acts stack pointer register. Another register user programming model Condition Register (CR), consisting eight, 4-bit fields. discuss this register more detail later this chapter. Also user programming model, there five special purpose registers. SPR1 Integer Exception Register (XER) register, which used multi-precision arithmetic, overflow, carry, summary overflow bit. Next Link Register, Special Purpose Register (SPR8). This stores return address when call subroutine instruction executes. SPR9 counter register. This commonly used counter register loop programs. Alternatively, programmer also this register GOTO, which routine stores address, branches location which address points. remaining special purpose registers TimeBase 269. This 64-bit time value, used time stamp. part PowerPC architecture. user access this TimeBase through these registers read-only basis.
Finally, there program counter user programming model; however, directly accessible user.
SLIDE
Overview Programming Model
Supervisor Programming Model changes different EPPC implementations)
Standard SPRs cause address storage fault exception time
SPR18 SPR19 SPR22 SPR26 DSISR
Additional SPRs SPR80-82: manipulation MSR[RI&EE] SPR144-630: Debug development support SPR560-570: Icache Dcache control/status SPR784-826: programming model
Machine State Register free running contains: decrementer info enables return address state enables
time exception SPR27
SPR272
scratch
SPR273 SPR274 SPR275 SPR284 SPR285
SPR80 SPR81 SRR0 SRR1 SPRG0 SPRG1 SPRG2 SPRG3 TB(to write) SPR825 TBU(to write) SPR826
processor version
SPR287
Supervisor Programming Model discuss supervisor programming model. Note that when discuss supervisor model, this synonymous with privileged state operation. supervisor programming model, there Machine State Register, which contains information about machine state, such enabling exceptions, interrupts. There also standard special purpose registers. first standard SPRs Data access exception Source Instruction Service Register (DSISR) Data Address Register (DAR) -store information when certain exceptions occur, especially error exceptions. next register Decrementer register. This register also functions part PowerPC architecture. value this register constantly decrements, possible interrupt occur when value reaches zero. next registers, Save Restore Registers (SRR0 SRR1), always used exception processing. exception service routine saves Machine State Register program counter into these registers. next four registers available operating system use, requires. Special purpose registers available TimeBase. this case, supervisor access these registers write value TimeBase. Special purpose register contains processor version revision number.
There quite additional special purpose registers, including those that affect Machine State Register; others that control debug development support, others affecting cache MMU. More detail these registers included chapters covering associated subjects.
SLIDE
Data Instructions
most significant (bit left. numbers increase toward least significant (LSB). byte, halfword, word. byte halfword word Instruction size instruction size word EPPC processors. Instructions word-aligned that order bits instruction address needed, zero. word
Data sizes
Data Instructions Here shown data sizes PowerPC. There three data sizes: byte, half-word, word. Also, we'd like make quick point about numbering PowerPC world. Bits labeled left right, most significant least significant, strictly labeling convention only does apply significance. still most significant, unless alternate mode operation, PowerPC uses Endian byte ordering default. PowerPC architecture does support dynamic sizing; therefore, does allow misaligned access. instruction size PowerPC always word. Instructions word-aligned that low-order bits instruction address needed, zero.
SLIDE
Data Instructions
first instruction format does operation with (rA) 16-bit immediate data (sign zero extended 32bits). second does operation with GPRs rB). Both place results into destination (rD). Operations always bits write bits General Syntax
Encoding
Examples Subopcode
Instr rD,rA,rB
Opcode
r3,r4,r6 r16,r12,r3
Instr_i rD,rA,0xXXXX
addi r3,r4,750 r14,r5,0x100 UIMM (16-bit unsigned immediate data), SIMM (16-bit signed immediate data) Opcode Instruction syntax instr rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB subf rD,rA,rB Algebraic Operation rA<opr>rB
=operation (+,-,*, ÷,etc)
Data Instructions There primary formats instructions. includes instruction mnemonic, followed three operands refers destination register, while determine contents source register. Refer examples right side chart. case "add r6", placed case logical operation, such "or", 'OR'd' with r12, result placed r16. similar format 'instruction immediate', which follows instruction mnemonic. this case, third operand immediate value bits. Refer examples right side chart. case "add immediate", added 750, which sign extended, placed into case logical operation, 'OR'd' with 0x100, zero extended, result placed into r14. Remember that operations always bits, write bits chart lower portion diagram clarifies order operands operations. Here shown instruction mnemonic with three operands. each case, assigned results operating upon value example, case "add" instruction, contains case subtraction operation, contains value minus Also shown `subf', which effect reversing operands that contains value minus `subf' simplified mnemonics, described more detail Appendix PowerPC Environments books.
SLIDE
Instruction Summary
Arithmetic Logic
subf
rotate shift cntlzw
nand
GPR0 GPR1 GPR30 GPR31
Load Store
Memory
lhbrx lwbrx
sthbrx stwbrx
stmw stsw
GPR0 GPR1 GPR30 GPR31
Store
Load
Instruction Summary Shown here number commonly used instructions PowerPC instruction set. First shown some arithmetic logical instructions, which performed conjunction with general-purpose registers. Sources data either GPRs immediate 16-bit data. destination GPR. Operations bits, update bits destination GPR. Most self-explanatory. Note `cntlzw' instruction, listed last set. "Count leading zeros word" obtains instruction number leading zeros word before encountered. This particularly useful when determining highest priority event exception register, which concept discuss exception chapters. Next shown load store instructions. These important when transferring data between memory general-purpose registers. data less than word, half-word byte, then load instructions always make data bits long, either filling with zeroes sign extending. `lbz' "load byte zero". `lha' "load half word algebraic", meaning that sign extended word. `lhz' "load half word zero extended". Next `lwz' instruction, which "load word zero extended". instructions PowerPC have been assembled potential with 64-bit architecture, possible instructions conjunction with 32-bit architecture. mnemonics remain same either case. There also "store byte" instruction, "store half word", "store word".
Next, "load multiple word", "store multiple word", "load string word", "store string word". Additionally, shown here instructions ending "brx" `sthbrx' `stwbrx'. These instructions particularly valuable when required that PowerPC access data that stored little endian mode. Perhaps there case which PowerPC shares memory with second processor using little endian data. order PowerPC access manipulate such data, these instructions permit storage data such that, should data arrive from little endian order, stored endian order.
SLIDE
Instruction Summary
Flow control
bcctr bclr trap
crand cror crxor creqv mcrf
SPR8 SPR9 Condition Register
"rfi" privileged instruction
Processor control
Here's load count into loop counter (spr9 (CTR)): r13,count ;load count into 2.mtspr CTR,r13 ;move mfmsr GPR0 mtmsr GPR1 mtspr mfcrf mtcrf Condition Register mcrxr GPR30 GPR31 mfspr mftb
SPR0 SPR1 SPR1022 SPR1023
"mtspr" "mfspr" instruction with other than 1,8,9,268, privileged
Instruction Summary Next shown number instructions supporting flow control, including branch instructions. Here branch instruction, branch conditional instruction, which makes bits Condition Register. right illustration shown Condition Register, broken into eight, 4-bit fields. Within each field bits representing less than, greater than, equal summary overflow. This register provides total eight condition fields supporting conditional branch instructions. There also instruction branch location pointing counter, which SPR9 user programming model. possible perform branch instruction conditionally based link register, thereby making special purpose register user programming model. SPR8 stores appropriate address event branch subroutine instruction. There also trap instruction, system call instruction, `rfi', which used with exception service routines. There also number instructions that directly affect Condition Register.
Next listing processor control instructions. valuable purpose these instructions includes ability transfer data between special purpose registers, general-purpose registers. possible operate directly upon values special purpose register. Instead, value copied into general-purpose register prior manipulating data. After operating data, information stored special purpose register. "move from special purpose register" instruction moves data from special purpose register general-purpose register. Likewise, "move special purpose register" instruction moves data from general-purpose register special purpose register. example, user wishes initialize counter register, necessary load generalpurpose register with value, shown here with "load immediate" instruction operating counter registers. Next, "move special register" instruction moves value counter register.
SLIDE
Instruction Summary
Synchronization
These instructions used control multiprocessor synchronization
eieio; isync; sync; lwarx; stwcx.;
control- next load store waits until prior loads/stores done waits prior operations complete flushes instruction queue waits prior operations complete multiprocessor synchronization with shared resource multiprocessor synchronization with shared resource
Instruction Summary Next shown synchronization instructions, control multiprocessor synchronization. first instruction listed 'eieio'. take closer look this instruction next diagram.
SLIDE 2-10
What eieio Instruction?
Example
while (TDRE char1; eieio"); while (TDRE char2;
TDRE
Stores followed loads executed out-of-order allow optimum resources. example, however, would work properly this happened. Line insures that line will completed before line which essential correct operation this program fragment.
What `eieio' instruction? `EIEIO' refers Enforce In-Order Execution I/O. `eieio' instruction provides ordering function effects load store instructions that access devices. programmer should `eieio' instruction when accessing device with store instruction followed load instruction. example, consider device located external memory space. includes transmit line, transmit data register. Also, there status bit, shown here TDRE, that indicates when transmit data register empty. this example, user wishes transmit characters. First, example routine contains instruction that checks value TDRE, does proceed further until TDRE equal '1'. When TDRE equal '1', routine writes character transmit data register. moment, skip line example routine, examine line Again, routine observes status TDRE bit, when this equals '1', writes second character transmit data register. general, PowerPC execute stores followed loads order allow optimum resources. This particular example would function properly such case. Note that line contains store instruction, followed line which contains load instruction. PowerPC could execute line prior line that order more efficient that time. that case, checks TDRE would occur, followed immediately writing characters transmit data register. handle such situation effectively, programmer inserts line 'eieio' instruction, between store load instructions. This informs PowerPC that store must executed before load instruction.
SLIDE 2-11
What eieio Instruction?
Specific Examples
Write Command pimm->CPCR comm1; asm(" eieio"); while ((pimm->CPCR pimm->CPCR comm2; Vector Number pimm->CIVR.IACK asm(" eieio"); pimm->CIVR.VN;
Additional Comments
device must page that cache-inhibited writethrough. MPC8xx devices far) prohibit reordering store followed load address same; however, this part PowerPC architecture. Therefore, architecturally compatible, eieio should implemented described.
What `eieio' instruction? There some cases specific MPC860 which 'eieio' instruction required. first example, shown here left, uses command register. routine writes command command register, CPCR. then monitors least significant determine when becomes '0'. Then routine writes another command. this case, writing first command constitutes store operation, examining least significant constitutes load operation. 'eieio' instruction shown ensures that store load instructions executed order. second example, shown right, involves getting vector number. vector number, routine writes Interrupt Acknowledge (IACK) field Interrupt Vector Register (CIVR) register, then performing read field CIVR register. Again, store followed load, between instructions there must 'eieio' instruction. device must page that cache-inhibited write through. These topics that will discuss later cache section.
SLIDE 2-12
Instruction Summary
Synchronization
These instructions used control multiprocessor synchronization
eieio; isync; sync; lwarx; stwcx.;
control- next load store waits until prior loads/stores done waits prior operations complete flushes instruction queue waits prior operations complete multiprocessor synchronization with shared resource multiprocessor synchronization with shared resource
Instruction Summary next synchronous instructions from list `isync', then `sync'. examine sync instruction more closely.
SLIDE 2-13
What Execution Synchronizing?
Definition instruction execution synchronizing causes instruction dispatching halted, does complete until instructions execution have completed point which they have reported exception they will cause. mtmsr
Example
;copy
Specific Execution Synchronizing Instructions
mtspr off-core registers
What Execution Synchronizing? instruction execution synchronizing Causes instruction dispatching halted, Does complete until instructions execution have completed point which they have reported exceptions they will cause. most common example move machine state register. Shown here "move machine state register" When this instruction executes, first waits until preceding instructions have completed execution. Then value into machine state register before proceeding next instruction. Additionally, MPC860 specific synchronizing instruction "move special register", used conjunction with off-core registers. This described more detail User Manual.
SLIDE 2-14
What sync Instruction?
Example sync //enter isync
;wait preceding operations complete ;enter power mode instructions execute after ;low power instruction
Specific Examples, Enter Power Mode
asm(" sync"); pimm->PLPRCR.LPM0_LPM1 asm(" sync");
What `sync' instruction? `sync' instruction execution synchronizing. addition Waits until pending memory accesses complete, Sends address-only broadcast cycle, although this implemented MPC860. `sync' instruction should used when change state occurs parameter, and: operations must complete prior parameter change, parameter change must complete before proceeding with other instructions. example using `sync' instruction entering power mode. preferred previous instructions have completed prior system entering power mode. Then, preferred that subsequent instructions complete until after system exits power mode. Here general example. First routine executes sync instruction, prior executing instructions enter power mode. This ensures that preceding instructions have completed. second example specific MPC860. Writing value Power Mode (LPM0_1) field PLL, Power, Reset Control Register (PLPRCR) register brings into power mode. (The PLPRCR register registers located internal memory map.) Again, this case, programmer desires that preceding operations complete prior entering power mode. `sync' instruction accomplishes this task. programmer also desires that further instructions execute after entering power mode. second `sync' instruction accomplishes
this task, ensuring that instruction bring system into power mode completes before subsequent instructions execute.
SLIDE 2-15
What sync Instruction?
Specific Examples, Enter Mask Lower Priority Interrupts sptr++ pimm->SIMASK; pimm->SIMASK 0xF0000000; asm(" sync"); asm(" mtspr 80,0");
//save SIMASK //mask intrpts //assure store SIMASK //enable interrupts
What sync instruction? second example specific MPC860 shown here. This example includes interrupt service routine, which programmer wishes mask interrupts writing SIMASK register. routine first writes value SIMASK, follows with `sync' instruction before re-enabling interrupts. This ensures that lower priority interrupts have been masked, because store memory completed prior enabling interrupts.
SLIDE 2-16
Instruction Summary
Synchronization
These instructions used control multiprocessor synchronization
eieio; isync; sync; lwzrx; stwcx.;
control- next load store waits until prior loads/stores done waits prior operations complete flushes instruction queue waits prior operations complete multiprocessor synchronization with shared resource multiprocessor synchronization with shared resource
Instruction Summary discuss `isync' instruction, shown here original list synchronizing instructions.
SLIDE 2-17
What isync Instruction?
Example r29,0x0200 mtspr IC_CST,r29 isync
;enable instruction cache
Instruction Fetches sequencer contiuously fetches instructions. change state instruction cache with instructions queue under different context could cause erratic operation. isync insures that instructions brought under present context that previous instructions completed.
Add'l Comments
Additional cases which require isync instruction listed pages 2-41 through 2-44 instructions, rfi, most exceptions, also context synchronizing.
What `isync' instruction? `isync' instruction instruction context synchronizing. Performs execution synchronizing, Reloads instruction queue under context. `isync' instruction should used when change context occurs, such enabling instruction cache, when execution synchronizing needed access completion. example, lines enable instruction cache. this point, several instructions instruction queue, instruction cache, since previously enabled. user might desire that these instructions load into cache from time that enabled. perform this function, routine includes `isync' instruction, causing these instructions reloaded context. instructions "system call", `rfi', most exceptions also context synchronizing.
SLIDE 2-18
Instruction Summary
Synchronization
These instructions used control multiprocessor synchronization
eieio; isync; sync; lwarx; stwcx.;
control- next load store waits until prior loads/stores done waits prior operations complete flushes instruction queue waits prior operations complete multiprocessor synchronization with shared resource multiprocessor synchronization with shared resource
Instruction Summary There more synchronizing instructions: `lwzrx' `stwcx'. These both used conjunction with reservation system, which useful multiprocessing application. PowerPC reserve shared memory area safely needed, there thus concern about second processor overwriting area shared memory. These instructions operate similar 68000.
SLIDE 2-19
Instruction Summary
Memory Control Here cache instructions. They broadcast.
dcbt dcbtst dcbz dcbst dcbf dcbi icbi
"dcbi" privileged instruction
Dcache
Memory
Icache
Instruction Summary Next shown memory control instructions, which transfer data between caches memory. There number instructions, many which concern cache. discuss cache more detail later chapter.
SLIDE 2-20
Instruction Summary
Simplified (Extended) mnemonics
Simplified (Extended) mnemonics provided simplify writing, comprehension, assembly language programs. shown here. Simplified Mnemonic rD,rS rD,rS loop rD,0xXXXX Equivalent r0,r0,0 rD,rS,rS rD,rS,rS 4,0,loop addi rD,r0,0xXXXX
destination
source
Instruction Summary Here also shown simplified, extended, mnemonics. Simplified mnemonics provided simplify writing, comprehension, assembly language programs. mentioned earlier, there simplified mnemonics, some which illustrated. These include 'nop' 'move register', 'not'. Simplified mnemonics particularly useful branch operations, here 'branch greater than equal'. really 4,0,loop' instruction, which much harder understand first glance. Finally, 'load immediate' into destination register.
SLIDE 2-21
Interpreting Condition Codes,
Condition Register 4-bit field Condition
Explanation Condition Comparisons Computations (rA)<(rB), simm uimm Negative (rA)>(rB), simm uimm Positive (rA)=(rB), simm uimm Zero copy XERso copy XERso
updated subf mulhw divw
updated add. subf. simm signed 16-bit data uimm unsigned 16-bit data neg. mulhw. divw. and. xor.
Interpreting Condition Codes have seen, Condition Register consists eight, 4-bit fields, CR0-CR7. Each field represent Integer Computation Comparison results. Each condition field record conditions "less than", "greater than", "equal", "summary overflow." only instruction that automatically affects Condition Code Register 'compare' instruction. Other instructions such 'add', 'subtract', 'divide' 'multiply' affect Condition Code Register, unless programmer wishes them programmer must explicitly indicate with period that condition codes recorded, shown chart left. four conditions 'less than', where less than 'greater than', where greater than These conditions implemented signed unsigned basis. Next, 'equal' condition, where equal fourth 'summary overflow', which copy summary overflow from register.
SLIDE 2-22
Interpreting Condition Codes,
;compare algebraic syntax: crx,size,rA,rB (signed) cmpl crx,size,rA,rB ;compare logical (unsigned) cmpi crx,size,rA,simm ;compare value signed cmpli crx,size,rA,uimm ;compare value unsigned examples: Simplified mnemonics: Equivalent cmpw r13,r14 cr0,0,r13,r14 cmpw cr5,r13,r14 cr5,0,r13,r14 cmplw cr5,r13,r14 cmpl cr5,0,r13,r14 cmpwi cr5,r13,1234 cmpi cr5,0,r13,1234 cmplwi cr5,r13,1234 cmpli cr5,0,r13,1234 cmpld cr5,r13,r14 cmpl cr5,1,r13,r14 Assuming these values: 0x70000000 GPR11 0x80000000 Determine compare operation fill correct values field: cmpw cmplw cr5,r10,r11 cr2,r10,r11
Interpreting Condition Codes Compare instructions affect Condition Register field. basic syntax compare instruction mnemonic, 'cmp' followed four fields. first field specifies which sets condition bits should affected CR0-CR7. second field specifies size. There possible sizes: either bits bits. Only 32-bit size possible with MPC860. Next, third fourth fields specify registers compared second form compare 'cmpl', compare logical. third form 'cmpi', compare immediate. fourth form 'cmpli' compare logical immediate. compare function also implemented simplified mnemonics. first instance shown here 'cmpw r13, r14.' This equivalent specifying 'cmp cr0, r13, r14.' Other examples follow chart, indicating possible specify instead including operands. examples shown bottom illustration. There registers: contains value seventy million, contains value eighty million. first example compares r11, places values condition bits cr5. this case, 'cmpw' 'sign compare', meaning that values registers assigned. seventy million large positive number, eighty million large negative number. Therefore, greater than r11, 'greater than' set, while 'lt' 'eq' both zero. next instruction similar, logical. this case, values treated unsigned numbers. Therefore, eighty million larger than seventy million. Therefore, greater than 'less than' set, while 'gt' 'eq' both zero.
SLIDE 2-23
Using Recording Arithmetic Info,
Register SPR1 byte count 000000000000000000000
(summary overflow)
overflow)
(carry)
whenever carry whenever instruction whenever overflow occurs, else cleared; multiply occurs, else cleared; sets overflow (OV) bit; divide instructions extended precision once set, only cleared mtspr instruction. result register. instructions operand. Using Register bits Examples: usage and/or affect instruction usage recording info addc record carry adde operand record carry addo record overflow addco record carry record overflow
Using Recording Arithmetic Information Here learn register with multi-precision arithmetic. register contains three bits use: summary overflow, overflow, carry. necessary programmer indicate explicitly which bits used updated appending instructions with 'C', 'E', and/or 'O'. records carry uses operand instruction, also records carry Finally, records overflow overflow summary overflow bits. example, simple 'add' instruction does make register. 'addc' records carry 'adde' uses operand records carry 'addo' records overflow 'addco' records carry overflow
SLIDE 2-24
Using Recording Arithmetic Info,
Write instructions 64-bit operands together. GPR3||GPR4 GPR14||GPR15 contain operands. Store result GPR13||GPR14||GPR15. Algorithm:
GPR13 GPR13
GPR3 GPR14 GPR14
GPR4 GPR15 GPR15
Results:
GPR13
Suggested program steps: Clear GPR13 record carry record carry
Using Recording Arithmetic Information example, programmer desires 64-bit operands. operand generalpurpose registers second operand general-purpose registers result should stored general-purpose registers This operation performed with following instructions: first instruction load immediate r13, clear register next 'addc' r15, This puts into carry into XER. Then have `adde' r14, r14, which sums carry from stores result carry XER. Last 'adde' r13, r13, r13, which includes carry completed.
SLIDE 2-25
Branch Types Addressing
Mnemonic Branch Operation branch always relative save next instruction address Link register branch always relative branch always absolute save next instruction address Link register branch always absolute branch conditional address contained Counter save next instruction address Link register branch conditional address contained Counter branch conditional address contained Link register this traditional instruction) save next instruction address Link register branch conditional address contained Link register branch conditional relative save next instruction address Link register branch conditional Target Address Generation opcode: 0x12 target 23-bit branch instr addr range 32Mbytes from branch instr opcode: 0x12 target 23-bit range 32Mbytes from 0x00000000 target contents counter, bits 30:31=00 range Gigabytes target contents link reg, bits 30:31=00 range Gigabytes opcode:
bcctr bcctrl bclr bclrl
target SE13-bit branch instr addr range 32kbytes from branch instr distance words away from branch) sign-extended bits)
Branch Types Addressing This summary available branch types. illustration shows branch mnemonic, branch operation, branch target address generation range. Each type option, which saves return address Link register. Conditional branches with option save return address Link register whether branch taken taken. 'GOTO' performed loading GOTO address into Counter register (SPR9), then executing 'bcctr'. Executing 'bclr' performs 'return from subroutine'. first branch mnemonic shown 'b', branch always relative. That allows programmer branch always relative location program counter. Similar 'ba', which performs branch always absolute address. Branch conditional relative takes branch certain type condition exists. There also branch conditional location contained link register, branch conditional location contained counter. Appending [lower case most these branch instructions permits their execution conjunction with storing address next instruction link register. exception 'branch always absolute', which takes form 'bla'.
SLIDE 2-26
Branch Operation
bdnz/bdz bdnzt/bdzt CNTR count-1 bdnz bdnzt
CNTR<>0?
Branch Fail Logic bc/bca bdzt
CNTR=0?
b/ba
Next Sequential Instruction Address Goto next sequential Instruction bl/bcl bclrl/bcctrl
bdnzt Condition True? bdzt bdnz/bdz
SPR9
Count register (CNTR)
Sign Extension BD/LI SPR8
Link register
Current Instruction Address bcctr
bclr
Branch Target Address Calculation This diagram does show order operations.
Branch Target Address
Branch Operation This diagram shows operation branch instruction types ways with which branch target addresses calculated. condition code flag, decremented count, both, neither help control branch instruction program flow. diagram divided into parts. half represents branch variations determine whether branch fall through next instruction. lower half represents each four possible methods branch instruction calculate target address. first examine lower portion diagram. location which routine branches come from counter register, link register. also possible branch absolute address supplied instruction itself, relative address, which current value program counter value supplied instruction. examine upper half diagram. `branch relative' `branch absolute' instructions require conditional processing, they bypass decision logic calculate target address branch. `branch conditional', `branch conditional absolute' instructions require check determine condition TRUE. condition true, then branch instruction falls through next sequential instruction. condition true, program counter takes branch instruction. Some instructions dependent counter: `bdz', `bdnz', `bdnzt', `bdzt'. When these instructions executed, counter decremented. these instructions, there check determine counter equal other instructions, there check determine counter equal answer 'yes' either case, then branch occurs those branch instructions that dependent another condition. answer 'no', branches fall next instruction.
there another condition involved, that condition must also checked, true branch taken.
SLIDE 2-27
Conditional Branch Instructions
Condition Register opcode: SPR9 Count register (cntr) 2930 0x12
Syntax: BO,BI,target
condition register (0-31)
Description Decrement cntr, branch decremented cntr<>0 condition false Decrement cntr, branch decremented cntr condition false Branch condition false Decrement cntr, branch decremented cntr<>0 condition true Decrement cntr, branch decremented cntr condition true Branch condition true Decrement cntr, branch decremented cntr<>0 Decrement cntr, branch decremented cntr Branch always
Conditional Branch Instructions Here shown Conditional Branch instruction types. mnemonic 'bc' followed three fields: 'BO', 'BI', target address. 'BI' field opcode determines which condition register used evaluating TRUE FALSE. 'BO' field opcode consists numbers table shown here, controls whether condition count determines branching. Each number table describes particular type branch, from very simple such "Branch condition true" more complex, such "Decrement counter, branch decremented counter equal zero condition true." Notice that table there sets values each condition even odd. even value provides default branch prediction. other words, prediction that branch taken displacement negative, taken displacement positive. value provides opposite prediction.
SLIDE 2-28
Conditional Branch Instructions Examples
Conditional branch Simplified mnemonic Description Operation branch true 12,2,target target 13,2,target 12,14,target 4,16,target same above 16,0,target 8,2,target beq- target cr3,target cr4,target cr4,target bdnz target branch true branch true branch false
same above decrement counter branch cntr<>0 bdnzt eq,target decrement counter branch cntr<>0 true
opposite prediction (Y=1)
Conditional Branch Instructions Examples examine conditional branch examples. First shown branch conditional. '12' 'BO' field, indicating that branch condition true. value 'BI' field indicates that routine checks Condition Register, which 'eq' CR0. location target. Therefore, branch occurs equal location target. programmer wished perform same instruction with opposite prediction, would place value '13' 'BO' field. simplified mnemonics, this specified appending minus sign instruction mnemonic. perform similar branch condition register, exemplified 'branch conditional 14'. '14' 'eq' CR3. This equivalent simplified mnemonic 'beq cr3, target.' Another example 'branch conditional indicates that branch taken condition false. '16' refers 'less than' CR4. corresponding simplified mnemonic 'branch less than cr4, target'. Alternatively, stated 'branch greater than equal.' next example 'branch conditional 16'. '16' refers 'Decrement counter, branch decremented counter equal zero'. this case, there condition that tested, zero placed corresponding field. corresponding mnemonic 'branch decrement, zero' target. Finally shown 'branch conditional refers 'Decrement counter, branch decremented counter equal zero condition true'. condition corresponding 'eq' CR0, followed target. corresponding simplified mnemonic 'bdnzt target'.
SLIDE 2-29
Controlling Program Flow Exercises
Loop control condition
Your program: loop: r13,0(r14) cmpwi r13,0 stwu r13,4(r15) loop
Program steps: word from FIFO Compare word zero (update cr0) store word memory buffer Goto word<>0 else goto done
Loop control count
Your program: r13,528 mtspr ctr,r13 loop: r13,0(r14) stwu r13,4(r15) bdnz loop
Program steps: Initialize counter word from FIFO store word memory buffer cntr, cntr<>0 goto done
Controlling Program Flow Exercises Here shown some examples controlling program flow. examine first example. This routine obtains data words from FIFO stores each word memory buffer until data word whose value zero stored buffer. first step load word zero from location which point. This gets word from FIFO. Next compare word zero. This done with 'cmpwi r13, instruction. Then, routine must store word memory buffer. Next, there branch back loop word equal zero. second example similar first. This routine obtains data words from FIFO stores each word memory buffer. first step initialize counter. instructions accomplish this task: 'load immediate r13, 528', followed 'move special register CTR, r13'. next instruction 'load word zero' from location which point. This gets word from FIFO. Next, routine stores word memory buffer. Step executes instruction 'bdnz', therefore decrements counter. counter equal zero, routine goes line else line loop executes times.
SLIDE 2-30
Controlling Program Flow Exercises
Loop control count condition Your program: r13,528 mtspr ctr,r13 loop: r13,0(r14) cmpwi r13,0 stwu r13,4(r15) bdnzf ne,loop Program steps: Initialize counter word from FIFO Compare word zero (update cr0) Store word memory buffer cntr, cntr<>0 word<>0 goto else goto done
Controlling Program Flow Exercises third example combines first two. This routine obtains data words from FIFO stores each word memory buffer until data word with value zero stored buffer, until maximum reached. initialize counter, routine performs 'load immediate' counter register. Next, program performs 'load word zero' from location which point. Next, instruction 'cmpwi r13, compares word zero. Then routine stores word memory buffer. next instruction decrements counter. counter equal zero word equal zero, routine goes else goes That instruction 'bdnzt loop'.
SLIDE 2-31
Writing Subroutines Manipulation
Subroutine example
main code instr. instr. instr. sub1 instr. instr.
sub1
sub1 instr. instr. instr. mfspr rN,lr stwu rN,-4(r1) sub2 rN,0(r1) sub2 addi r1,r1,4 mtspr lr,rN instr. instr. bclr Leaf subroutine
sub2 instr. instr. instr. instr. instr. instr. instr. bclr
Writing Subroutines Manipulation subroutine call instruction saves return address single location, Link Register (LR). This requires subroutine that calls another subroutine save Link Register stack before subroutine call, restore Link Register from stack after subroutine call. Leaf subroutines -subroutines that call others need save restore Link Register. register usage dictates which GPRs must also saved restored. This example shows subroutine, shown italicized code, saving restoring Link Register from stack. There several instructions within main code, including branch subroutine instruction sub1'. When sub1' instruction executed, program counter moves Link Register, sub1 moves program counter. routine sub1 executes several instructions, after which calls another subroutine sub2. Note that sub1 simply calls second subroutine without taking additional steps, contents Link Register overwritten, thus preventing ability return main code. Therefore, necessary programmer save contents Link Register stack. steps accomplish this task. First, 'mfspr instruction moves Link Register contents general-purpose register. Next, 'stwu -4(r1)' instruction stores general-purpose register stack. safe invoke second subroutine with sub2' instruction. Sub2 executes returns sub1. program then gets stored value from stack, stores back into Link Register. Sub1 continues executing, performs 'bclr' instruction return main, using value Link Register.
SLIDE 2-32
Writing Subroutines Manipulation
testing Manipulation device access device, use: where: base address device offset register byte control status data1 data2 timer Memory
rD,d(rA) rS,d(rA)
example:
r13,5(r14) ;get contents data2
device
Writing Subroutines Manipulation Another important function ability access devices. programmer uses same methods test change bits device registers required test change bits locations. This because devices memory mapped. First, load instruction copies data into GPR. Next, routine tests changes data that GPR. Finally, store instruction moves data back device. Many devices 8-bits wide. Motorola advises connecting such devices data pins through Many devices require correct order, which case device should connected 860, connected likewise device. Next, programmer pointer that points base device. Then, individual registers accessed displacement. This example assumes that memory controller implemented. generic example shows 'load byte zero' destination register from location being pointed with offset more specific example shows 'load byte zero' from location pointed with offset This gets contents data2, puts them into r13. possible store information same way, using 'store byte' instruction from source register location pointed with offset
Chapter Accessing Operands Memory
SLIDE
Accessing Operands Memory
What will learn Learn Access memory with variable address Access memory with constant address Access memory with single pointer Increment decrement pointer Push pull data from stack Load 32-bit value into register Access data little endian mode
Memory
GPR0 GPR1 GPR30 GPR31
Store Load
this chapter will learn Access memory with variable address Access memory with constant address Access memory with single pointer Increment decrement pointer Push pull data from stack Load 32-bit value into register Access data little endian mode
SLIDE
Overview Addressing Capabilities
rA=GPR0?
Effective Address
(rA) Update?
Store Load
Memory Access
These instructions that addressing modes: load_mnemonic destination register, memory address i.e. lhax rD,rA,rB ;load halfword algebraic from indexed address into rD,d(rA) ;load word zero-extended from immediate address into store_mnemonic source register,memory address i.e. stwu rS,d(rA) ;store word immediate indexed address with update stbx rS,rA,rB ;store byte indexed address cache_mnemonic memory address i.e. icbi rA,rB ;invalidate instruction cache block from indexed address dcbst rA,rB ;store data cache block, modified, indexed address
Overview Addressing Capabilities Load, store cache instructions addressing modes. There three basic addressing modes: first Register Indirect with Immediate Index, which effective address register plus displacement, 'd'. displacement, 'd', Register Indirect with Immediate Index 16-bit signed value, extended bits. second Register Indirect with Index, which effective address generalpurpose registers. third addressing mode Register Indirect, which used only string loads stores. this case, effective address single register. material presented here focuses first addressing modes, third addressing mode used less often. special case these effective addresses where equal General Purpose Register When equal General Purpose Register literal zero used, instead value GPR0. This reduces effective address single variable constant. Also, Update option causes updated with calculated effective address. This allows pointer incremented decremented. This diagram illustrates addressing mode variations. First, checked determine GPR0. value zero used. not, value specified register used. This value added implemented addressing mode Register Indirect with Index. Alternatively, this value added addressing mode Register Indirect with Immediate Index. addressing mode Register Indirect, specified value added zero.
becomes effective address, which used access memory. there Update option, then effective address into general-purpose register specified Some examples instructions that addressing modes illustrated lower portion diagram. First 'load half-word algebraic indexed', with operands 'load word zero', with operands d(rA). 'Store word' 'store byte' also examples. cache instructions also this form, specifically Register Indirect with Index. this case, there destination register specified operands.
SLIDE
Using (rA|0) Addressing
Instruction Encoding: Opcode rD/rS
rA=GPR0?
1516 Sign Extension
(rA) Update? Store Load Memory Access Effective Address
Using (rA|0) Addressing This diagram illustrates Register Indirect with Immediate Index addressing mode. this case, register specified instruction checked determine equal equal then literal value zero used. equal then value used. resulting value that used added specified displacement, which 16-bit, signed, extended value. provides effective address, which used access memory, specified, updates general-purpose register designated
SLIDE
Using (rA|0) Addressing Examples
Example rA<>GPR0
Instruction: r6,10(r8) 0x0000000A immediate index 0x00010000 Memory address 0x0001000A Result: 0x000000C5 Memory
Instruction: r6,10(r0) Example value used 0x0000000A immediate index 0x00032000 0x00000000 GPR0 Memory address 0x0000000A Result: 0x000000C5
Memory
Example Update
Instruction: lbzu r6,-10(r8) 0xFFFFFFF6 immediate index 0x00010030
Note: EPPC Arch. defines rA=GPR0 rA=rD invalid Update form address.
Memory
Memory address 0x00010026 Results: 0x000000C5 0x00010026
Using (rA|0) Addressing Examples Here shown some example implementations Register Indirect with Immediate Index mode. First, instruction 'lbz r6,10(r8)'. value '10', which 0x0A, added value which this example 0x00010000. value 0x0001000A. byte located 1000A then moved into same example, changing This means that routine uses literal zero, rather than value stored simply '10', 0x0A, allowing program access location from constant address this case, 0x0A. Then instruction gets value from location 0x0A, puts into example Update function shows instruction, 'load byte zero, updated', with operands -10(r8). obtain effective address, value which 0x00010030 pre-decremented result 0x00010026. value 10026 then placed into effective address placed into
SLIDE
Using (rA|0) +(rB) Addressing
1011 Instruction Encoding: Opcode rD/rS Subopcode
(rB) rA=GPR0? (rA) Update? Store Load Memory Access Effective Address
Using (rA|0) (rB) Addressing This diagram illustrates Register Indirect with Index addressing mode. this case, register specified instruction checked determine equal equal then literal value zero used. equal then value specified register used. resulting value that used added contents Register that instruction specifies. This produces effective address, which then used access memory, perhaps update with effective address.
SLIDE
Using (rA|0) +(rB) Addressing Examples
Example rA<>GPR0
Instruction: lbzx r6,r5,r8 0xABCD0000 0x00001000 Memory
Memory address 0xABCD1000 Result: 0x000000C5
Example actual value used 0x00032000 GPR0
Instruction: lbzx r6,r0,r8 0x00000000 literal zero 0x00001000 Memory address 0x00001000 Result: 0x000000C5 Memory
Example Update
Instruction: lbzux r6,r5,r8
Note: EPPC Arch. defines rA=GPR0 rA=rD invalid Update form address.
0xABCD0000 0x00000010 Memory address 0xABCD0010 Results: 0x000000C5 0xABCD0010
Memory
Using (rA|0) (rB) Addressing Here shown some example implementations Register Indirect with Index mode. First, instruction 'lbzx r6,r5,r8'. value added value form effective address, contents that location, move data into same example, changing treated literal zero this case, effective address value plus zero, this case, 0x00001000. This example, therefore, accesses data basis single pointer. contents that memory location then moved Finally, also possible implement Update function with this addressing mode. Here have 'load byte zero updated, indexed'. forms effective address. contents associated location, 0xABCD0010, placed into effective address placed into
SLIDE
Stacking/Unstacking Exercise
Stacking Exercise Write instruction push word GPR3 stack: stwu r3,-4(r1) lower addresses higher addresses Unstacking Exercise Write instructions pull word0 from stack into GPR4: lower addresses Stack word0 word1 Stack word0 word1
r4,0(r1) addi r1,r1,4
higher addresses
Stacking Unstacking Exercise familiar with instructions stacking unstacking. EPPC microprocessor family stack-based family. stack maintained hardware. Software must implement stacks. GPR1 Application Binary Interface (ABI) standard stack pointer. Decrementing stack pointer size bytes data, then storing data memory, pushes data onto stack. Loading data from memory then incrementing stack pointer size bytes data pulls data stack. First, write instruction push word GPR3 stack. This possible writing 'stwu' instruction "store with update" with operands -4(r1). This writes value into location which (r1-4) points, places new, effective address into Next, unstacking, write instructions pull word0 from stack into GPR4. This possible with 'load word zero' instruction, with operands 0(r1). This brings word stack into General Purpose Register next instruction must 'add immediate', with operands r1,r1,4 update stack pointer itself.
SLIDE
Using "lis" Load 32-bit Numbers addi
Operation addi 1011 1516 Instruction Encoding: Opcode
rA=GPR0?
1516 Sign Extension
(rA)
(rD)
Using 'lis' Load 32-bit Numbers addi takes instructions load 32-bit number. 'lis' first. help understand 'lis' instruction, first consider 'add immediate' instruction. This diagram illustrates operation 'addi' instruction. this case, register specified instruction checked determine equal equal then literal value zero used. equal then value used. resulting value that used added signed extended value specified displacement. then placed into destination, general-purpose register.
SLIDE
Using "lis" addi Example
Example addi GPR0 Instruction: addi r6,r0,0x8234 used 0x00032000 Simplified Mnemonic: r6,0x8234
0x00000000 literal zero 0xffff8234
0xffff8234 (sign-extended bits)
Using 'lis' Load 32-bit Numbers addi Example example here shows instruction, 'addi r6,r0,0x8234'. this case, treated literal zero. displacement, sign extended, placed into simplified mnemonic this instruction r6,0x8234'.
SLIDE 3-10
Using "lis" Load 32-bit Numbers addis
Operation addis Instruction Encoding: Opcode
rA=GPR0?
1516
(rA)
(rD)
Using 'lis' Load 32-bit Numbers Another type 'add immediate' instruction 'addis' 'add immediate shifted'. This diagram illustrates operation 'addis' instruction. 'addis' instruction works similar 'addi' instruction. difference that displacement value placed into upper bits, lower bits becomes zero addition displacement register obtain final value destination register.
SLIDE 3-11
Using "lis" addis Example
Example addis GPR0 Instruction: addis r6,r0,0x8234 used 0x00032000 Simplified mnemonic: r6,0x8234
0x00000000 literal zero 0x82340000 (shifted upper halfword) 0x82340000
Using 'lis' Load 32-bit Numbers addis Example example here shows instruction, 'addis r6,r0,0x8234'. represents literal zero, while displacement 0x82340000, which also result that into simplified mnemonic this instruction 'lis r6,0x8234'.
SLIDE 3-12
Loading 32-bit Numbers
r5,constantU r5,r5,constantL
Instruction: addis r5,r0,constantU used 0x00032000
;load upper halfword into ;load lower halfword into
Simplified Mnemonic: r5,constantU
0x00000000 literal zero constantU_0000 data left shifted constantU_0000
Instruction: r5,r5,constantL constantU_0000 0000_constantL data zero padded constantU_constantL Exercise Write instructions store immediate data 0xDEADBEEF effective address 0xABADCAFE.
0xDEAD r5,r5, 0xBEEF 0xABAD r6,r6, 0xCAFE 0(r6)
Loading 32-bit Numbers takes instructions load 32-bit number. have just finished discussing first, which 'lis' instruction. operand "constant Upper" connected operand "constant Lower" word, instruction sequence shown this slide loads word into register GPR5. First shown 'load immediate shifted', which places constant into upper half-word Then immediate' places constant into lower half exercise, write instructions store immediate data 0xDEADBEEF effective address 0xABADCAFE. This possible writing 'load immediate shifted' r5,0xDEAD, followed immediate', r5,r5,0xBEEF. This then followed 'load immediate shifted', r6,0xABAD, followed again immediate', r6,r6,0xCAFE. This then followed 'store word', r5,0(r6), 'store word', r5,r0,r6.
SLIDE 3-13
Summarizing four rA=GPR0 special cases
There only four cases where rA=GPR0 results being used literal zero used instead- address modes: d(r0) r0,rB instructions: addi rD,r0,d addis rD,r0,d Given these values before each instruction, fill result each instruction:
GPR0 0x12340000 GPR1 0xA0000000 GPR2 0x00010000 addi r1,r0,0x1000 addis r1,r0,0x1000 r1,r0,r2 0x00001000 0x10000000 0x12350000
Summarizing Four rA=GPR0 Special Cases There only four cases where rA=GPR0 results literal value zero being used place first cases have with addressing modes, these address register indirect with immediate index, address register indirect with index. other cases occur with 'add immediate' 'add immediate shifted', with position. first example exercise shows instruction 'addi r1,r0,0x1000'. This instructions which treated literal zero. Upon completion this instruction, contains value 0x1000. second example exercise shows another case which position treated literal zero. result 0x1000 upper half word 0x0000 lower half word. Finally, third example exercise shows `add' instruction. does meet four cases, does treat literal zero. result 0x12350000, which then placed into
SLIDE 3-14
What Endian modes?
Endian This data appears organized memory programmer: increasing address 0x12345678 stored memory endian 0x1234 stored memory endian
least significant byte most significant byte
Memory
Little Endian This data appears organized memory programmer: increasing address 0x12345678 stored memory little endian Memory
0x1234 stored memory little endian
What Endian Modes? Endian modes refer order which bytes bits transferred stored memory. Remember that although bits labeled left right this does have anything with significance. Endian default endian order MPC860. first diagram illustrates data appears organized memory programmer. example, value 0x12345678 stored memory endian order. memory dump would reveal bytes exact order stated, from most significant least significant bit. second diagram shows data little endian mode appears organized memory programmer. memory dump same value, 0x12345678, would reveal that bytes stored reverse order.
SLIDE 3-15
PowerPC Little Endian
Data Size bytes) Modification change with 0b100 with 0b110 with 0b111 Example: access byte using address 0b1110 with munged address 0b1001 Memory N+12
0x12345678 stored memory endian address 0x12345678 stored memory address 0x1234 stored memory address N+12 0x1234 stored memory endian address N+12
doubleword aligned address (low bits 000)
PowerPC Little Endian Finally, PowerPC little endian mode available. load store data memory using this mode, address munging occurs. Address munging refers process which, depending size, exclusive `or' binary value occurs with least significant digit address. example, programmer wished access byte location ending 0x0E, then would exclusive `or' with value 0b111, producing munged address 0b1001. byte would accessed address ending example, value 0x12345678 stored endian mode address contents memory look they appear first memory chart lower right corner illustration. contrast, value 0x12345678 stored PowerPC little endian mode address value actually stored address although still stored endian order. Unless have compelling reasons otherwise, Motorola recommends operating MPC860 endian order.
Chapter Using Caches
SLIDE
Using Caches
What Will Learn Learn Enable/disable caches Invalidate cache entries Lock/Unlock critical code segments that need fast deterministic execution time. Maintain cache coherency multi process environment External Memory
Prerequisites Chapter MPC860 Architecture, Part
Cache line (block)
Comparator
Data
Address
Data
Current Address
Match? (Hit)
Cache appnote available more information
this chapter, will learn Enable disable caches Invalidate cache entries Lock unlock critical code segments that need fast deterministic execution time Maintain cache coherency multi-processor environment Please note that there also excellent Cache appnote available which also discusses this material provide more insights you. When requested data cache, cache controller performs external access. Then cache controller loads data into cache line, tags with address location origin data, marks valid. cache controller compares address subsequent memory accesses tag. there match, hit, occurs, data sent requester fraction time external access. There both instruction data cache. Caches have many cache lines. Cache blocks, lines (the terms synonymous) include value line data. Each cache line contains status determine whether data been written line, whether line valid.
Also, each cache line status used lock entry that entry never swapped cache. user wish lock cache line entry case important library interrupt routine. Finally, data cache, there also dirty bit. instruction cache read only, data cache read-write. some cases, data have been written cache, memory. dirty set, should this discrepancy occur.
SLIDE
Cache Organization Flow
Instruction Pointer
way0 set0 tag0 set1 tag1
VALID LOCK
word select way1 tag0 tag1
VALID LOCK
set126 tag126 set127 tag127 comp hit0
tag126 tag127
hit1
comp
Bidirectional line buffer from burst buffer
Cache Organization Flow Data Instruction Caches both Kbyte, two-way associative physically addressed caches. caches have sets, lines set, 4-word line (block) size. instruction cache read-only. data cache read write. First, review operation instruction cache. cache access cycle begins with instruction request from instruction unit core. When core asserts address instruction, bits that address asserted MMU, bits used index into sets cache. lines data selected. tags from both ways then compared against bits 0-20 instruction's address. match constitutes hit. neither tags match, matched invalid, miss. matches, data associated with that cache hit, consisting total four words, becomes available. Bits instruction address used select word from cache line whose matches. instruction immediately transferred from instruction unit core.
case cache miss, address missed instruction driven internal with 4word burst transfer read request. cache controller reads line into cache, replacing this line either there invalid entry present cache, that entry replaced. both lines valid, cache controller replaces least recently used line. Locked lines never replaced.
SLIDE
Data Cache
Effective Address way0 tag0 tag1 tag126 tag127 hit1 comp byte select way1
DIRTY VALID LOCK
set0 tag0 set1 tag1
DIRTY VALID LOCK
set126 tag126 set127 tag127 comp hit0
Bidirectional from line buffer burst buffer
Data Cache Data Instruction Caches both Kbyte, two-way associative, physically addressed caches. caches have sets, lines set, 4-word line (block) size. addition, data cache dirty bits because read write. operation data cache essentially same that instruction cache. cache controller uses same translation mechanism, which involves sending bits address MMU, using next seven bits address select indexed set. read operation same instruction cache read operation. write operation similar read with hit. cache operates either write-through copyback mode, programmed MMU. copy-back mode, cache line which data written changed modified-valid state, meaning that both valid dirty bits set, corresponding external memory location remains unmodified. write operation with write-through mode updates both cache external memory, while associated cache line remains unmodified-valid state, meaning that dirty does set. write miss copy-back mode causes line read from external memory, into empty Least Recently Used (LRU) selected set. write updates line cache, changed modified-valid state, both valid dirty bits set. external memory location modified.
write miss write-through mode writes external memory does affect cache.
SLIDE
Controlling Cache Modes
Write-through (WT=1) WRITE CACHE INTEGER UNIT WRITE CACHE MISS INTEGER UNIT
CACHE
CACHE
Memory allocated cache (no-allocate)
MAIN MEMORY
MAIN MEMORY
Controlling Cache Modes Data cache functions different modes: either write-through copy-back mode. user controls caches with MMU. configures memory into pages, user determines whether each page cache inhibited not. also possible control page basis whether page write-through copy-back mode. When equal data cache operates write-through no-allocate. write memory incurs cache, then cache entry updated, main memory updated. Alternatively, write memory incurs miss, then only main memory updated.
SLIDE
Controlling Cache Modes
Copy-back (WT=0) WRITE CACHE INTEGER UNIT WRITE CACHE MISS (1/2) WRITE CACHE MISS (2/2) INTEGER UNIT Cache miss CACHE MAIN MEMORY CACHE CACHE Burst read from memory MAIN MEMORY INTEGER UNIT
MAIN MEMORY
Controlling Cache Modes When equal data cache operates copy-back allocate. write memory incurs cache, data only written cache, dirty set. Alternatively, write memory incurs miss, cache controller loads line data from main memory into cache, data written only cache, dirty set.
SLIDE
Cache Instructions Operations
Cache Instructions These cache instructions:
dcbf Data Cache Block Flush
Operation:
modified, writes line memory then invalidates line (modified not) Writes line memory Loads line from memory into cache Loads line from memory into cache Zeroes line cache Invalidates line (modified not) Invalidates line
dcbst Data Cache Block Store dcbt Data Cache Block Touch dcbtst Data Cache Block Touch store dcbz Data Cache Block zero dcbi Data Cache Block Invalidate icbi Instruction Cache Block Invalidate
These instructions require memory address specify line accessed. dcbi instruction privileged because modified data lost. compared dcbf.
Cache Instructions Operations caches support PowerPC architecture cache instructions, together with some additional implementation-specific operations that help control cache debug information stored Most time, user prefers enable cache, operate directly upon cache. However, there times when user does wish operate directly cache, perform certain operations. offers different means operate directly cache, first which through cache instructions listed here. PowerPC supports cache instructions shown here. These instructions include writing lines memory, loading lines from memory, invalidating lines, like. These instructions require memory address specify line accessed. `dcbi' instruction privileged because modified data lost. compared `dcbf'.
SLIDE
Cache Instructions Operations
These implementation-specific operations. They implemented writing more special purpose control registers: Comments: Operation: Data Cache Block Lock Useful fast deterministic accesses Instruction Cache Block Load Lock Useful fast deterministic accesses Cache Block Unlock Locked lines cannot flushed/invalidated Cache Invalidate Must done after reset Cache Unlock Must done after reset Data Cache flush cache line Similar dcbf does compare Cache read tags Useful testing debug Cache read registers Useful testing debug special purpose control registers used order control Icache D-cache: D-cache I-cache Description DC_CST IC_CST D/I-cache control status register DC_ADR IC_ADR D/I-cache address register DC_DAT IC_DAT D/I-cache data port (read only)
Cache Instructions Operations (2of Additionally, MPC860 supports implementation-specific operations shown here. They implemented writing more special purpose control registers. These operations include load lock, unlock block, cache unlock all, like. special purpose control registers used control Instruction cache Data cache. programming model consists Data Cache Control Status Register, Instruction Cache Control Status Register, address register data instruction caches, readonly cache data port data instruction caches.
SLIDE
Programming Model
IC_CST I-Cache Control Status Register Reserved Reserved Reserved Reserved
IC_ADR I-Cache Address Register
IC_DAT I-Cache Data Register
Programming Model Here shown programming model with registers supporting instruction cache. first register Instruction Cache Control Status Register. This 32-bit register, with most bits reserved. remaining bits read-only, with exception command field. command field allows user write commands they wish execute while they operating directly cache. Such commands include `cache enable', `load lock', `unlock line', `unlock all'. Instruction Cache Address Register allows user specify particular address used command programmed Control Status Register. Finally, Instruction Cache Data Port Register supports reading data directly from instruction cache.
SLIDE
Programming Model
DC_CST D-Cache Control Status Register Reserved
Reserved
Reserved DC_ADR D-Cache Address Register
Programming Model This slide shows registers supporting data cache. First Data Control Status Register, which bits reserved read-only, with exception command field. command field allows user write commands they wish execute. Such commands include `data cache enable', `lock line', `unlock all', `flush data cache line', like. Data Cache Address Register allows user specify particular address used command programmed Data Control Status Register.
SLIDE 4-10
Programming Model
DC_ADR D-Cache Address Register Reserved Reserved
RESERVED Tags Regs
Number Register Number
DC_DAT D-Cache Data Register Value
Value
Valid Locked Dirty
Reserved
Programming Model Data Cache Address Register also allows user, case certain operations, operate directly line cache specifying number number that line. Finally, Data Cache Data Register supports reading data directly from data cache.
Chapter Memory Management Unit
SLIDE
Memory Management Unit
What Will Learn operates initialize TLBs (Translation Lookaside Buffers) from reset, useful systems requiring pages less data instructions. implement table lookup reload data instruction accesses. Initialize tables Perform tablewalk Initialize proper operation. Configure system. Load reserved entries.
Prerequisites Chapter Architecture, Part Chapter EPPC Cache
Cache appnote available more information
this chapter, will learn Describe operates Initialize Translation Lookaside Buffers (TLB's) from reset. This useful systems requiring pages fewer data instructions. Implement table lookup reload data instruction accesses, including initializing tables performing tablewalk Initialize proper operation Configure system Load reserved entries Please note that there also excellent Cache appnote available which also discusses this material provide more insights you.
SLIDE
What Basic Functions?
Multi-Tasking Operation
transparently monitors memory accesses. access defined allowed, causes interrupt. Access page memory O.S. brings page from disk memory O.S. defines page resident.
Memory Pages Read-only Read/Write TLBs Cacheable Cache-inhibited Task Shared Read/Write Access a
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