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SST29EE020A SST29LE020A SST29VE020A FEATURES: Single Voltage Read
Top Searches for this datasheetMegabit (256K Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A FEATURES: Single Voltage Read Write Operations 5.0V-only SST29EE020A 3.0-3.6V SST29LE020A 2.7-3.6V SST29VE020A Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption Active Current: (typical) (typical) 3.0/2.7V Standby Current: (typical) Fast Page Write Operation Bytes Page, 2048 Pages Page Write Cycle: (typical) Complete Memory Rewrite: (typical) Effective Byte Write Cycle Time: (typical) Fast Read Access Time: 5.0V-only operation: 3.0-3.6V operation: 2.7-3.6V operation: Latched Address Data Automatic Write Timing Internal Generation Write Detection Toggle Data# Polling Hardware Software Data Protection Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available PDIP 32-Pin PLCC 32-Pin TSOP (8mm 20mm) SST29EE020A/29LE020A/29VE020A suited applications that require convenient economical updating program, configuration, data memory. system applications, SST29EE020A/29LE020A/ 29VE020A significantly improve performance reliability, while lowering power consumption. SST29EE020A/29LE020A/29VE020A improve flexibility while lowering cost program, data, configuration storage applications. meet high density, surface mount requirements, SST29EE020A/29LE020A/29VE020A offered 32pin TSOP 32-lead PLCC packages. 600-mil, 32pin PDIP package also available. Figures pinouts. Device Operation page mode EEPROM offers in-circuit electrical write capability. SST29EE020A/29LE020A/ 29VE020A does require separate Erase Program operations. internally timed write cycle executes both Erase Program transparently user. SST29EE020A/29LE020A/29VE020A have industry standard Software Data Protection. SST29EE020A/29LE020A/29VE020A compatible with industry standard EEPROM pinouts functionality. PRODUCT DESCRIPTION SST29EE020A/29LE020A/29VE020A 256K CMOS Page Write EEPROM manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST29EE020A/29LE020A/29VE020A write with single power supply. Internal Erase/Program transparent user. SST29EE020A/29LE020A/ 29VE020A conform JEDEC standard pinouts bytewide memories. Featuring high performance page write, SST29EE020A/29LE020A/29VE020A provide typical byte-write time µsec. entire memory, i.e., KBytes, written page-by-page little seconds, when using interface features such Toggle Data# Polling indicate completion write cycle. protect against inadvertent write, SST29EE020A/29LE020A/29VE020A have on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST29EE020A/29LE020A/29VE020A offered with guaranteed page write endurance cycles. Data retention rated greater than years. 1999 Silicon Storage Technology, Inc. logo SuperFlash registered trademarks Silicon Storage Technology, Inc. These specifications subject change without notice. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Read Read operations SST29EE020A/29LE020A/ 29VE020A controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer read cycle timing diagram further details (Figure Write Page Write SST29EE020A/29LE020A/ 29VE020A uses JEDEC Standard Software Data Protection (SDP) three-byte command sequence. Write operation consists three steps. Step three-byte load sequence Software Data Protection. Step byte-load cycle page buffer SST29EE020A/29LE020A/29VE020A. Steps same timing both operations. Step internally controlled write cycle writing data loaded page buffer into memory array nonvolatile storage. During both three-byte load sequence byte-load cycle, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. internal write cycle initiated TBLCO timer after rising edge CE#, whichever occurs first. write cycle, once initiated, will continue completion, typically within Figures controlled page write cycle timing diagrams Figures flowcharts. Write operation three functional cycles: Software Data Protection load sequence, page load cycle, internal write cycle. Software Data Protection consists specific three-byte load sequence that allows writing selected page will leave SST29EE020A/29LE020A/29VE020A protected Page Write. page load cycle consists loading bytes data into page buffer. internal write cycle consists TBLCO time-out write timer operation. During Write operation, only valid reads Data# Polling Toggle Bit. Page Write operation allows loading bytes data into page buffer SST29EE020A/ 29LE020A/29VE020A before initiation internal write cycle. During internal write cycle, data page buffer written simultaneously into memory array. Hence, page write feature SST29EE020A/ 29LE020A/29VE020A allow entire memory written little seconds. During internal write cycle, host free perform additional tasks, such fetch data from other locations system write next page. each Page Write operation, bytes that loaded into page buffer must have same page address, i.e. through A16. byte loaded with user data will written Figures page write cycle timing diagrams. after completion three-byte load sequence, host loads second byte into page buffer within byte-load cycle time (TBLC) SST29EE020A/29LE020A/29VE020A will stay page load cycle. Additional bytes then loaded consecutively. page load cycle will terminated additional byte loaded into page buffer within (TBLCO) from last byte-load cycle, i.e., subsequent high-to-low transition after last rising edge CE#. Data page buffer changed subsequent byte-load cycle. page load period continue indefinitely, long host continues load device within byte-load cycle time page loaded determined page address last byte loaded. Software Chip Erase SST29EE020A/29LE020A/29VE020A provide Chip Erase operation, which allows user simultaneously clear entire memory array state. This useful when entire device must quickly erased. Software Chip Erase operation initiated using specific six-byte load sequence. After load sequence, device enters into internally timed cycle similar write cycle. During Erase operation, only valid read Toggle Bit. Table load sequence, Figure timing diagram, Figure flowchart. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Write Operation Status Detection SST29EE020A/29LE020A/29VE020A provide software means detect completion write cycle, order optimize system write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising whichever occurs first, which initiates internal write cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST29EE020A/29LE020A/29VE020A internal write cycle, attempt read last byte loaded during byte-load cycle will receive complement true data. Once write cycle completed, will show true data. device then ready next operation. Figure Data# Polling timing diagram Figure flowchart. Toggle (DQ6) During internal write cycle, consecutive attempts read will produce alternating 1's, i.e., toggling between When write cycle completed, toggling will stop. device then ready next operation. Figure Toggle timing diagram Figure flowchart. initial read Toggle will typically "1". Data Protection SST29EE020A/29LE020A/29VE020A provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate write cycle. Power Up/Down Detection: write operation inhibited when less than 2.5V. Write Inhibit Mode: Forcing low, high, high will inhibit write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST29EE020A/29LE020A/29VE020A provide JEDEC approved software data protection scheme data alteration operations, i.e., Write Chip Erase. With this scheme, write operation requires inclusion series three byte-load operations precede data loading operation. three byte-load sequence used initiate write cycle, providing optimal protection from inadvertent write operations, e.g., during system power-up power-down. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Product Identification product identification mode identifies device SST29EE020A/29LE020A/29VE020A manufacturer SST. This mode accessed hardware software operations. hardware operation typically used programmer identify correct algorithm SST29EE020A/29LE020A/29VE020A. Users wish software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. manufacturer device codes same both operations. Product Identification Mode Exit order return standard read mode, Software Product Identification mode must exited. Exiting accomplished issuing Software Exit (reset) operation, which returns device read operation. Reset operation also used reset device read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Table software command codes, Figure timing waveform Figure flowchart. TABLE PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 SST29EE020A Device Code 0001 SST29LE020A Device Code 0001 SST29VE020A Device Code 0001 Data T1.1 FUNCTIONAL BLOCK DIAGRAM 29EE020A/29LE020A/29VE020A X-Decoder 2,097,152 EEPROM Cell Array Address Buffer Latches Y-Decoder Page Latches Control Logic Buffers Data Latches B1.0 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Standard Pinout View F01.0 FIGURE ASSIGNMENTS 32-PIN TSOP PACKAGES 32-Pin PDIP View F02.0 32-Lead PLCC View FIGURE ASSIGNMENTS 32-PIN PLASTIC DIPS 32-LEAD PLCCS TABLE DESCRIPTION Symbol Name A17-A7 Address Inputs A6-A0 DQ7-DQ0 Column Address Inputs Data Input/output Functions provide memory addresses. addresses define page write cycle. Column Addresses toggled load page data. output data during read cycles receive input data during write cycles. Data internally latched during write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control write operations provide 5-volt supply 10%) SST29EE020A, 3-volt supply (3.0-3.6V) SST29LE020A 2.7-volt supply (2.7-3.6V) SST29VE020A Unconnected pins. T2.0 1999 Silicon Storage Technology, Inc. 306-01 2/99 Chip Enable Output Enable Write Enable Power Supply Ground Connection Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A TABLE OPERATION MODES SELECTION Mode Read Page Write Standby Write Inhibit Write Inhibit Software Chip Erase Product Identification Hardware Mode Software Mode Enable Mode DOUT High High DOUT High DOUT Manufacturer Code (BF) Device Code (see notes) Address AIN, Table AIN, Table VIL, VIL, Table Table T3.0 TABLE SOFTWARE COMMAND CODES Command Sequence Page Write Software Chip Erase Software Entry Software Exit Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H Write Cycle Addr(1) Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H 5555H 2AAAH 5555H Write Cycle Addr(1) Data Addr(2) Data 5555H Write Cycle Addr(1) Data 2AAAH Write Cycle Addr(1) Data 5555H Alternate Software 5555H Entry(3) Notes: T4.0 Address format A14-A0 (Hex), Address "Don't Care". Page Write consists loading bytes A0). Alternate six-byte Software Product Command Code software Chip Erase function supported industrial temperature part. Please contact SST, require this function industrial temperature part. Notes Software Product Command Code: With Manufacturer Code BFH, read with SST29EE020A Device Code 24H, read with SST29LE020A/29VE020A Device Code 25H, read with device does remain Software Product Mode powered down. This product supports both JEDEC standard three-byte command code sequence SST's original six-byte command code sequence. designs, recommends that three-byte command code sequence used. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VCC+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VCC+ 1.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1) Note: Outputs shorted more than second. more than output shorted time. SST29EE020A OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C SST29LE020A OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C SST29VE020A OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C CONDITIONS TEST 5V±10% 5V±10% Input Rise/Fall Time Output Load Gate Figures 3.0V 3.6V 3.0V 3.6V 2.7V 3.6V 2.7V 3.6V 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A TABLE SST29EE020A OPERATING CHARACTERISTICS Limits Symbol Parameter Units Test Conditions Power Supply Current CE#=OE#=VIL,WE#=VIH I/Os open, Read Address input VIL/VIH, f=1/TRC Min., VCC=VCC Write CE#=WE#=VIL, OE#=VIH, =VCC Max. ISB1 Standby Current CE#=OE#=WE#=VIH, =VCC Max. (TTL input) ISB2 Standby Current CE#=OE#=WE#=VCC -0.3V. (CMOS input) Max. Input Leakage Current =GND VCC, Max. Output Leakage Current VOUT =GND VCC, Max. Input Voltage Min. Input High Voltage Max. Output Voltage Min. Output High Voltage -400µA, Min. Supervoltage 11.6 12.4 =VIL, Supervoltage Current VIL, VIH, Max. T5.1 TABLE SST29LE020A/29VE020A OPERATING CHARACTERISTICS 3.0-3.6V SST29LE020A, 2.73.6V SST29VE020A Limits Symbol Parameter Units Test Conditions Power Supply Current CE#=OE#=VIL,WE#=VIH I/Os open, Read Address input VIL/VIH, f=1/TRC Min., VCC=VCC Write CE#=WE#=VIL, OE#=VIH, =VCC Max. ISB1 Standby Current CE#=OE#=WE#=VIH, =VCC Max. (TTL input) ISB2 Standby Current CE#=OE#=WE#=VCC -0.3V. (CMOS input) Max. Input Leakage Current =GND VCC, Max. Output Leakage Current VOUT =GND VCC, Max. Input Voltage Min. Input High Voltage Max. Output Voltage Min. Output High Voltage -100 Min. Supervoltage 11.6 12.4 =VIL, Supervoltage Current VIL, VIH, Max. T6.1 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A TABLE POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up Read Operation TPU-WRITE Power-up Write Operation Maximum Units T7.0 T8.0 TABLE CAPACITANCE MHz, other pins open) Parameter Description Test Condition CI/O Capacitance VI/O Input Capacitance Maximum Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter. TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention VZAP_HBM(1) Susceptibility Human Body Model VZAP_MM Susceptibility Machine Model ILTH Latch Note: (1)This Minimum Specification 10,000 2000 Units Cycles Years Volts Volts Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard T9.2 parameter measured only initial qualification after design process change that could affect this parameter. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A CHARACTERISTICS TABLE SST29EE020A READ CYCLE TIMING PARAMETERS Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST29EE020A-120 SST29EE020A-150 Units T10.0 TABLE SST29LE020A READ CYCLE TIMING PARAMETERS Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) SST29LE020A-200 SST29LE020A-250 Parameter Units Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change T11.0 TABLE SST29VE020A READ CYCLE TIMING PARAMETERS Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST29VE020A-200 SST29VE020A-250 Units T12.0 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A TABLE PAGE WRITE CYCLE TIMING PARAMETERS Symbol TOES TOEH TBLC(1) TBLCO(1) TIDA TSCE Parameter Write Cycle (Erase Program) Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software Access Exit Time Software Chip Erase SST29EE020A 0.05 SST29LE/VE020A 0.05 Units T13.1 Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A ADDRESS A17-0 TCLZ DATA VALID TOLZ TOHZ TCHZ HIGH-Z DATA VALID F03.0 HIGH-Z FIGURE READ CYCLE TIMING DIAGRAM Page Write ADDRESS A17-0 5555 2AAA 5555 TOES TOEH TBLC TBLCO BYTE DATA VALID BYTE BYTE F04.0 FIGURE CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Page Write ADDRESS A17-0 5555 2AAA 5555 TBLC TBLCO TOES TOEH BYTE DATA VALID BYTE BYTE F05.0 FIGURE CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM ADDRESS A17-0 TOEH TOES TBLCO F06.0 FIGURE DATA# POLLING TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A ADDRESS A17-0 TOEH TOES TBLCO READ CYCLES WITH SAME OUTPUTS F07.1 FIGURE TOGGLE TIMING DIAGRAM Six-Byte Code Software Chip Erase ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555 TSCE TBLC F09.1 TBLCO FIGURE SOFTWARE CHIP ERASE TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Three-Byte Sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 TIDA DEVICE CODE 0001 TBLC DEVICE CODE SST29EE020A SST29LE020A/29VE020A F10.1 Three-Byte Sequence Software Exit Reset FIGURE SOFTWARE ENTRY READ ADDRESS A14-0 5555 2AAA 5555 TIDA TBLC F11.0 FIGURE SOFTWARE EXIT RESET 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A VIHT INPUT REFERENCE POINTS OUTPUT VILT F12.1 test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Inputs rise fall times (10% 90%) Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS TEST LOAD EXAMPLE TESTER HIGH F13.0 FIGURE TEST LOAD EXAMPLE 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Start Figure Page Write Command Page Address Byte Address Load Byte Data Increment Byte Address F14.0 Byte Address 128? Wait TBLCO Wait Write (TWC, Data# Polling Toggle operation) Write Completed FIGURE WRITE ALGORITHM 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Internal Timer Page Write Initiated Toggle Page Write Initiated Data# Polling Page Write Initiated Wait Read byte from page Read (Data last byte loaded) Write Completed Read same byte true data? Write Completed Does match? Write Completed F15.0 FIGURE WAIT OPTIONS 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Command Sequence Write data: Address: 5555 Write data: Address: 2AAA Write data: Address: 5555 Page Load Operation Load Bytes page data Wait TBLCO Wait Device Written F16.1 FIGURE PAGE WRITE FLOWCHARTS 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Software Product Entry Command Sequence Write data: Address: 5555 Software Product Exit Reset Command Sequence Write data: Address: 5555 Write data: Address: 2AAA Write data: Address: 2AAA Write data: Address: 5555 Write data: Address: 5555 Pause Pause Read Software Return normal operation F17.0 FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Software Chip Erase Command Sequence Write data: Address: 5555 Write data: Address: 2AAA Write data: Address: 5555 Write data: Address: 5555 Write data: Address: 2AAA Write data: Address: 5555 Wait TSCE Chip Erase F18.0 FIGURE SOFTWARE CHIP ERASE COMMAND CODES 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type PDIP PLCC TSOP (die 20mm Unencapsulated Operating Temperature Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed Version Code Voltage 5.0V-only 3.0-3.6V 2.7-3.6V SST29XE020A 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A SST29EE020A Valid combinations SST29EE020A-120-4C- SST29EE020A-150-4C- SST29EE020A-120-4I-EH SST29EE020A-150-4I-EH SST29EE020A-150-4C-U2 SST29LE020A Valid combinations SST29LE020A-200-4C- SST29LE020A-250-4C- SST29LE020A-200-4I-EH SST29LE020A-250-4C-U2 SST29LE020A-200-4C- SST29LE020A-250-4C- SST29LE020A-200-4I-NH SST29EE020A-120-4C- SST29EE020A-150-4C- SST29EE020A-120-4I-NH SST29EE020A-150-4I-NH SST29EE020A-120-4C- SST29EE020A-150-4C- SST29VE020A Valid combinations SST29VE020A-200-4C-EH SST29VE020A-250-4C-EH SST29VE020A-200-4I-EH SST29VE020A-250-4C-U2 SST29VE020A-200-4C-NH SST29VE020A-250-4C-NH SST29VE020A-200-4I-NH Example:Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations. Note: software chip erase function supported industrial temperature part. Please contact SST, require this function industrial temperature part. 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A PACKAGING DIAGRAMS index .600 .625 .530 .550 .065 .075 1.645 1.655 PLCS. Base Plane Seating Plane .015 .050 .120 .150 .170 .200 .008 .012 .600 .070 .080 .045 .065 .016 .022 .100 Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32.pdipPH-ILL.1 32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE: VIEW SIDE VIEW BOTTOM VIEW Optional Identifier .485 .495 .447 .453 .042 .048 .106 .112 .020 MAX. .023 .029 .030 .040 .042 .048 .585 .595 .547 .553 .026 .032 .013 .021 .400 .490 .530 .050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032 Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches. 32.PLCC.NH-ILL.1 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE: 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A IDENTIFIER 1.05 0.95 8.10 7.90 .270 .170 0.15 0.05 18.50 18.30 0.70 0.50 20.20 19.80 32.TSOP-EH-ILL.2 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05) 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE: 1999 Silicon Storage Technology, Inc. 306-01 2/99 Megabit Page Mode EEPROM SST29EE020A SST29LE020A SST29VE020A Area Offices Customer Service Northwest USA, Rocky Mtns. West Canada Central Southwest East East Canada North America Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7754 (408) 523-7661 (727) 771-8819 (978) 356-3845 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000 International Sales Representatives Distributors Australia Belgium Memec Benelux China/Hong Kong Actron Technology Co., Ltd. (HQ) Hong Kong Actron Technology Co., Ltd. Shanghai Actron Technology Co., Ltd. Shenzhen Actron Technology Co., Ltd. Chengdu Actron Technology Co., Ltd. Beijing Actron Technology Co., Ltd. Wuhan Actron Technology Co., Ltd. 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Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873 1999 Silicon Storage Technology, Inc. 306-01 2/99 Other recent searchesTQM969001 - TQM969001 TQM969001 Datasheet PS2811-1 - PS2811-1 PS2811-1 Datasheet PS2811-4 - PS2811-4 PS2811-4 Datasheet PLP1820-6 - PLP1820-6 PLP1820-6 Datasheet EA60QC06EA60QC06-F - EA60QC06EA60QC06-F EA60QC06EA60QC06-F Datasheet BFT39 - BFT39 BFT39 Datasheet BAV99BRW - BAV99BRW BAV99BRW Datasheet AD5666 - AD5666 AD5666 Datasheet
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