DataPath Systems, Inc. 04/22/2000 further information, pleas
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Multiline ATU-C Analog Front Digital Interface V0.1.0
DataPath Systems, Inc.
04/22/2000
further information, please contact: Cormac Conroy 408-365-6073 cconroy@DataPathSystems.Com Phil Welsh 408-365-6058 pwelsh@DataPathSystems.Com FAX: 408-365-0530 Mailing address: 5883 Ferrari, Suite Jose, 95138
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General Description
This document describes digital interfaces future DataPath multi-channel ADSL AFE's product generations following after previously-announced DPS8002 dual e.g., potentially quad, hex, octal etc.
Note: this document, number channels designated numbering scheme channels N-1. simplify notation, symbol used follows: N-1. e.g. quad AFE: M=3, octal M=7.
digital data interface data consists signals: groups each channel, data consists 2-bit data stream 17.6 MHz, support 2.208 incoming data rate, with 16-bit word. each channel, data consists 1-bit data stream either 17.6 MHz, support 1.104 outgoing data rate, 8.832 MHz, support outgoing data rate, with 16-bit word. chip requires single low-jitter 35.328 clock applied MCLK pin. clock generation performed internally converter clocks both paths directly derived from MCLK. independent asynchronous 4-wire serial port used control gains, attenuations, modes etc.
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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Digital Interface Functionality
MCLK
(35.328 MHz)
M=N-1
WCLK
(1.104 kHz)
TX0[1:0]
(17.664 MHz)
Channel
(17.664 8.832 MHz)
TXM[1:0]
(1M.664 MHz)
Serial Parallel Parallel Serial
DAC/TX path Channel MS/s kS/s ADC/RX path
DAC/TX path Channel
Channel
(17.664 8.832 MHz)
MS/s
kS/s ADC/RX path
I/O's
Serial port control
Internal Signals
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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Digital Function Description
Name
MCLK WCLK
following table: digital input, digital output, digital I/O.
Type
Function Description
Master reference clock input: 35.328 Strobe frame-sync digital output digital inputs digital outputs Serial port data output from Serial port clock input Serial port enable input Serial port data input Resets internal state chip (active low)
TXM[1:0],.,TX0[1:0] RXM,.,RX0 S_DOUT S_CLK S_EN S_DIN RESETB
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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Digital Interfaces
Digital Interfaces
incoming word each channel bits wide 17.664 MHz. This support data rate each channel. Internally, data upsampled before going each channel. outgoing word each channel wide 17.664 MHz. This support MS/s each channel. kS/s ADC, digital outputs 8.832 MHz. Below Fig. diagram showing explicitly words transmitted during same time that word received 1.104 MS/s operation; Fig. shows case kS/s operation where digital outputs changing 8.832 rate. TX0[1:0],., TXM[1:0] digital inputs AFE, channel, channels respectively. RX0, outputs from AFE, channel, channels respectively. DA0[15:0], DAM[15:0], internal 16-bit words channels respectively. AD0[15:0], ADM[15:0] internal 16-bit words channels respectively. DA0[], DAM[], AD0[], ADM[] words: LSB. There another signal called "WCLK" which start-of-word marker always either 1.104 kHz. WCLK output from AFE; viewed "start words" signal should used align outgoing transmit digital data incoming receive data. WCLK transitions only rising edge 17.664 clock, therefore aligned also rising edge 35.328 clock. WCLK drawn 1/16 duty cycle clock convenience. However, implemented duty cycle clock. interpretation that start 16-bit data frame indicated simultaneous rising edges MCLK WCLK. There WCLK rising edge each word. MCLK master clock input always 35.328 MHz. This clock immediately divided down 17.664 MHz. diagram also shows internally generated 17.664 clock. Data transmitted from rising edge 17.664 sampled falling edge 17.664 clock.
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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understood that samples data falling edge 17.664 clock (generated presumably inside DSP). This allows data from have more delay than they were sampled falling edge 35.328 clock. WCLK MCLK common between channels. Thus, entire digital interface receive transmit channels implemented using data lines, clock line (MCLK), frame-sync start-of-word signal (WCLK). state interface after power-on undefined: interface resets itself next 16-bit frame (i.e., first complete frame) following power-on. There tristate control outputs. chip does support incoming data rate (for G.lite running Nyquist). With respect electrical levels, digital inputs both 3.3V CMOS compatible, HIGH level outputs power supply voltage VDD_ADIO. will always possible digital output HIGH level separate voltage. With respect threshold trigger level digital inputs AFE, DataPath guarantees that they operate correctly with HIGH level practice, because variable propagation delays etc., cannot wait rising edge WCLK send data needs recognize ahead time send data advance example clock earlier. Both complement offset binary formats available independently data data. However, channels must same format, channels must same format. above modes, sample rates etc. controlled on-chip control registers, accessible thru 4-wire serial control port. details these registers will described relevant product Advance Data Sheet.
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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timing diagram interface with 1.104 MS/s ADC's shown below.
MCLK
(35.328 MHz) 56.6
(Internal)
(17.664 MHz)
Falling edge location critical.
WCLK
(1.104 MHz)
First word
Second word
TX0[1] TX0[0]
DA0[15] DA0[14] DA0[13]
DA0[9] DA0[8] DA0[15]
DA0[8]
DA0[15] DA0[14]
DA0[7]
DA0[6]
DA0[5]
DA0[1]
DA0[0]
DA0[7]
DA0[0]
DA0[7]
DA0[6]
AD0[15] AD0[14] AD0[13]
AD0[9]
AD0[8]
AD0[7]
AD0[0]
AD0[15] AD0[14]
16-bit words 16-bit sample
TXM[2] TXM[0]
DAM[15] DAM[14] DAM[13]
DAM[9] DAM[8] DAM[15]
DAM[8] DAM[15] DAM[14]
DAM[7]
DAM[6]
DAM[5]
DAM[1] DAM[0]
DAM[7]
DAM[0]
DAM[7]
DAM[6]
ADM[15] ADM[14] ADM[13]
ADM[9]
ADM[8]
ADM[7]
ADM[0]
ADM[15] ADM[14]
Fig.
Detailed RX/TX sequence digital interface N-channel ATU-C N-1).
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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timing diagram interface with kS/s ADC's shown below.
MCLK
(35.328 MHz) 56.6
(Internal)
(17.664 MHz)
Falling edge location critical.
WCLK
(552 kHz)
First word
Fourth word
TX0[1] TX0[0]
DA0[15] DA0[14]
DA0[9]
DA0[8]
DA0[15]
DA0[8]
DA0[15] DA0[14]
DA0[7]
DA0[6]
DA0[1]
DA0[0]
DA0[7]
DA0[0]
DA0[7]
DA0[6]
AD0[15]
AD0[14]
AD0[0]
AD0[15]
Four 16-bit words 16-bit sample
TXM[2] TXM[0]
DAM[15] DAM[14]
DAM[9] DAM[8]
DAM[15]
DAM[8]
DAM[15] DAM[14]
DAM[7]
DAM[6]
DAM[1] DAM[0]
DAM[7]
DAM[0]
DAM[7]
DAM[6]
ADM[15]
ADM[14]
ADM[0]
ADM[15]
Fig.
Detailed RX/TX sequence digital interface N-channel ATU-C
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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following detailed timing specifications various digital interfaces.
Output Timing
MCLK
MCLK/2 (Internal)
WCLK
Parameter
MCLK high Data Valid
Symbol
Units
Fig.
Output timing. Conditions: load capacitance
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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Input Timing
MCLK
MCLK/2 (Internal)
TSU1
Inputs TXi[1:0]
Parameter
inputs setup time inputs hold time
Symbol
TSU1
Units
Fig.
input timing. Conditions: load capacitance
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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Serial Port Interface
4.2.0 Introduction
serial port interface controls read/write registers chip. interface consists active-low enable input (S_EN), serial clock input (S_CLK), data input (S_DIN) data output (S_DOUT). timing diagram operation serial port shown Fig. After S_EN asserted, chip-select (CS), serial port register address (A5-A0) read/write control (R/W) serially clocked rising edge S_CLK.
Note that order allow future register address space expansion, this scheme
uses 6-bit register address, different from previous DataPath ADSL AFE's, which used 5-bit address. write operation (R/W=1), addressed register updated upon receiving 16-bit data (D15-D0). read oper ation (R/W=0), 16-bit contents addressed register sequentially shifted S_DOUT alling edge S_CLK. Fig. S_DOUT iven only when data being read. Otherwise istated. Note: this implementation, chip select (CS) tied internall chip, should ways real usage. Apart from issue, 6-bit address format, this interface identical that present existing DPS8000 DPS8001 family products.
4.2.1 Serial Port Timing
timing diagram serial port shown Fig.
S_EN S_CLK S_DIN S_DOUT
Fig. Timing diagram serial port
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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4.2.2 Serial Port
TCYC TSU1 TPWH
S_EN
TPWL
S_CLK
TSU2
S_DIN
S_DOUT
Parameter
S_CLK clock period S_CLK high time S_CLK time S_EN S_CLK high S_CLK high S_EN high S_EN inactive pulse width S_DIN setup time S_DIN hold time S_CLK S_DOUT delay S_EN inactive S_DOUT
Symbol
TCYC TPWH TPWL TSU1 TSU2
Units
Conditions: load capacitance
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front Digital Interface V0.1.0 04/22/2000
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