PID7t-603e implementation PowerPC603e (after named 603r) low-power imp

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PID7t-603e implementation PowerPC603e (after named 603r) low-power imp

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SPECint95, SPECfp95 (estimated) Superscalar instructions clock peak). Dual 16KB caches. Selectable clock. 32-bit compatibility PowerPC implementation. chip debug support. typical Watts (200 MHz), full operating conditions. Nap, doze sleep modes power savings.
PID7t-603e implementation PowerPC603e (after named 603r) low-power implementation reduced instruction computer (RISC) microprocessors PowerPCfamily. 603r pin-to-pin compatible with PowerPC 603E 603P Cerquad package. 603r implements 32-bit effective addresses, integer data types bits, floating-point data types bits. 603r low-power design provides four software controllable power-saving modes. 603r superscalar processor capable issuing retiring many three instructions clock. Instructions execute order increased performance however, 603r makes completion appear sequential. 603r integrates five execution units able execute five instructions parallel. 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches instructions data on-chip instruction data memory management units (MMUs). MMUs contain 64-entry, two-way set-associative, data instruction translation lookaside buffers that provide support demand-paged virtual memory address translation variable-sized block translation. 603r selectable 64-bit data 32-bit address bus. 603r interface protocol allows multiple masters complete system resources through central external arbiter. 603r supports single-beat burst data transfers memory accesses, supports memory-mapped I/O. 603r uses advanced, 2.5/3.3-V CMOS process technology maintains full interface compatibility with devices. 603r integrates system testability debugging features through JTAG boundary-scan capability.
TSPC603r
CERQUAD MQUAD Packages
PowerPC 603eRISC MICROPROCESSOR Family PID7t-603e Specification
Target Specification
Screening Quality /Packaging
This product manufactured full compliance with: MIL-STD-883 class (TBC) According standards Full military temperature range -55°C, +125°C) Industrial temperature range -40°C, +110°C)
Commercial temperature range 0°C, +70°C) Internal Power Supply Cerquad MQUAD packages
MQUAD CERQUAD
suffix CERQUAD Ceramic Leaded Chip Carrier Cavity
suffix MQUAD Metal Quad Flat Pack Cavity
August 2000
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SUMMARY
GENERAL DESCRIPTION
INTRODUCTION ASSIGNMENTS 2.1. CERQUAD MQUAD packages 2.2. Pinout listing SIGNAL DESCRIPTION
5.2. Instruction addressing modes 5.2.1. PowerPC instruction addressing modes 5.2.2. PowerPC 603r microprocessor instruction 5.3. Cache implementation 5.3.1. PowerPC cache characteristics 5.3.2. PowerPC 603r microprocessor cache implementation 5.4. Exception model 5.4.1. PowerPC exception model 5.4.2. PowerPC 603r microprocessor exception model 5.5. Memory management 5.5.1. PowerPC memory management 5.5.2. PowerPC 603r microprocessor memory management 5.6. Instruction timing PREPARATION DELIVERY 6.1. Packaging 6.2. Certificate compliance HANDLING PACKAGE MECHANICAL DATA 8.1. Mechanical dimensions wire-bond CERQUAD package 8.2. Mechanical dimensions wire-bond MQUAD package
DETAILED SPECIFICATIONS
SCOPE APPLICABLE DOCUMENTS REQUIREMENTS 3.1. General 3.2. Design construction 3.2.1. Terminal connections 3.2.2. Lead material finish 3.3. Absolute maximum ratings 3.4. Recommended Operating Conditions 3.5. Thermal characteristics 3.5.1. Generalities 3.5.2. Thermal management example 3.6. Power consideration 3.6.1. Dynamic Power Management 3.6.2. Programmable Power Modes 3.6.3. Power Management Modes 3.6.4. Power Management Software Considerations 3.6.5. Power dissipation 3.7. Marking ELECTRICAL CHARACTERISTICS 4.1. General requirements 4.2. Static characteristics 4.3. Dynamic characteristics 4.3.1. Clock specifications 4.3.2. Input specifications 4.3.3. Output specifications 4.4. JTAG timing specifications FUNCTIONAL DESCRIPTION 5.1. PowerPC registers programming model 5.1.1. General-Purpose Registers (GPRs) 5.1.2. Floating-Point Registers (FPRs) 5.1.3. Condition Register (CR) 5.1.4. Floating-Point Status Control Register (FPSCR) 5.1.5. Machine State Register (MSR) 5.1.6. Segment Registers (SRs) 5.1.7. Special-Purpose Registers (SPRs)
CLOCK RELATIONSHIPS CHOICE SYSTEM DESIGN INFORMATION 10.1. Power Supply Filtering 10.2. Decoupling Recommendations 10.3. Connection Recommendations 10.4. Pull-up Resistor Requirements DEFINITIONS DIFFERENCES WITH COMMERCIAL PART ORDERING INFORMATION
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TSPC603r
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GENERAL DESCRIPTION
Fetch Unit Completion Unit Dispatch Unit Branch Unit
Integer Unit
Unit
Rename
Load/ Store Unit
Rename
File
Float Unit
Data Cache
Inst. Cache
Interface Unit address data
System
Figure Block diagram
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INTRODUCTION
603r low-power implementation PowerPC microprocessor family reduced instruction commuter (RISC) microprocessors. 603r implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits, floating-point data types bits. 64-bit PowerPC microprocessors, PowerPC architecture provides 64-bit integer data types, 64-bit addressing, other features required complete 64-bit architecture. 603r provides four software controllable power-saving modes. Three modes (the nap, doze, sleep modes) static nature, progressively reduce amount power dissipated processor. fourth dynamic power management mode that causes functional units 603r automatically enter low-power mode when functional units idle without affecting operational performance, software execution, external hardware. 603r superscalar processor capable issuing retiring many three instructions clock. Instructions execute order increased performance however, 603r makes completion appear sequential. integrates five execution units integer unit (IU), floating-point unit (FPU), branch processing unit (BPU), load/store unit (LSU) system register unit (SRU). ability execute five instructions parallel simple instructions with rapid execution times yield high efficiency throughput 603r-based systems. Most integer instructions execute clock cycle. pipelined single-precision multiply-add instruction issued every clock cycle. 603r provides independent on-chip, Kbyte, four-way set-associative, physically addressed caches instructions data on-chip instruction data memory management units (MMUs). MMUs contain 64-entry, two-way set-associative, data instruction translation lookaside buffers (DTLB ITLB) that provide support demand-paged virtual memory address translation variable-sized block translation. TLBs caches least recently used (LRU) replacement algorithm. 603r also supports block address translation through independent instruction data block address translation (IBAT DBAT) arrays four entries each. Effective addresses compared simultaneously with four entries array during block translation. accordance with PowerPC architecture, effective address hits both array, translation takes priority. 603r selectable 64-bit data 32-bit address bus. 603r interface protocol allows multiple masters compete system resources through central external arbiter. 603r provides three-state coherency protocol that supports exclusive, modified, invalid cache states. This protocol compatible subset MESI four-state protocol operates coherently systems that contain four-state caches. 603r supports single-beat burst data transfers memory accesses, supports memory-mapped I/O. 603r uses advanced, 0.29 metal layer CMOS process technology maintains full interface compatibility with devices.
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ASSIGNMENTS
2.1. CERQUAD MQUAD packages
Figure CERQUAD view
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2.2. Pinout listing
Table 1.Power ground pins
CERQUAD MQUAD packages (AVDD) Internal logic Output drivers 122, 137, 147, 157, 167, 177, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 19,29, 116, 132, 142, 152, 162, 172, 182, 206, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228,
Table 2.Signal pinout listing
Signal name A[0-31] AACK AP[0-3] ARTRY CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBDIS DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY HRESET L1_TSTCLK1 L2_TSTCLK1 LSSD_MODE1 CERQUAD MQUAD number 179, 178, 176, 175, 174, 170, 169, 168, 166, 165, 164, 160, 159, 158, 151, 144, 231,230,227,226 225,150 115, 114, 113, 110, 109, 108, 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100,
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Signal name PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2] TT[0-4]
Notes These test signals factory only must pulled normal machine operation.
OVDD inputs supply power drivers inputs supply power processor core. Future members family different OVDD input levels.
CERQUAD MQUAD number 213, 211, 210, 224, 197, 196, 191, 190, 185, 184,
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SIGNAL DESCRIPTION
Figure AUCUN LIEN AUCUN LIEN describe signals TSPC603r indicate signal functions. test signals, TRST, TMS, TCK, TDO, comply with subset P-1149.1 IEEE testability standard. signals LSSD_MODE, LI_TSTCLK L2_TSTCLK test signals factory only must pulled normal machine operations. ADDRESS ARBITRATION A[0-31] ADDRESS AP[0-3] TT[0-4] TBST TSIZ[0-2] TRANSFER ATTRIBUTE CSE[0-1] TC[0-1] DBWO DATA ATTRIBUTION
ADDRESS START
DH[0-31], DL[0-31] DP[0-7] DBDIS DRTRY INT, CKSTP_IN, CKSTP_OUT HRESET, SRESET RSRV QREQ, QACK TBEN TLBISYNC INTERRUPTS CHECKSTOPS RESET DATA TERMINATION DATA TRANSFER
603r
PROCESSOR STATUS
AACK ADDRESS TERMINATION ARTRY SYSCLK CLOCKS CLK_OUT PLL_CFG[0-3] POWER SUPPLY INDICATOR VOLTDETGND
TRST, TCK, TMS, TDI, LSSD_MODE, L1_TSTCLK, L2_TSTCLK OVDD AVDD
JTAG/COP INTERFACE LSSD TEST CONTROL
POWER SUPPLY
Figure Functional signal groups Table 3.Address data signal index
Signal name Address Data Data Mnemonic A[0-31] DH[0-31] DL[0-31] Signal function output, physical address data transferred. input, represents physical address snoop operation. Represents state data, during data write operation output, during data read operation input. Represents state data, during data write operation output, during data read operation input. Signal type
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Table 4.Signal index
Signal name Address Acknowledge Address Busy Address Parity Mnemonic AACK AP[0-3] Signal function address phase transaction complete output, 603r address master input, address output, represents parity each bytes physical address transaction input, represents parity each bytes physical address snooping operations Incorrect address parity detected snoop output, detects condition which snooped address tenure must retried input, must retry preceding address tenure Signal type Input
Address Parity Error Address retry
ARTRY
Output
grant request Cache Inhibit Test Clock Checkstop Input Checkstop Output Cache Entry Data Busy Data Disable Data Grant Data Write Only Data Parity Data Parity Error Data Retry Global Hard Reset Interrupt
CLK_OUT CKSTP_IN CKSTP_OUT CSE[0-1] DBDIS DBW0 DP[0-7] DRTRY HRESET LSSD_MODE L1_TSTCLK L2_TSTCLK
May, with proper qualification, assume mastership address Input Request mastership address single-beat transfer will cached Provides clock output testing monitoring Must terminate operation internally gating clocks, release outputs detected checkstop condition ceased operation Cache replacement element current transaction reloading into writing cache output, 603r data master input, another device master (For write transaction) must release data data parity high impedance during following cycle May, with proper qualification, assume mastership data data tenure output, parity each bytes data write transactions input, parity each byte read data Incorrect data parity Must invalidate data from previous read operation output, transaction global input, transaction must snooped 603r Initiates complete hard reset operation Initiates interrupt register LSSD test control signal factory only LSSD test control signal factory only LSSD test control signal factory only Initiates machine check interrupt operation register EMCP HID0 register Output Output Output Input Output Output Input Input Input Output Input Input Input Input Input Input Input
Machine Check Interrupt
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Signal name
Mnemonic
Signal function
Signal type Input Input Output Output Input Input Input Input Input Output Input Input Output Input Input Input Input
Configuration Quiescent Acknowledge Quiescent Request Reservation System Management Interrupt Soft Reset System Clock Transfer Acknowledge Timebase Enable Transfer Burst Transfer Code Test clock Test data input Test data output Transfer Error Acknowledge TLBI Sync Test mode select Test reset Transfer Size Transfer start
PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2]
Configures operation internal processor clock frequency activity terminated 603r enter quiescent power) state requesting activity normally enter quiescent (low power) state Represents state reservation coherency reservation address register Initiates system management interrupt operation register Initiates processing reset exception Represents primary clock input 603r, clock frequency 603r operation single-beat data transfer completed successfully data beat burst transfer completed successfully timebase should continue clocking output, burst transfer progress input, when snooping single-beat reads Special encoding transfer progress Clock signal IEEE P1149.1 test access port (TAP) Serial data input Serial data output error occurred Instruction execution should stop after execution tlbsync instruction Selects principal operations test-support circuitry Provides asynchronous reset controller memory accesses, these signals along with TBST indicate data transfer size current operation output, begun memory transaction address transfer attribute signals valid input, another master begun transaction address transfer attribute signals valid snooping (see GBL) Type transfer progress single-beat transaction write-through Available only package Indicates power supply that low-voltage processor present.
Transfer Type Write-Through
TT[0-4]
Output Output
Power supply indicator VOLTDETGND
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DETAILED SPECIFICATIONS
SCOPE
This drawing describes specific requirements microprocessor TSPC603r, compliance with MIL-STD-883 class standard screening.
APPLICABLE DOCUMENTS
MIL-STD-883 Test methods procedures electronics. MIL-PRF-38535 General specifications microcircuits.
REQUIREMENTS
3.1. General microcircuits accordance with applicable documents specified herein. 3.2. Design construction 3.2.1. Terminal connections terminal connections shall shown Figure DETAILED SPECIFICATIONS) Figure GENERAL DESCRIPTION). 3.2.2. Lead material finish Lead material finish shall specified MIL-STD-1835 (see enclosed 3.3. Absolute maximum ratings Absolute maximum ratings stress rating only functional operation maximum guaranteed. Stresses beyond those listed affect device reliability cause permanent damage device
Table 5.Absolute maximum rating 603r
Parameter Core supply voltage supply voltage supply voltage Input voltage Storage temperature range
Symbol AVdd OVdd Tstg
-0.3 -0.3 -0.3 -0.3
2.75 2.75 +150
Unit
Notes: Functional operating conditions given electrical specifications. Stresses beyond absolute maximums listed affect device reliability cause permanent damage device. Caution Input voltage must greater than OVdd more than times, including during power-on reset. Caution OVdd voltage must greater than Vdd/AVdd more than times, including during power-on reset. Caution Vdd/AVdd voltage must greater than OVdd more than times, including during power-on reset.
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3.4. Recommended Operating Conditions These recommended tested operating conditions. Proper device operation outside these conditions guaranteed.
Parameter Core supply voltage supply voltage supply voltage Input voltage Case Operating temperature Junction operating temperature
Symbol AVdd OVdd
2.375 2.375 3.135
2.625 2.625 3.465 +125 +135
Unit
3.5. Thermal characteristics This section provides thermal management data 603r this information based typical desktop configuration using lead, wire-bond CERQUAD MQUAD packages with cavity (silicon attached bottom package). This configuration allows dissipate through PCB. 3.5.1.Generalities thermal characteristics wire-bond CERQUAD package follows Thermal resistance (junction-to-bottom case) (typical)= Rqjc 2.5°C/Watt. Thermal resistance (junction-to-top case) typically 25°C/W. thermal characteristics MQUAD package Thermal resistance (junction-to-bottom case) (typical) Rqjc 1.3°C/Watt. 3.5.2.Thermal management example following example based typical desktop configuration using wire-bond package with cavity (see 3.5.1). junction temperature calculated from junction ambient thermal resistance, follows Junction temperature Where ambient temperature vicinity device Rqja junction-to-ambient thermal resistance Rqjc junction-to-case thermal resistance device case-to-heat sink thermal resistance interface material heat sink-to-ambient thermal resistance power dissipated device Because dissipation made through PCB, user values, vary considerably regarding customer application. typical customer application, 0.5°C/W, 3°C/W 110°C, estimated. 110°C (2.5 125°C. Note that verification external thermal resistance case temperature should performed each application. Thermal resistance vary considerably many factors including degree turbulence. 3.6. Power consideration PowerPC603r microprocessor specifically designed low-power operation. 603e microprocessor version, 603r provides both automatic program-controllable power reduction modes progressive reduction power consumption. This chapter describes hardware support provided 603r power management. Rqjc (Rcs Rsa) Rqjc (Rqjc Rsa)
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3.6.1. Dynamic Power Management Dynamic power management automatically powers down individual execution units 603r, based upon contents instruction stream. example, floating-point instructions being executed, floating-point unit automatically powered down. Power actually removed from execution unit instead, each execution unit independent clock input, which automatically controlled clock-by- clock basis. Since CMOS circuits consume negligible power when they switching, stopping clock execution unit effectively eliminates power consumption. operation completely transparent software external hardware. Dynamic power management enabled setting HID0 power-up, following HRESET. 3.6.2. Programmable Power Modes 603r provides four programmable power states full power, doze, sleep. Software selects these modes setting (and only one) three power saving mode bits. Hardware enable power management state through external asynchronous interrupts hardware interrupt causes transfer program flow interrupt handler code. appropriate mode then software. 603r provides separate interrupt interrupt vector power management system management interrupt (SMI). 603r also contains decrement timer which allows enter doze mode predetermined amount time then return full power operation through decrementer interrupt (DI). Note that 603r cannot switch from power management mode another without first returning full mode. sleep modes disable snooping therefore, hardware handshake provided ensure coherency before 603r enters these power management modes. AUCUN LIEN summarizes four power states.
Table 6.Power 603r Microprocessor Programmable Power Modes
Mode
Full power Full power (with DPM) Doze
Functioning Units
units active Requested logic demand snooping Data cache needed Decrementer timer
Activation Method
Full-Power Wake Method
instruction dispatch Controlled
External asynchronous exceptions* Decrementer interrupt Reset
Decrementer timer
Controlled hardware External asynchronous exceptions software Decrementer interrupt Reset
Sleep
None
Controlled hardware External asynchronous exceptions software Reset
Exceptions referred interrupts architecture specification
3.6.3. Power Management Modes following sections describe characteristics 603r's power management modes, requirements entering exiting various modes, system capabilities provided 603r while power management modes active. Full-Power Mode with Disabled Full-power mode with disabled power mode selected when enable (bit HID0 cleared. Default state following power-up HRESET. functional units operating full processor speed times. Full-Power Mode with Enabled Full-power mode with enabled (HID0[11] provides on-chip power management without affecting functionality performance 603r. Required functional units operating full processor speed. Functional units clocked only when needed. software hardware intervention required after mode set. Software/hardware performance transparent. Doze Mode Doze disables most functional units maintains cache coherency enabling interface unit snooping. snoop will cause 603r enable data cache, copy data back memory, disable cache, fully return doze state.
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Most functional units disabled. snooping time base/decrementer still enabled. Dose mode sequence doze (HID0[8) 603r enters doze mode after several processor clocks. Several methods returning full-power mode Assert INT, SMI, decrementer interrupts. Assert hard reset soft reset. Transition full-power state takes more than processor cycles. running locked SYSCLK. Mode mode disables 603r still maintains phase locked loop (PLL) time base/decrementer. time base used restore 603r full-on state after programmed amount time. Because snooping disabled sleep mode, hardware handshake using quiesce request (QREQ) quiesce acknowledge (QACK) signals requires maintain data coherency. 603r will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603r will enter sleep mode. Time base/decrementer still enabled. Most functional units disabled (including snooping). nonessential input receivers disables. mode sequence (HID0[9] 603r asserts quiesce request (QREQ) signal. System asserts quiesce acknowledge (QACK) signal. 603r enters sleep mode after several processor clocks. Several methods returning full-power mode Assert INT, SPI, decrementer interrupts. Assert hard reset soft reset. Transition full-power takes more than processor cycles. running locked SYSCLK. Sleep Mode Sleep mode consumes least amount power four modes since functional units disabled. conserve maximum amount power, disabled SYSCLK removed. fully static design 603r, internal processor state preserved when internal clock present. Because time base decrementer disabled while 603r sleep mode, 603r's time base contents will have updated from external time base following sleep mode accurate time-ofday maintenance required. Before 603r enters sleep mode, 603r will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603r will enter sleep mode. functional units disabled (including snooping time base). nonessential input receivers disabled Internal clock regenerators disabled. still running (see below). Sleep mode sequence sleep (HID0[10] 603r asserts quiesce request (QREQ). System asserts quiesce acknowledge (QACK). 603r enters sleep mode after several processor clocks. Several methods returning full-power mode Assert INT, SMI, interrupts. Assert hard reset soft reset.
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disabled SYSCLK removed while sleep mode. Return full-power mode after SYSCLK disabled sleep mode Enable SYSCLK. Reconfigure into desired processor clock mode. System logic waits startup relock time (100 msec). System logic asserts sleep recovery signals (for example, SMI). 3.6.4. Power Management Software Considerations Since 603r dual issue processor with -of-order execution capability, care must taken power management mode entered. Furthermore, sleep modes require outstanding operations completed before power management mode entered. Normally during system configuration time, power management modes would selected setting appropriate HID0 mode bit. Later power management mode invoked setting MSR[POW] bit. provide clean transition into power management mode, stmsr[POW] should preceded sync instruction followed isync instruction. 3.6.5. Power dissipation
Table 7.Power dissipation Vdd/AVdd OVdd 125°C clock Frequency
Full-On Mode (DPM Enabled) Typical Doze Mode Typical Mode Typical Sleep Mode Typical Units
Sleep Mode-PLL Disabled Typical
Sleep Mode-PLL SYSCLK Disabled Typical Maximum
Notes: These values apply valid PLL_CFG[0-3] settings include output driver power (OVDD) analog supply power (AVDD). OVDD power system dependent typically VDD. Worst-case AVDD Typical power average value measured VDD=AVDD=2.5 OVV=3.3 system executing typical applications benchmark sequences. Maximum power measured VDD=2.625 using worst-case instruction mix. calculate power consumption temperature (-55 °C), factor 1.25.
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3.7. Marking document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum Thomson logo, Manufacturer's part number, Class identification applicable, Date-code inspection lot, identifier available, Country manufacturing.
ELECTRICAL CHARACTERISTICS
4.1. General requirements static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below Table Static electrical characteristics electrical variants. Tables Dynamic electrical characteristics 603r. These specifications processor core frequencies. processor core frequency determined (SYSCLK) frequency settings PLL_CFG0 PLL_CFG3 signals. timings specified respective rise edge SYSCLK. 4.2. Static characteristics
Table 8.Electrical characteristics AVdd OVdd -55°C 125°C
Characteristics Input high voltage (all inputs except SYSCLK) Input voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input voltage Input leakage current 3.465 V(1, V(1, Hi-Z (off-state) leakage current 3.465 V(1, V(1, Output high voltage Output voltage Symbol CVIH CVIL ITSI ITSI 10.0 15.0 Unit
Capacitance, MHz(2) (excludes ABB, DBB, ARTRY) Capacitance, MHz(2) (for ABB, DBB, ARTRY)
Notes:
Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, JTAG signals). Capacitance periodically sampled rather than tested. Leakage currents measured nominal OVdd both OVdd Vdd. Same variation (for example, both OVdd vary either
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4.3. Dynamic characteristics 4.3.1. Clock specifications Table provides clock timing specifications defined Figure
Table 9.Clock timing specifications
AVdd OVdd -55°C 125°C Characteristics Processor frequency frequency SYSCLK (bus) frequency SYSCLK cycle time SYSCLK rise fall time SYSCLK duty cycle (1.4V measured) SYSCLK jitter 603r internal relock time
Notes: Rise fall times SYSCLK input measured from Cycle-to-cycle jitter guaranteed design. Timing guaranteed design characterization, tested. relock time maximum amount time required lock after stable Vdd, OVdd, AVdd SYSCLK reached during power-on reset sequence. This specification also applies when been disabled subsequently re-enabled during sleep mode. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence. Caution SYSCLK frequency PLL_CFG[0-3] settings must chosen such that resulting SYSCLK (bus) frequency, (core) frequency, (VCO) frequency exceed their respective maximum minimum operating frequencies. Refer PLL_CFG[0-3] signal description valid PLL_CFG[0-3] settings.
66.7 60.0 ±150 33.3 13.3 40.0
66.7 60.0 ±150
Unit
Note
40.0
Figure SYSCLK input timing diagram
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4.3.2. Input specifications Table provides input timing specifications 603r defined Figure Figure
Table 10.Input timing specifications
AVdd OVdd -55°C 125°C Characteristics 166,200 Address/data/transfer attribute inputs valid SYSCLK (input setup) other inputs valid SYSCLK (input setup) Mode select inputs valid HRESET (input setup) (for DRTRY, QACK TLBISYNC) SYSCLK address/data/transfer attribute inputs invalid (input hold) SYSCLK other inputs invalid (input hold) HRESET mode select inputs invalid (input hold) (for DRTRY, QACK, TLBISYNC) tsysclk 4,5,6,7 4,6,7 Unit Note
Notes input specifications measured from level (0.8 signal question rising edge input SYSCLK. Both input output timings measured pin. Figure Address/data/transfer attribute input signals composed following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7]. other input signals composed following: ABB, DBB, ARTRY, AACK, DBG, DBWO, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. setup hold time with respect rising edge HRESET. Figure tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. These values guaranteed design, tested. This specification configuration mode only. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence.
Figure Input timing diagram
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Figure Mode select input timing diagram
4.3.3. Output specifications Table provides output timing specifications 603r (shown Figure
Table 11.Output timing specifications
AVdd OVdd -55°C 125°C Characteristic SYSCLK output driven (output enable time) SYSCLK output valid (5.5 ABB, ARTRY, DBB) SYSCLK output valid (TS, ABB, ARTRY, DBB) SYSCLK output valid (5.5 except ABB, ARTRY, DBB) SYSCLK output valid (all except TS,ABB,ARTRY,DBB) SYSCLK output invalid (output hold) SYSCLK output high impedance (all except ARTRY, ABB, DBB) SYSCLK ABB, DBB, high impedance after precharge SYSCLK ARTRY high impedance before precharge SYSCLK ARTRY precharge enable tsysclk 166,200 11.0 tsysclk Unit Note
Maximum delay ARTRY precharge SYSCLK ARTRY high impedance after precharge
tsysclk tsysclk
Notes:1 output specifications measured from rising edge SYSCLK level (0.8 signal question. Both input output timings measured pin. Figure maximum timing specifications assume This minimum parameter assumes SYSCLK output valid (5.5 includes extra delay associated with discharging external voltage from instead from CMOS levels instead CMOS levels). tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. Output signal transitions from Nominal precharge width tsysclk. Nominal precharge width ARTRY tsysclk.
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Figure Output timing diagram
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4.4. JTAG timing specifications
Table 12.JTAG timing specifications (independent SYSCLK) AVdd OVdd -55°C 125°C
Figure Clock input timing diagram
Figure TRST timing diagram
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Figure Boundary-scan timing diagram
Figure Test access port timing diagram
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FUNCTIONAL DESCRIPTION
5.1. PowerPC registers programming model PowerPC architecture defines register-to-register operations most computational instructions. Source operands these instructions accessed from registers provided immediate values embedded instruction opcode. three-register instruction format allows specification target register distinct from source operands. Load store instructions transfer data between registers memory. PowerPC processors have levels privilege supervisor mode operation (typically used operating system) user mode operation (used application software). programming models incorporate GPRs, FPRs, special-purpose registers (SPRs) several miscellaneous registers. Each PowerPC microprocessor also unique hardware implementation (HID) registers. Having access privilege instructions, registers, other resources allows operating system control application environment (providing virtual memory protecting operating-system critical machine resources). Instructions that control state processor, address translation mechanism, supervisor registers executed only when processor operating supervisor mode. following sections summarize PowerPC registers that implemented 603r. 5.1.1. General-Purpose Registers (GPRs) PowerPC architecture defines user-level, general-purpose registers (GPRs). These registers either bits wide 32-bit PowerPC microprocessors bits wide 64-bit PowerPC microprocessors. GPRs serve data source destination integer instructions. 5.1.2. Floating-Point Registers (FPRs) PowerPC architecture also defines user-level, 64-bit floating-point registers (FPRs). FPRs serve data source destination floating-point instructions. These registers contain data objects either single double precision floating-point formats. 5.1.3. Condition Register (CR) 32-bit user-level register that consists eight four-bit fields that reflect results certain operations, such move, integer floating-point compare, arithmetic, logical instructions, provide mechanism testing branching. 5.1.4. Floating-Point Status Control Register (FPSCR) floating-point status control register (FPSCR) user-level register that contains exception signal bits, exception summary bits, exception enable bits, rounding control bits needed compliance with IEEE standard. 5.1.5. Machine State Register (MSR) machine state register (MSR) supervisor-level register that defines state processor. contents this register saved when exception taken restored when exception handling completes. 603r implements 32-bit register, 64-bit PowerPC processors implement 64-bit MSR. 5.1.6. Segment Registers (SRs) memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers (SRs). speed access, 603r implements segment registers arrays main array (for data memory accesses) shadow array (for instruction memory accesses). Loading segment entry with Move Segment Register (stsr) instruction loads both arrays. 5.1.7. Special-Purpose Registers (SPRs) powerPC operating environment architecture defines numerous special-purpose registers that serve variety functions, such providing controls, indicating status, configuring processor, performing special operations. During normal execution, program access registers, shown Figure depending program's access privilege (supervisor user, determined privilege-level (PR) MSR). Note that register such GPRs FPRs accessed through operands that part instructions. Access registers explicit (that through specific instructions that purpose such Move Special-Purpose Register (mtspr) Move from Special-Purpose Register (mfspr) instructions) implicit, part execution instruction. Some registers accessed both explicitly implicitly. 603r, SPRs bits wide.
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User-Level SPRs following 603r SPRs accessible user-level software Link register (LR) link register used provide branch target address hold return address after branch link instructions. bits wide 32-bit implementations. Count register (CTR) decremented tested automatically result branch-and-count instructions. bits wide 32-bit implementations. Integer exception register (XER) 32-bit contains summary overflow bit, integer carry bit, overflow bit, field specifying number bytes transferred Load String Word Indexed (lswx) Store String Word Indexed (stswx) instruction. Supervisor-Level SPRs 603r also contains SPRs that accessed only supervisor-level software. These registers consist following 32-bit DSISR defines cause data access alignment exceptions. data address register (DAR) 32-bit register that holds address access after alignment exception. Decrementer register (DEC) 32-bit decrementing counter that provides mechanism causing decrementer exception after programmable delay. 32-bit SDR1 specifies page table format used virtual-to-physical address translation pages. (Note that physical address referred real address architecture specification). machine status save/restore register (SRR0) 32-bit register that used 603r saving address instruction that caused exception, address return when Return from Interrupt (rfi) instruction executed. machine status save/restore register (SRR1) 32-bit register used save machine status exceptions restore machine status when instruction executed. 32-bit SPRG0-SPRG3 registers provided operating system use. external access register (EAR) 32-bit register that controls access external control facility through External Control Word Indexed (eciwx) External Control Word Indexed (ecowx) instructions. time base register (TB) 64-bit register that maintains time operates interval timers. consists 32-bit fields time base upper (TBU) time base lower (TBL). processor version register (PVR) 32-bit, read-only register that identifies version (model) revision level PowerPC processor. Block address translation (BAT) arrays PowerPC architecture defines registers, divided into four pairs data BATs (DBATs) four pairs instruction BATs (IBATs). Figure list numbers arrays.
following supervisor-level SPRs implementation-specific 603r DMISS IMISS registers read-only registers that loaded automatically upon instruction data miss. HASH1 HASH2 registers contain physical addresses primary secondary page table entry groups (PTEGs). ICMP DCMP registers contain duplicate first word page table entry (PTE) which table search looking. required physical address (RPA) register loaded processor with second word correct during page table search. hardware implementation (HID0 HID1) registers provide means enabling 603r"s checkstops features, allows software read configuration configuration signals. instruction address breakpoint register (IABR) loaded with instruction address that compared instruction addresses dispatch queue. When address match occurs, instruction address breakpoint exception generated. Figure shows 603r registers available user supervisor level. number right SPRs indicate number that used syntax instruction operands access register.
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These registers 603r-specific registers. They supported other PowerPC processors.
Figure PowerPC microprocessor programming model Register
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5.2. Instruction addressing modes following subsections describe PowerPC instruction addressing modes general. 5.2.1. PowerPC instruction addressing modes PowerPC instructions encoded single-word (32-bit) opcodes. Instruction formats consistent among instruction types, permitting efficient decoding occur parallel with operand accesses. This fixed instruction length consistent format greatly simplifies instruction pipelining.
PowerPC instruction
PowerPC instructions divided into following categories Integer instructions These include computational logical instructions. Integer arithmetic instructions. Integer compare instructions. Integer logical instructions. Integer rotate shift instructions. Floating-point instructions -These include floating-point computational instructions, well instructions that affect FPSCR. Floating-point arithmetic instructions. Floating-point multiply/add instructions. Floating-point rounding conversion instructions. Floating-point compare instructions. Floating-point status control instructions. Load/store instructions These include integer floating-point load store instructions. Integer load store instruction. Integer load store multiple instructions. Floating-point load store. Primitives used construct atomic memory operations (lwarx stwcx. instructions). Flow control instructions These include branching instructions, condition register logical instructions, trap instructions, other instructions that affect instruction flow. Branch trap instructions. Condition register logical instructions. Processor control instructions These instructions used synchronizing memory accesses management caches, TLBs, segment registers. Move to/from instructions. Move to/from MSR. Synchronize. Instruction synchronize. Memory control instruction These instructions provide control caches, TLBs, segment registers. Supervisor-level cache management instructions. User-level cache instructions. Segment register manipulation instructions. Translation lookaside buffer management instructions. Note that this grouping instructions does indicate which execution unit executes particular instruction group instructions. Integer instructions operate byte, half-word, word operands. Floating-point instructions operate single-precision (one word) double-precision (one double word) floating-point operands. PowerPC architecture uses instructions that four bytes long word-aligned. provides byte, half-word, word operand loads stores between memory GPRs. also provides word double-word operand loads stores between memory floating-point registers (FPRs). Computational instructions modify memory. memory operand computation then modify same another memory location, memory contents must loaded into register, modified, then written back target location with distinct instructions. PowerPC processors follow program flow when they normal execution state. However, flow instructions interrupted directly execution instruction asynchronous event. Either kind exception cause several components system software invoked.
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Calculating effective addresses effective address (EA) 32-bit address computed processor when executing memory access branch instruction when fetching next sequential instruction. PowerPC architecture supports simple memory addressing modes (RA|0) offset (including offset (register indirect with immediate index). (RA|0) (register indirect with index). These simple addressing modes allow efficient address generation memory accesses. Calculation effective address aligned transfers occurs single clock cycle. memory access instruction, effective address operand length exceeds maximum effective address, memory operand considered wrap around from maximum effective address effective address Effective address computations both data instruction accesses 32-bit unsigned binary arithmetic. carry from ignored 32-bit implementations.
5.2.2. PowerPC 603r microprocessor instruction 603r instruction defined follows 603r provides hardware support 32-bit PowerPC instructions. 603r provides implementation-specific instructions used software table search operations following misses Load Data Entry (tlbld). Load Instruction Entry (tlbli). 603r implements following instructions which defined optional PowerPC architecture External Control Word Indexed (eciwx). External Control Word Indexed (ecowx). Floating Select (fsed). Floating Reciprocal Estimate Single-Precision (fres). Floating Reciprocal Square Root Estimate (frsqrte). Store Floating-Point Integer Word (stfiwx). 5.3. Cache implementation following subsections describe PowerPC architecture's treatment cache general, 603r specific implementation, respectively. 5.3.1. PowerPC cache characteristics PowerPC architecture does define hardware aspects cache implementations. example, some PowerPC processors, including 603r, have separate instruction data caches (hardware architecture), while others, such PowerPC 601microprocessor, implement unified cache. PowerPC microprocessor control following memory access modes page block basis Write-back/write-through mode. Cache-inhibited mode. Memory coherency. Note that 603r, cache line defined eight words. defines cache management instructions that provide means which application programmer affect cache contents. 5.3.2. PowerPC 603r microprocessor cache implementation 603r 16-Kbyte, four-way set-associative (instruction data) caches. caches physically addressed, data cache operate either write-back write-through mode specified PowerPC architecture. data cache configured sets lines each. Each line consists bytes, state bits, address tag. state bits implement three-state (modified/exclusive/invalid) protocol. Each line contains eight 32-bit words. Note that PowerPC architecture defines term block cacheable unit. 603r, block size equivalent cache line. block diagram data cache organization shown Figure instruction cache also consists sets lines, each line consists bytes, address tag, valid bit. instruction cache written except through line fill operation. instruction cache snooped, cache coherency must maintained software. fast hardware invalidation capability provided support cache maintenance. organization instruction cache very similar data cache shown Figure Each cache line contains eight contiguous words from memory that loaded from 8-word boundary (that bits A27-A32 effective addresses zero) thus, cache line never crosses page boundary. Misaligned accesses across page boundary incur performance penalty.
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603's cache lines loaded four beats bits each. burst load performed "critical double word first". cache that being loaded blocked internal accesses until load completes. critical double word simultaneously written cache forwarded requesting unit, thus minimizing stalls load delays. ensure coherency among caches multiprocessor multiple caching-device) implementation, 603r implements protocol. These three states, modified, exclusive, invalid, indicate state cache block follows Modified cache line modified with respect system memory that data this address valid only cache system memory. Exclusive This cache line holds valid data that identical data this address system memory. other cache this data. Invalid This cache line does hold valid data. Cache coherency enforced on-chip snooping logic. Since 603r's data cache tags single ported, simultaneous load store snoop access represent resource contention. snoop access given first access tags. load store then occurs clock following snoop.
Figure Data cache organization
5.4. Exception model following subsections describe PowerPC exception model 603r implementation, respectively. 5.4.1. PowerPC exception model PowerPC exception mechanism allows processor change supervisor state result external singles, errors, unusual conditions arising execution instructions, differ from arithmetic exceptions defined IEEE floatingpoint operations. When exceptions occur, information about state processor saved certain registers processor begins execution address (exception vector) predetermined each exception. Processing exceptions occurs supervisor mode. Although multiple exception conditions single exception vector, more specific condition determined examining register associated with exception example, DSISR FPSCR. Additionally, some exception conditions explicitly enable disabled software. PowerPC architecture requires that exceptions handled program order therefore, although particular implementation recognize exception conditions order, they presented strictly order. When instruction-caused exception recognized, unexecuted instructions that appear earlier instruction stream, including that have entered execute state, required complete before exception taken. exceptions caused those instructions handled first. Likewise, exceptions that asynchronous precise recognized when they occur, handled until instruction currently completion state successfully completes execution generates exception, completed store queue emptied. Unless catastrophic causes system reset machine check exception, only exception handled time. example, single instruction encounters multiple exception conditions, those conditions encountered sequentially. After exception handler handles exception, instruction execution continues until next exception condition encountered. However, many cases there attempt re-execute instruction. This method recognizing handling exception conditions sequentially guarantees that exceptions recoverable. Exception handlers should save information stored SRR0 SRR1 early prevent program state from being lost system reset machine check exception instruction-caused exception exception handler, before enabling external interrupts.
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PowerPC architecture support four types exceptions Synchronous, precise These causes instructions. instruction-caused exceptions handled precisely that machine state time exception occurs known completely restored. This means that (excluding trap system call exceptions) address faulting instruction provided exception handler that neither faulting instruction subsequent instructions code stream will complete execution before exception taken. Once exception processed, execution resumes address faulting instruction alternate address provided exception handler). When exception taken trap system call instruction, execution resumes address provided handler. Synchronous, imprecise PowerPC architecture defines imprecise floating-point exception modes, recoverable nonrecoverable. Even though 603r provides means enable imprecise modes, implements these modes identically precise mode (-hat enabled floating-point enabled exceptions always precise 603r). Asynchronous, maskable external, SMI, decrementer interrupts maskable asynchronous exceptions. When these exceptions occur, their handling postponed until next instruction, exceptions associated with that instruction, completes execution. there instructions execution units, exception taken immediately upon determination correct restart address (for loading SRR0). Asynchronous, maskable There maskable asynchronous exceptions: system reset machine check exception. These exceptions recoverable, provide limited degree recoverability. exceptions report recoverability through SMR[RI] bit. 5.4.2. PowerPC 603r microprocessor exception model specified PowerPC architecture, 603r exceptions described either precise imprecise either synchronous asynchronous. Asynchronous exceptions (some which maskable) caused events external processor's execution synchronous exceptions, which handled precisely 603r, caused instructions. 603r exception classes shown Table Synchronous/Asynchronous Asynchronous, maskable Asynchronous, maskable precise/Imprecise Imprecise Precise Exception type Machine check System reset External interrupt Decrementer System management interrupt Instruction-caused exceptions
Synchronous
Precise
Table 13.PowerPC 603r microprocessor exception classifications
Although exceptions have other characteristics well, such whether they maskable maskable, distinctions shown Table define categories exceptions that 603r handles uniquely. Note that Table includes synchronous imprecise instructions. While PowerPC architecture supports imprecise handling floating-point exceptions, 603r implements these exception modes precise exceptions. 603r's exceptions, conditions that cause them, listed Table Exceptions that specific 603r indicated.
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Table 14.Exceptions conditions
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5.5. Memory management following subsections describe memory management features PowerPC architecture, 603r implementation, respectively. 5.5.1. PowerPC memory management primary functions translate logical (effective) addresses physical addresses memory accesses, provide access protection blocks pages memory. There types accesses generated 603r that require address translation instruction accesses, data accesses memory generated load store instructions. PowerPC exception model support demand-paged virtual memory. Virtual memory management permits execution programs larger than size physical memory demand-paged implies that individual pages loaded into physical memory from system memory only when they first accessed executing program. hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. page table contains number page table entry groups (PTEGs). PTEG contains eight page table entries (PTEs) eight bytes each therefore, each PTEG bytes long. PTEG addresses entry points table search operations. Address translations enabled setting bits MSR-MSR[IR] enables instruction address translations MSR[DR] enables data address translations. 5.5.2. PowerPC 603r microprocessor memory management instruction data memory management units 603r provide Gbyte logical address space accessible supervisor user programs with 4-Kbyte page size 256-Mbyte segment size. Block sizes range from Kbyte 256Mbyte software selectable. addition, 603r uses interim 52-bit virtual address hashed page tables generating 32-bit physical addresses. MMUs 603r rely exception processing mechanism implementation paged virtual memory environment enforcing protection designated memory areas. Instruction data TLBs provide address translation parallel with on-chip cache access, incurring additional time penalty event hit. cache most recently used page table entries. Software responsible maintaining consistency with memory. 603r's TLBs 64-entry, two-way set-associative caches that contain instruction data address translations. 603r provides hardware assist software table search operations through ashed page table misses. Supervisor software invalidate entries selectively. 603r also provides independent four-entry arrays instructions data that maintain address translations blocks memory. These entries define blocks that vary from Kbyte Mbyte. arrays maintained system software. specified PowerPC architecture, hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. Also specified PowerPC architecture, page table contains number page table entry groups (PTEGs). PTEG contains eight page table entries (PTEs) eight bytes each therefore, each PTEG bytes long. PTEG addresses entry points table search operations. 5.6. Instruction timing 603r pipelined superscalar processor. pipelined processor which processing instruction reduced into discrete stages. Because processing instruction broken into series stages, instruction does require entire resources execution unit. example, after instruction completes decode stage, pass next stage, while subsequent instruction advance into decode stage. This improves throughput instruction flow.
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example, take three cycles floating-point instruction complete, there stalls floating-point pipeline, series floating-point instructions have throughput instruction cycle. instruction pipeline 603r four major pipeline stages, described follows fetch pipeline stage primarily involves retrieving instructions from memory system determining location next instruction fetch. Additionally, decodes branches during fetch stage folds branch instructions before dispatch stage possible. dispatch pipeline stage responsible decoding instructions supplied instruction fetch stage, determining which instructions eligible dispatched current cycle. addition, source operands instructions read from appropriate register file dispatched with instruction execute pipeline stage. dispatch pipeline stage, dispatched instructions their operands latched appropriate execution unit. During execute pipeline stage each execution unit that executable instruction executes selected instruction (perhaps over multiple cycles), writes instruction's result into appropriate rename register, notifies completion stage that instruction finished execution. case internal exception, execution unit reports exception completion/writeback pipeline stage discontinues instruction execution until exception handled. exception signaled until that instruction next completed. Execution most floating-point instructions pipelined within allowing three instructions executing concurrently. pipeline stages floating-point unit multiply, add, round-convert. Execution most load/store instructions also pipelined. load/store units pipeline stages. first stage effective address calculation translation second stage accessing data cache. complete/writeback pipeline stage maintains correct architectural machine state transfers contents rename registers GPRs FPRs instructions retired. completion logic detects instruction causing exception, following instructions cancelled, their execution results rename registers discarded, instructions fetched from correct instruction stream. superscalar processor that issues multiple independent instructions into multiple pipelines allowing instructions execute parallel. 603r five independent execution units, each integer instructions, floating-point instructions, branch instructions, load/store instructions, system register instructions. each have dedicated register files maintaining operands (GPRs FPRs, respectively), allowing integer calculations floating-point calculations occur simultaneously without interference. Because PowerPC architecture applied such wide variety implementations, instruction timing among various PowerPC processors varies accordingly.
PREPARATION DELIVERY
6.1. Packaging Microcircuits prepared delivery accordance with MIL-PRF-38535. 6.2. Certificate compliance offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 guarantying parameters tested temperature extremes entire temperature range.
HANDLING
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical.
PACKAGE MECHANICAL DATA
8.1. Mechanical dimensions wire-bond CERQUAD package
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Wire Bonds
Ceramic Body Alloy Leads
Notes Dimensioning tolerancing ASME Y14.5M-1994 Controlling dimension millimeter. Datum plane located bottom lead coincident with lead where lead exits ceramic body bottom parting line. Datum determined datum plane Dimension determined seating plane Dimension define maximum ceramic body dimensions including glass protrusion bottom mismatch. MILLIMETERS 30.86 31.00 30.86 31.00 3.67 3.95 0.185 0.220 3.10 3.50 0.175 0.200 0.50 2.025 2.100 0.130 0.147 0.45 0.50 0.25 34.41 34.58 17.20 17.30 34.41 34.58 0.25 0.50 17.20 17.30 0.122 0.127 1.80 0.95
31.75 31.75 4.15 0.270 3.90 0.225 2.175 0.175 0.55 34.75 17.40 34.75 0.75 17.40 0.132
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8.2. Mechanical dimensions wire-bond MQUAD package
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CLOCK RELATIONSHIPS CHOICE
603r microprocessors offer customers numerous clocking options. internal phase-lock loop synchronizes processor (CPU) clock system clock (SYSCLK) various ratios. Inside each PowerPC microprocessor phase-lock loop circuit. voltage controlled oscillator (VCO) precisely controlled frequency phase frequency/phase detector which compares input frequency (SYSCLK frequency) submultiple VCO. ratio SYSCLK frequencies often referred mode (for example, mode). Table horizontal scale represents frequency (SYSCLK) vertical scale represents PLL-CFG[0-3] signals. given SYSCLK (bus) frequency, configuration signals internal frequency operation.
Table 15.CPU frequencies common frequencies multipliers
PLL_CFG[0-3] Bus-to- Core Multiplier 0100 0101 0110 1000 1110 1010 0111 1011 1001 1101 0011 1111
Notes Some configurations select bus, frequencies which supported PLL-bypass mode, SYSCLK input signal clocks internal processor directly, disabled, mode mode operation. This mode intended factory only. Note timing specifications given this document apply PLL-bypass mode. clock-off mode, clocking occurs inside 603r regardless SYSCLK input.
Frequency (VCO Frequency MHz) Core-to Multiplier (300) 33.33 (300) (333) (366) (400) (320) (360) (400) bypass Clock (300) (350) (400) (300) (360) 66.67 (333) (400)
2.5x 3.5x 4.5x 5.5x
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SYSTEM DESIGN INFORMATION
10.1. Power Supply Filtering AVdd power signal provided 603e provide power clock generation phase-locked loop. ensure stability internal clock, power supplied AVdd input signal should filtered using circuit similar shown Figure circuit should placed close AVdd ensure filters much noise possible. capacitor should closest AVdd pin, followed capacitor, finally resistor Vdd. These traces should kept short direct.
AVdd
Figure Power Supply Filter Circuit 10.2. Decoupling Recommendations 603e's dynamic power management feature, large address data buses, high operating frequencies, 603e generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components 603e system, 603e itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVdd 603e. also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, power planes PCB, utilizing short traces minimize inductance. These capacitors should vary value from provide both high-and low-frequency filtering, should placed close possible their associated OVdd pin. Suggested values pins (ceramic), 0,01 (ceramic) (ceramic). Suggested values OVdd pins 0,01 (ceramic), (ceramic), (tantalum). Only (surface mount technology) capacitors should used minimize lead inductance. addition, recommended that there several bulk storage capacitors distributed around PCB, feeding OVdd planes, enable quick recharging smaller chip capacitors. These bulk capacitors should also have (equivalent series resistance) rating ensure quick response time necessary. They should also connected power ground planes through vias minimize inductance. Suggested bulk capacitors (AVX tantalum) (AVX tantalum). 10.3. Connection Recommendations ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied Vdd. Unused active high inputs should connected GND. (no-connect) signals must remain unconnected. Power ground connections must made external Vdd, OVdd, pins 603e. 10.4. Pull-up Resistor Requirements 603e requires high-resistive (weak pull-up resistors several control signals interface maintain control signals negated state after they have been actively negated released 603e other master. These signals -TS, ABB, DBB, ARTRY. addition, 603e three open-drain style outputs that require pull-up resistors (weak stronger KW-10 they used system. These signals APE, DPE, CKSTP_OUT. During inactive periods bus, address transfer attributes driven master float high-impedance state relatively long periods time. Since 603e must continually monitor these signals snooping, this float condition cause excessive power draw input revivers 603e. recommended that these signals pulled trough weak pull-up resistors restored some manner system. snooped address transfer attribute inputs A0-3], AP[0-3], TT[0-4], TBST, GBL. data input receivers normally turned when read operation progress require pull-up resistors data bus.
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DEFINITIONS Datasheet status Objective specification This datasheet contains target goal specification discussion with customer application validation. This datasheet contains target goal specification product development. This datasheet contains preliminary data. Additional data published later could include simulation result. This datasheet contains also characterization results. This datasheet contains final product specification. Limiting values Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. customers using selling these products such applications their risk agree fully indemnify damages resulting from such improper sale. Validity Before design phase.
Target specification Preliminary specification site
Valid during design phase. Valid before characterization phase. Valid before industrialization phase. Valid production purpose.
Preliminary specification site Product specification
DIFFERENCES WITH COMMERCIAL PART
Commercial part Package Temperature range Power consumption TBGA 105C
Military part CERQUAD MQUAD -55C +125C 1.25 factor calculate temperature (-55C)
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ORDERING INFORMATION PC603R Revision level Type (TSXPC603R prototype) Temperature range -55, +125 -40, +110 +70°C Package CERQUAD MQUAD divider confirmed)
internal processor speed :166 (TBD) (TBD)
Screening level Standard MIL-STD-883, class (TBC) according MIL-STD-883
availability different versions, contact your ATMEL sale office
Information furnished believed accurate reliable. However Atmel-Grenoble assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Atmel-Grenoble. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. AtmelGrenoble products authorized critical components life support devices systems without express written approval from Atmel-Grenoble.
2000 Atmel-Grenoble- Printed France rights reserved.
This product manufactured Atmel-Grenoble- 38521 SAINT-EGREVE FRANCE. further information please contact Atmel-Grenoble Route B.P. 91401 ORSAY Cedex FRANCE Phone (0)1 (0)1
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PID7t-603e implementation PowerPC603e (after named 603r) low-power imp

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