Download

PDF Abstract Text:

TSPC603R

PowerPC 603e RISC MICROPROCESSOR Family PID7t-603e Specification

TSPC603R
PowerPC 603e RISC MICROPROCESSOR Family PID7t-603e Specification
DESCRIPTION
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC family. The 603r implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603r is a low-power 2.5 / 3.3-volt design and provides four software controllable power-saving modes. The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance however, the 603r makes completion appear sequential. The 603r integrates five execution units and is able to execute five instructions in parallel. The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way setassociative, data and instruction translation lookaside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to complete for system resources through a central external arbiter. The 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I / O. The 603r uses an advanced, 2.5 / 3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. The 603r integrates in system testability and debugging features through JTAG boundary-scan capability.
G suffix CBGA 255 Ceramic Ball Grid Array
GS suffix CI-CGA 255 Ceramic Ball Grid Array with Solder Column Interposer (SCI)
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with:
H CI-CGA 255 : MIL-STD-883 class Q or According to TCS H H H H
January 1999
TSPC603R SUMMARY
Condition Register (CR) . . . . . . . . . . . . 22 Floating-Point Status and Control Register (FPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Machine State Register (MSR) . . . . . . 22 Segment Registers (SRs) . . . . . . . . . . . 22 Special-Purpose Registers (SPRs) . . . 22
5.2. Instruction set and addressing modes . . . . 25
5.2.1. 5.2.2. PowerPC instruction set and addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerPC 603r microprocessor instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
B. DETAILED SPECIFICATIONS . . . . . . . . . . 10
3.2.1. 3.2.2. Terminal connections . . . . . . . . . . . . . . . 10 Lead material and finish . . . . . . . . . . . . 10
5.3.1. 5.3.2. PowerPC cache characteristics . . . . . . 26 PowerPC 603r microprocessor cache implementation . . . . . . . . . . . . . . . . . . . . 26
5.4.1. 5.4.2. PowerPC exception model . . . . . . . . . . 27 PowerPC 603r microprocessor exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.1. 5.5.2. PowerPC memory management . . . . . 31 PowerPC 603r microprocessor memory management . . . . . . . . . . . . . . . . . . . . . . 31
3.3. Absolute maximum ratings . . . . . . . . . . . . . . 10 3.4. Recommended operating conditions . . . . . . 11 3.5. Thermal characteristics . . . . . . . . . . . . . . . . . 11 3.6. Power consideration . . . . . . . . . . . . . . . . . . . 12
3.6.1. 3.6.2. 3.6.3. 3.6.4. 3.6.5. Dynamic Power Management . . . . . . . Programmable Power Modes . . . . . . . . Power Management Modes . . . . . . . . . Power Management Software Considerations . . . . . . . . . . . . . . . . . . . . Power dissipation . . . . . . . . . . . . . . . . . . 12 12 12 14 14
4.3.1. 4.3.2. 4.3.3. Clock AC specifications . . . . . . . . . . . . . 16 Input AC specifications . . . . . . . . . . . . . 17 Output AC specifications . . . . . . . . . . . . 18
8.2. Mechanical dimensions of the CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3. CI-CGA package parameters . . . . . . . . . . . 34 8.4. Mechanical dimensions of the CI-CGA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . 35 10. SYSTEM DESIGN INFORMATION . . . . . . . . . . . 36 10.1 PLL Power Supply Filtering . . . . . . . . . . . . . 36 10.2 Decoupling Recommendations . . . . . . . . . . 36 10.3 Connection Recommendations . . . . . . . . . . 36 10.4 Pull-up Resistor Requirements . . . . . . . . . 37 11. ORDERING INFORMATION . . . . . . . . . . . . . . . . 38
4.4. JTAG AC timing specifications . . . . . . . . . . . 20 5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 22 5.1. PowerPC registers and programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1. 5.1.2. General-Purpose Registers (GPRs) . . 22 Floating-Point Registers (FPRs) . . . . . 22
TSPC603R
A. GENERAL DESCRIPTION
Fetch Unit Completion Unit Dispatch Unit Branch Unit
Integer Unit
Gen Reg Unit
Gen Rename
Load / Store Unit
FP Rename
FP Reg File
Float Unit
D MMU 16K Data Cache
I MMU 16K Inst. Cache
Bus Interface Unit 32b address 64b data
System Bus
Figure 1 : Block diagram
1. INTRODUCTION
TSPC603R 2. PIN ASSIGNMENTS 2.1. CBGA 255 and CI-CGA 255 packages
Figure 2 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA packages. The direction of the top surface view is shown by the side profile of the packages.
Substrate Assembly
CBGA 255
Encapsulant
CI-CGA 255
Not to scale
Figure 2 : CBGA 255 and CI-CGA 255 Top view
TSPC603R 2.2. Pinout listing
Table 1 : Power and ground pins
VDD2 PLL (AVDD) Internal logic Output drivers A10 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12 J05 J07 J10 J12 K06 K08 K09 K11 L05 H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 GND
Table 2 : Signal pinout listing
Signal name A0-31 CBGA Pin number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04 J04 L01 B06 E01 D08 A06 D07 B01, B05 J14 N01 H15 G04 Active High I / O I / O
Low Low High Low Low Low Low Low Low Low High Low Low Low Low
Input I / O I / O Output I / O Input Output Output Input Output Output Output I / O Input Input Input I / O I / O
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09, High T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 F01 A07 B15 D11 High
High Low Low Low Low Low -
I / O Output Input I / O Input Input Input
TSPC603R
Notes : 1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 2. OVDD inputs supply power to the I / O drivers and VDD inputs supply power to the processor core. 3. NC (no-connect) in the 603e BGA package internally tied to GND in the 603r BGA package to indicate to the power supply that a low-voltage processor is present.
D12 B10 C13 A08, B09, A09, D09 D03 J03 D01 A16 B14 C09 H14 C02 A14 A02, A03 C11 A11 A12 H13 C04 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 B07, B08, C03, C06, C08, D05, D06, F03, H04, J16 F03
Low Low High Low Low Low Low Low Low High Low High High High Low Low High Low Low High High Low Low Low
Input Input Input Input Input Output Output Input Input Input Input Input I / O Output Input Input Output Input Input Input Input I / O I / O I / O Output Input Output
TSPC603R 3. SIGNAL DESCRIPTION
ADDRESS START
PROCESSOR STATUS
JTAG / COP INTERFACE LSSD TEST CONTROL
POWER SUPPLY
Figure 3 : Functional signal groups
Table 3 : Address and data bus signal index
Signal name Address bus Data bus Data bus Mnemonic A0-31 DH0-31 DL0-31 Signal function if output, physical address of data to be transferred. if input, represents the physical address of a snoop operation. Represents the state of data, during a data write operation if output, or during a data read operation if input. Represents the state of data, during a data write operation if output, or during a data read operation if input. Signal type I / O I / O I / O
TSPC603R
Table 4 : Signal index
Signal name Address Acknowledge Address Bus Busy Address Bus Parity Mnemonic AACK ABB AP0-3 Signal function The address phase of a transaction is complete If output, the 603r is the address bus master If input, the address bus is in use If output, represents odd parity for each of 4 bytes of the physical address for a transaction If input, represents odd parity for each of 4 bytes of the physical address for snooping operations Incorrect address bus parity detected on a snoop Signal type Input I / O I / O
Address Parity Error Address retry
APE ARTRY
Output
If output, detects a condition in which a snooped address tenure must be I / O retried If input, must retry the preceding address tenure May, with the proper qualification, assume mastership of the address bus Request mastership of the address bus A single-beat transfer will not be cached Provides PLL clock output for PLL testing and monitoring Must terminate operation by internally gating off all clocks, and release all outputs Has detected a checkstop condition and has ceased operation Cache replacement set element for the current transaction reloading into or writing out of the cache If output, the 603r is the data bus master If input, another device is bus master (For a write transaction) must release data bus and the data bus parity to high impedance during the following cycle May, with the proper qualification, assume mastership of the data bus May run the data bus tenure If output, odd parity for each of 8 bytes of data write transactions If input, odd parity for each byte of read data Incorrect data bus parity Must invalidate the data from the previous read operation If output, a transaction is global If input, a transaction must be snooped by the 603r Initiates a complete hard reset operation Initiates an interrupt if bit EE of MSR register is set LSSD test control signal for factory use only LSSD test control signal for factory use only LSSD test control signal for factory use only Initiates a machine check interrupt operation if the bit ME of MSR register and bit EMCP of HID0 register are set Configures the operation of the PLL and the internal processor clock frequency Input Output Output Output Input Output Output I / O Input Input Input I / O Output Input I / O Input Input Input Input Input Input Input
Bus grant Bus request Cache Inhibit Test Clock Checkstop Input Checkstop Output Cache Set Entry Data Bus Busy Data Bus Disable Data Bus Grant Data Bus Write Only Data Bus Parity Data Parity Error Data Retry Global Hard Reset Interrupt
Machine Check Interrupt PLL Configuration
TSPC603R
Signal name Mnemonic Signal function Signal type Input Output Output Input Input Input Input Input I / O Output Input Input Output Input Input Input Input I / O I / O
Quiescent Acknowledge Quiescent Request Reservation System Management Interrupt Soft Reset System Clock Transfer Acknowledge Timebase Enable Transfer Burst Transfer Code Test clock Test data input Test data output Transfer Error Acknowledge TLBI Sync Test mode select Test reset Transfer Size Transfer start
QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC0-1 TCK TDI TDO TEA TLBISYNC TMS TRST TSIZ0-2 TS
All bus activity has terminated and the 603r may enter a quiescent (or low power) state Is requesting all bus activity normally to enter a quiescent (low power) state Represents the state of the reservation coherency bit in the reservation address register Initiates a system management interrupt operation if the bit EE of MSR register is set Initiates processing for a reset exception Represents the primary clock input for the 603r, and the bus clock frequency for 603r bus operation A single-beat data transfer completed successfully or a data beat in a burst transfer completed successfully The timebase should continue clocking If output, a burst transfer is in progress If input, when snooping for single-beat reads Special encoding for the transfer in progress Clock signal for the IEEE P1149.1 test access port (TAP) Serial data input for the TAP Serial data output for the TAP A bus error occurred Instruction execution should stop after execution of a tlbsync instruction Selects the principal operations of the test-support circuitry Provides an asynchronous reset of the TAP controller For memory accesses, these signals along with TBST indicate the data transfer size for the current bus operation If output, begun a memory bus transaction and the address bus and transfer attribute signals are valid If input, another master has begun a bus transaction and the address bus and transfer attribute signals are valid for snooping (see GBL) Type of transfer in progress A single-beat transaction is write-through Available only on BGA package Indicates to the power supply that a low-voltage processor is present.
Transfer Type Write-Through
TT0-4 WT
I / O Output Output
Power supply indicator VOLTDETGND
TSPC603R
B. DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the microprocessor TSPC603r, in compliance with MIL-STD-883 class B or TCS standard screening.
2. APPLICABLE DOCUMENTS
1) MIL-STD-883 : Test methods and procedures for electronics. 2) MIL-PRF-38535 : General specifications for microcircuits.
3. REQUIREMENTS 3.1. General
The microcircuits are in accordance with the applicable documents and as specified herein.
3.2. Design and construction
3.3. Absolute maximum ratings
Absolute maximum ratings are stress rating only and functional operation at the maximum is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device
Table 5 : Absolute maximum rating for the 603r
Parameter Core supply voltage PLL supply voltage I / O supply voltage Input voltage Storage temperature range
Notes:
Symbol Vdd AVdd OVdd Vin Tstg
Min -0.3 -0.3 -0.3 -0.3 -55
Max 2.75 2.75 3.6 5.5 +150
1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. 2. Caution : Input voltage must not be greater than OVdd by more than 2.5 V at any times, including during power-on reset. 3. Caution : OVdd voltage must not be greater than Vdd / AVdd by more than 1.2 V at any times, including during power-on reset. 4. Caution : Vdd / AVdd voltage must not be greater than OVdd by more than 0.4 V at any times, including during power-on reset.
TSPC603R 3.4. Recommanded Operating Conditions
These are the recommanded and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Parameter Core supply voltage PLL supply voltage I / O supply voltage Input voltage Operating temperature 3.5. Thermal characteristics
Symbol Vdd AVdd OVdd Vin Tc
Min 2.375 2.375 3.135 GND -55
Max 2.625 2.625 3.465 5.5 +125
Assuming an air velocity of 1.0 m / sec, the associated overall thermal resistance and junction temperature, found in Table 6 will result.
TSPC603R
Table 6 : Thermal resistance and junction temperature
Configuration With 2328B heat sink
(°C / W) 5.0
Tj (°C) 106
Vendors such as Aavid Engineering Inc., Thermalloy, and Wakefield Engineering can supply heat sinks with a wide range of thermal performance.
3.6. Power consideration
The PowerPC603r is a microprocessor specifically designed for low-power operation. As the 603e microprocessor version, the 603r provides both automatic and program-controllable power reduction modes for progressive reduction of power consumption. This chapter describes the hardware support provided by the 603r for power management. 3.6.1.Dynamic Power Management Dynamic power management automatically powers up and down the individual execution units of the 603r, based upon the contents of the instruction stream. For example, if no floating-point instructions are being executed, the floating-point unit is automatically powered down. Power is not actually removed from the execution unit instead, each execution unit has an independent clock input, which is automatically controlled on a clock-by- clock basis. Since CMOS circuits consume negligible power when they are not switching, stopping the clock to an execution unit effectively eliminates its power consumption. The operation of DPM is completely transparent to software or any external hardware. Dynamic power management is enabled by setting bit 11 in HID0 on power-up, of following HRESET. 3.6.2.Programmable Power Modes The 603r provides four programmable power states - full power, doze, nap and sleep. Software selects these modes by setting one (and only one) of the three power saving mode bits. Hardware can enable a power management state through external asynchronous interrupts The hardware interrupt causes the transfer of program flow to interrupt handler code. The appropriate mode is then set by the software. The 603r provides a separate interrupt and interrupt vector for power management - the system management interrupt (SMI). The 603r also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of time and then return to full power operation through the decrementer interrupt (DI). Note that the 603r cannot switch from on power management mode to another without first returning to full on mode. The nap and sleep modes disable bus snooping therefore, a hardware handshake is provided to ensure coherency before the 603r enters these power management modes. Table 7 summarizes the four power states.
Table 7 : Power PC 603r Microprocessor Programmable Power Modes
PM Mode
Full power Full power (with DPM) Doze
Functioning Units
All units active Requested logic by demand - Bus snooping - Data cache as needed - Decrementer timer -
Activation Method
Full-Power Wake Up Method
By instruction dispatch Controlled by SW
External asynchronous exceptions Decrementer interrupt Reset
Decrementer timer
Controlled by hardware and External asynchronous exceptions software Decrementer interrupt Reset
Sleep
Controlled by hardware and External asynchronous exceptions software Reset
Exceptions are referred to as interrupts in the architecture specification
3.6.3.1. Full-Power Mode with DPM Disabled Full-power mode with DPM disabled power mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
TSPC603R
- Default state following power-up and HRESET. - All functional units are operating at full processor speed at all times.
TSPC603R
D Several methods of returning to full-power mode : - Assert INT, SMI, or MCP interrupts. - Assert hard reset or soft reset. D PLL may be disabled and SYSCLK may be removed while in sleep mode. D Return to full-power mode after PLL and SYSCLK disabled in sleep mode : - Enable SYSCLK. - Reconfigure PLL into desired processor clock mode. - System logic waits for PLL startup and relock time (100 msec). - System logic asserts one of the sleep recovery signals (for example, INT or SMI). 3.6.4.Power Management Software Considerations Since the 603r is a dual issue processor with out -of-order execution capability, care must be taken in how the power management mode is entered. Furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power management mode is entered. Normally during system configuration time, one of the power management modes would be selected by setting the appropriate HID0 mode bit. Later on, the power management mode is invoked by setting the MSRPOW bit. To provide a clean transition into and out of the power management mode, the stmsrPOW should be preceded by a sync instruction and followed by an isync instruction. 3.6.5.Power dissipation
Table 8 : Power dissipation
Doze Mode Typical Nap Mode Typical 100 120 140 160 180 mW 1.5 1.7 1.8 2.0 2.1 W
Sleep Mode Typical 96 110 123 135 150 mW
Sleep Mode-PLL Disabled Typical 60 60 60 60 60 mW
Sleep Mode-PLL and SYSCLK Disabled Typical Maximum
TSPC603R 3.7. Marking
4. ELECTRICAL CHARACTERISTICS 4.1. General requirements
4.2. Static characteristics
Table 9 : Electrical characteristics
Notes:
TSPC603R 4.3. Dynamic characteristics
4.3.1.Clock AC specifications Table 10 provides the clock AC timing specifications as defined in Figure 5.
Num Characteristics 166 MHz Min Processor frequency VCO frequency SYSCLK (bus) frequency 1 2, 3 4 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle (1.4V measured) SYSCLK jitter 603r internal PLL relock time
Figure 5 : SYSCLK input timing diagram
TSPC603R
4.3.2.Input AC specifications Table 11 provides the input AC timing specifications for the 603r as defined in Figure 6 and Figure 7.
Table 11 : Input AC timing specifications
tsysclk 4, 5, 6, 7 ns ns ns 2 3 4, 6, 7
Notes : 1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Both input and output timings are measured at the pin. See Figure 7. 2. Address / data / transfer attribute input signals are composed of the following: A0-31, AP0-3, TT0-4, TC0-1, TBST, TSIZ0-2, GBL, DH0-31, DL0-31, DP9-7. 3. All other input signals are compsed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 7. 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. These values are guaranteed by design, and are not tested. 7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100 ms) during the power-on reset sequence.
Figure 6 : Input timing diagram
TSPC603R
Figure 7 : Mode select input timing diagram 4.3.3.Output AC specifications Table 12 provides the output AC timing specifications for the 603r (shown in Figure 8).
Num Characteristic 166, 200 MHz Min 12 13a 13b 14a 14b 15 16 17 18 19 SYSCLK to output driven (output enable time) SYSCLK to output valid (5.5 V to 0.8 V - TS, ABB, ARTRY, DBB) SYSCLK to output valid (TS, ABB, ARTRY, DBB) SYSCLK to output valid (5.5 V to 0.8 V - all except TS, ABB, ARTRY, DBB) SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all except ARTRY, ABB, DBB) SYSCLK to ABB, DBB, high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable 1.0 - - - - 1.0 - - - 0.2 tsysclk + 1.0 - - Max - 9.0 8.0 11.0 9.0 - 8.5 1.0 8.0 - 233, 266 MHz Min 1.0 - - - - 1.0 - - - 0.2 tsysclk + 1.0 - - Max - 9.0 8.0 11.0 9.0 - 8.0 1.0 7.5 - 300 MHz Min 1.0 - - - - 1.0 - - - 0.2 tsysclk + 1.0 - - Max - 9.0 8.0 11.0 9.0 - 8.0 1.0 7.5 - ns ns ns ns ns ns ns tsysclk ns ns 3, 5, 8 5, 8 6, 8 5, 7 4 6 4 6 3 Unit Note
Maximum dalay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge
tsysclk tsysclk
TSPC603R
Figure 8 : Output timing diagram
TSPC603R 4.4. JTAG AC timing specifications
Table 13 : JTAG AC timing specifications (independent of SYSCLK)
Figure 9 : Clock input timing diagram
Figure 10 : TRST timing diagram
TSPC603R
Figure 11 : Boundary-scan timing diagram
Figure 12 : Test access port timing diagram
TSPC603R 5. FUNCTIONAL DESCRIPTION 5.1. PowerPC registers and programming model
5.1.7.1. User-Level SPRs The following 603r SPRs are accessible by user-level software : D Link register (LR) - The link register can be used to provide the branch target address and to hold the return address after branch and link instructions. The LR is 32 bits wide in 32-bit implementations. D Count register (CTR) - The CRT is decremented and tested automatically as a result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations. D Integer exception register (XER) - The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
TSPC603R
5.1.7.2. Supervisor-Level SPRs The 603r also contains SPRs that can be accessed only by supervisor-level software. These registers consist of the following : D The 32-bit DSISR defines the cause of data access and alignment exceptions. D The data address register (DAR) is a 32-bit register that holds the address of an access after an alignment or DSI exception. D Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. D The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for pages. (Note that physical address is referred to as real address in the architecture specification). D The machine status save / restore register 0 (SRR0) is a 32-bit register that is used by the 603r for saving the address of the instruction that caused the exception, and the address to return to when a Return from Interrupt (rfi) instruction is executed. D The machine status save / restore register 1 (SRR1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an rfi instruction is executed. D The 32-bit SPRG0-SPRG3 registers are provided for operating system use. D The external access register (EAR) is a 32-bit register that controls access to the external control facility through the External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions. D The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. The TB consists of two 32-bit fields - time base upper (TBU) and time base lower (TBL). D The processor version register (PVR) is a 32-bit, read-only register that identifies the version (model) and revision level of the PowerPC processor. D Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT registers, divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). See Figure 13 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603r : D The DMISS and IMISS registers are read-only registers that are loaded automatically upon an instruction or data TLB miss. D The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary page table entry groups (PTEGs). D The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE) for which the table search is looking. D The required physical address (RPA) register is loaded by the processor with the second word of the correct PTE during a page table search. D The hardware implementation (HID0 and HID1) registers provide the means for enabling the 603r"s checkstops and features, and allows software to read the configuration of the PLL configuration signals. D The instruction address breakpoint register (IABR) is loaded with an instruction address that is compared to instruction addresses in the dispatch queue. When an address match occurs, an instruction address breakpoint exception is generated. Figure 13 shows all the 603r registers available at the user and supervisor level. The number to the right of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.
TSPC603R
(1) These registers are 603r-specific registers. Tey may not be supported by other PowerPC processors.
Figure 13 : PowerPC microprocessor programming model - Register
TSPC603R 5.2. Instruction set and addressing modes
The following subsections describe the PowerPC instruction set and addressing modes in general. 5.2.1.PowerPC instruction set and addressing modes All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining.
TSPC603R
5.3. Cache implementation
TSPC603R
Figure 14 : Data cache organization
5.4. Exception model
TSPC603R
Synchronous
Precise
Table 15 : PowerPC 603r microprocessor exception classifications
TSPC603R
Table 16 : Exceptions and conditions
TSPC603R
5.5. Memory management
5.6. Instruction timing
The 603r is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is reduced into discrete stages. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit. For example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. This improves the throughput of the instruction flow. For example, it may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of floating-point instructions can have a throughput of one instruction per cycle.
TSPC603R
6. PREPARATION FOR DELIVERY 6.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
6.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range.
7. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended : a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50 percent if practical.
TSPC603R 8. PACKAGES MECHANICAL DATA
The following sections provide the package parameters and mechanical dimensions for the CBGA packages.
8.1. CBGA package parameters
The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline . . . . . . . . . . . 21 mm x 21 mm Interconnects . . . . . . . . . . . . . 255 Pitch . . . . . . . . . . . . . . . . . . . . . 1.27 mm Maximum module height . . . 3.00 mm
8.2. Mechanical dimensions of the CBGA package
Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D G H K N P MILLIMETERS MIN MAX 21.000 BSC 21.000 BSC 2.450 3.000 0.820 0.930 1.270 BSC 0.790 0.990 0.635 BSC 5.000 16.000 5.000 16.000 INCHES MIN MAX 0.827 BSC 0.827 BSC 0.097 0.118 0.032 0.036 0.050 BSC 0.031 0.039 0.025 BSC 0.197 0.630 0.197 0.630
Figure 15 : Mechanical dimensions and bottom surface nomenclature of the CBGA package
TSPC603R 8.3. CI-CGA package parameters
The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CI-CGA). Package outline . . . . . . . . . . . 21 mm x 21 mm Interconnects . . . . . . . . . . . . . 255 Pitch . . . . . . . . . . . . . . . . . . . . . 1.27 mm Typical module height . . . . . . 3.84 mm
8.4. Mechanical dimensions of the CI-CGA package
Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.
NOTES :
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 21.000 BSC 21.000 BSC 3.84 BSC 0.790 0.990 1.270 BSC 1.545 1.695 0.635 BSC 5.000 16.000 5.000 16.000 3.02 BSC 0.10 BSC 0.25 0.35
Figure 16 : Mechanical dimensions and bottom surface nomenclature of the CI-CGA package
TSPC603R 9. CLOCK RELATIONSHIPS CHOICE
The 603r microprocessors offer customers numerous clocking options. An internal phase-lock loop synchronizes the processor (CPU) clock to the bus or system clock (SYSCLK) at various ratios. Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in frequency and phase by a frequency / phase detector which compares the input bus frequency (SYSCLK frequency) to a submultiple of the VCO. The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode). In the Table 17, the horizontal scale represents the bus frequency (SYSCLK) and the vertical scale represents the PLL-CFG0-3 signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
Table 17 : CPU frequencies for common bus frequencies and multipliers
Notes : 1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note : the AC timing specifications given in this document do not apply in PLL-bypass mode. 3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
CPU Frequency in MHZ (VCO Frequency in MHz) Core-to VCO Multiplier 2x 4x 2x 2x 2x 2x 2x 2x 2x 2x Bus 25 MHz - - - - - - - - - 150 (300) Bus 33.33 MHz - - - - - - 150 (300) 166 (333) 183 (366) 200 (400) Bus 40 MHz - - - - - 160 (320) 180 (360) 200 (400) 220 (440) 240 (480) PLL bypass Clock off Bus 50 MHz - - - 150 (300) 175 (350) 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) Bus 60 MHz - - 150 (300) 180 (360) 210 (420) 240 (480) 270 (540) 300 (600) - - Bus 66.67 MHz - - 166 (333) 200 (400) 233 (466) 267 (533) 300 (600) - - - Bus 75 MHz 150 (300) - 187 (375) 225 (450) 263 (525) 300 (600) - - - -
2x 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x
TSPC603R 10.SYSTEM DESIGN INFORMATION 10.1.PLL Power Supply Filtering
The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 17. The circuit should be placed as close to the AVdd pin to ensure it filters out as much noise as possible. The 0.1 mF capacitor should be closest to the AVdd pin, followed by the 10 mF capacitor, and finally the 10 W resistor to Vdd. These traces should be kept short and direct. 10 W 10 mF
AVdd 0.1 mF
Figure 17 : PLL Power Supply Filter Circuit
10.2.Decoupling Recommendations
10.3.Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. ALL NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the 603e.
10.4.Pull-up Resistor Requirements
TSPC603R 11. ORDERING INFORMATION TS (X) PC603R M G B / Q 12 L (C) Revision level Bus divider (to be confirmed) L : Any bus 75 MHz
TCS prefix (1) Prototype Type Temperature range : TC M : -55, +125 °C V : -40, +110 °C Package : G : GS : CBGA CI-CGA
Max internal processor speed (2) 6 8 10 12 14 : : : : : 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES For availability of the different versions, contact your TCS sale office
TSPC603R
Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES products are not authorized for use as critical components in life support devices or systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. The PowerPC names and logo type are trademarks of International Business Machines Corporation, used under licence