THIRD-GENERATION 32-BIT MICROPROCESSOR DESCRIPTION 68040 Thomson'

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THIRD-GENERATION 32-BIT MICROPROCESSOR DESCRIPTION 68040 Thomson'

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68040
THIRD-GENERATION 32-BIT MICROPROCESSOR
DESCRIPTION 68040 Thomson's third generation 68000-compatible, high-performance, 32-bit microprocessors. 68040 virtual memory microprocessor employing multiple, concurrent execution units highly integrated architecture provide very high performance monolithic HCMOS device. single chip, 68040 integrates 68030-compatible integer unit, IEEE 754-compatible floating-point unit (FPU), fully independent instruction data demand-paged memory management units (MMUs), including independent 4K-byte instruction data caches. high degree instruction execution parallelism achieved through multiple independent execution pipelines, multiple internal buses, full internal Harvard architecture, including separate physical caches both instruction data accesses. 68040 also directly supports cache coherency multimaster applications with dedicated onchip snooping logic. 68040 user-object-code compatible with previous members 68000 Family specifically optimized reduce execution time compiler-generated code. 68040 HCMOS technology, provides ideal balance between speed, power, physical device size. Figure simplified block diagram 68040. Instruction execution pipelined both integer unit FPU. Independent data instruction MMUs control main caches address translation caches (ATCs). ATCs speed logical-to-physical address translations storing recently used translations. snooper circuit ensures cache coherency multimaster multiprocessing applications. MAIN FEATURES 26-42 MIPS integer performance. 3.5-5.6 MFLOPS floating-point-performance. IEEE 754-Compatible FPU. Independant instruction data MMUs. 4K-byte physical instruction cache 4K-byte physical data cache accessed simultaneously. 32-bit, nonmultiplexed external address data buses with synchronous interface. User-object-code compatibility with earlier 68000 microprocessors. Multimaster multiprocessor support snooping. Concurrent integer unit, FPU, MMU, controller, snooper maximize throughput. 4-Gbyte direct addressing range. Software support including optimizing compiler unix* system port. IEEE 1149-1 test mode tag). MHz, 88915T clock driver suggested. SCREENING MIL-STD-883. DESC. Drawing 5962-93143. standards. suffix CQFP Gullwing shape lead Ceramic Quad Flat Pack
suffix Ceramic Grid Array Cavity down
This document contains information product. Specifications information herein subject change without notice.
February 1998
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SUMMARY
GENERAL DESCRIPTION
INTRODUCTION ASSIGNMENTS
CQFP
DETAILED SPECIFICATIONS
SCOPE APPLICABLE DOCUMENTS REQUIREMENTS
General Design construction 3.2.1 Terminal connections 3.2.2 Lead material finish 3.2.3 Package Electrical characteristics 3.3.1 Absolute maximum rating 3.3.2 Recommended condition Thermal consideration 3.4.1 General thermal consideration 3.4.2 Thermal characteristics Mechanical environment Marking
SIGNAL DESCRIPTION
QUALITY CONFORMANCE INSPECTION
DESC MIL-STD-883
ELECTRICAL CHARACTERISTICS
General requirements Static characteristics Dynamic characteristics Switching test circuit waveforms Programming model Data types addressing modes Instruction overview Instruction data caches Operand transfer mechanism Exception processing Memory management units
FUNCTIONAL DESCRIPTION
PREPARATION DELIVERY
Packaging Certificate compliance
HANDLING PACKAGE MECHANICAL DATA
pins pins CQFP pins Gullwing CQFP
ORDERING INFORMATION
10.1 MIL-STD-883 10.2 DESC Drawing 5962-93143. 10.3 Detailed 68040 part list
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GENERAL DESCRIPTION
Figure Block diagram.
INTRODUCTION 68040 enhanced, 32-bit, HCMOS microprocessor that combines integer unit processing capabilities 68030 microprocessor with independent 4K-byte data instruction caches on-chip FPU. 68040 maintains 32-bit registers available with entire 68000 Family well 32-bit address data paths, rich instruction set, versatile addressing modes. Instruction execution proceeds parallel with accesses internal caches, operations, controller activity. Additionally, integer unit optimized high-level language environments. 68040 user-object-code compatible with 68882 floating-point coprocessor conforms ANSI IEEE Standard binary floating-point arithmetic. been optimized execute most commonly used subset 68882 instruction set, includes additional instruction formats single double-precision rounding results. Floating-point instructions execute concurrently with integer instructions integer unit. MMUs support multiprocessing, virtual memory systems translating logical addresses physical addresses using translation tables stored memory. MMUs store recently used address mappings separate ATCs-on-chip. When contains physical address cycle requested processor, translation table search avoided physical address supplied immediately, incurring delay adress translation. Each transparent translation registers available that define one-to-one mapping adress space segments ranging size from Mbytes Gbytes each. Each provides read-only supervisor-only protections page basis. Also, processes given isolated address spaces assigning each unique table structure updating root pointer upon task swap. Isolated address spaces protect integrity independent processes. instruction data caches operate independently from rest machine, storing information fast access execution units. Each cache resides internal address internal data bus, allowing simultaneous access both. data cache provides writethrough copyback write modes that configured page-by-page basis. 68040 controller supports high-speed, nonmultiplexed, synchronous external interface, which allows following transfer sizes byte, word bytes), long word bytes), line bytes). Line accesses performed using burst transfers both reads writes provide high data transfer rates.
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ASSIGNMENTS
Figure Bottom view.
Table Internal logic C11, C13, K16, M16, R11, R13, S10, B10, B13, B15, B17, D17, F17, H17, L17, N17, Q17, S15, C10, C12, C14, H16, J16, L16, R12, B14, C17, G17, M17, R17,
Output drivers
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CQFP
Figure assignments.
Table Internal logic 113, 119, 121, 122, 124, 125, 129, 130, 141, 159, 105, 106, 146, 147, 148, 149, 155, 162, 163, 169, 176, 182, 183, 189, 195, 114, 126, 137, 158, 173,
Output drivers
102, 152, 166, 179,
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SIGNAL DESCRIPTION Figure Table describe signals 68040 indicate signal functions. test signals, TRST, TMS, TCK, TDI, TDO, comply with subset P-1149.1 IEEE testability standard.
Figure Functional signal groups.
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Table Signal index Signal Name Address Data Transfer type Transfer modifier Transfer line number User programmable attributes Read write Transfer size lock lock Cache inhibit Transfer start Transfer progress Transfer acknowledge Transfer error acknowledge Transfer cache inhibit Transfer burst inhibit Data latch enable Snoop control Memory inhibit request grant busy Cache disable disable Reset Reset Interrupt priority level Interrupt pending Autovector Processor status clock Mnemonic A31-A0 D31-D0 TT1, TM2, TLN1, TLN0 UPA1, UPA0 SIZ1, SIZ0 LOCK LOCKE CIOUT SC1, CDIS MDIS RSTI RSTO IPL2-IPL0 IPEND AVEC PST3-PST0 BCLK Function 32-bit address used address Gbytes 32-bit data used transfer bits data transfer Indicates general transfer type normal, MOVE alternate logical function code, acknowledge Indicates supplemental information about access Indicates which cache line being pushed loaded current line transfer User-defined signals, controlled corresponding user attribute bits from address translation entry Identifies transfer read write Indicates data transfer size. These signals, together with define active sections data Indicates transfer part read-modify-write operation, that sequence transfers should interrupted Indicates current transfer last locked sequence transfer Indicates processor will cache current transfer Indicates beginning transfer Asserted duration transfer Asserted acknowledge transfer Indicates error condition exists transfer Indicates current transfer should cached Indicates slave cannot handle line burst acces Alternate clock input used latch input data when processor operating mode Indicates snooping operation required during alternate master access Inhibits memory devices from responding alternate master access during snooping operations Asserted processor request mastership Asserted arbiter grant mastership processor Asserted current master indicate assumed ownership Dynamically disables internal caches assist emulator support Disables translation mechanism MMUs Processor reset Asserted during execution RESET instruction reset external devices Provides encoded interrupt level processor Indicates interrupt pending Used during interrupt acknowledge transfer request internal generation vector number Indicates internal processor status Clock input used derive signal timing
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Table Signal index (Continued) Signal Name Processor clock Test clock Test mode select Test data input Test data output Test reset Power supply Ground Mnemonic PCLK TRST Function Clock input used internal logic timing. PCLK frequency exactly BCLK frequency Clock signal IEEE P1149.1 test access port (TAP) Selects principle operations test-support circuitry Serial data input Serial data output Provides asynchronous reset controller Power supply Ground connection
DETAILED SPECIFICATIONS
SCOPE This drawing describes specific requirements microprocessor 68040 MHz, compliance with MIL-STD-883 class standard screening. APPLICABLE DOCUMENTS MIL-STD-883 MIL-STD-883 test methods procedures electronics. MIL-I-38535 general specifications microcircuits. DESC 5962-93143. REQUIREMENTS General microcircuits accordance with applicable document specified herein. Design construction 3.2.1 Terminal connections Depending package, terminal connections shall shown Figures
3.2.2 Lead material finish Lead material finish shall specified MIL-STD-853 (see enclosed 10). 3.2.3 Package macrocircuits packaged hermetically sealed ceramic packages which conform case outlines MIL-STD1835-or follow CMGA 10-179-PAK grid array, 9.1. similar CQCC1-F196C-U6 ceramic uniform lead chip carrier package with ceramic conductiv tie-bar internal drawing 9.2, gullwing shape CQFP 9.3.
precise case outlines described specification into MIL-STD-1835. Electrical characteristics
3.3.1 Absolute maximum ratings Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability.
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Table Absolute maximum ratings Symbol Tstg Tlead Parameter Supply voltage range Input voltage range Power dissipation Operating temperature Storage temperature range Junction temperature (see Note) Lead temperature Max.10 soldering Large buffers enabled Small buffers enabled Condition Min. Max. Unit
Note This device tested 125°C. Testing performed setting junction temperature 125°C Note allowing case ambient temperatures rise fall necessary exceed maximum Note junction temperature.
3.3.2 Recommended conditions Table Unless otherwise stated, voltages referenced reference terminal (see A.3).
Symbol Supply voltage range Logic level input voltage range Logic high level input voltage range High level output voltage level output voltage Clock frequency version version Case operating temperature range (see Note) Maximum operating junction temperature TJmax Parameter Min. 4.75 Typ. Max. 5.25 Unit
Note This device tested 125°C. Testing performed setting junction temperature 125°C Note allowing case ambient temperatures rise fall necessary exceed maximum Note junction temperature.
Thermal considerations 3.4.1 General thermal considerations This section given information only user. microprocessors becoming more complex requiring more power, need efficiently cool device becomes increasingly more important. past, 68000 Family, been able provide 0-70°C ambient temperature part speeds less than MHz. However, 68040, which arithmetic logic unit (ALU) speed, specified with maximum power dissipation particular mode, maximum junction temperature, thermal resistance from junction case. This provides more accurate method evaluating environment, taking into consideration both air-flow ambient temperature available. This also allows user information design cooling method which meets both thermal performance requirements constraints board environment. This section discusses device charateristics thermal management, several methods thermal management, example method cooling 68040.
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Thermal device characteristics 68040 presents some inherent characteristics which should considered when evaluating method cooling device. following paragraphs discuss these package power considerations. package 68040 being placed cavity-down alumina-ceramic 179-pin that specified thermal resistance from junction case 1°C/W. This package differs from previous 68000 Family packages which were cavity This cavity-down design allows attached surface package, which increases ability part dissipate heat through package surface attached heat sink. maximum perimeter that 68040 allows heat sink surface without interfering with capacitor pads 1.48" 1.48". specific dimensions design particular heat sink will need determined system designer considering both thermal performance requirements size requirements. Power considerations 68040 maximum power rating, which varies depending operating frequency output buffer mode combination being used. large buffer output mode dissipates more power than small, higher frequencies operation dissipate more power than lower frequencies. following paragraphs discuss tradeoffs using different output buffer modes, calculation specific maximum power dissipation different modes, relationship thermal resistances temperatures. Output buffer mode 68040 capable resetting enable combination either large buffers small buffers outputs miscellaneous control signals, data bus, address transfer attribute pins. large buffers offer quicker output times, which allow easier logic design. However, they driving about times much current small buffers (refer 68040 Electrical specifications current output). designer should consider whether quicker timings present enough advantage justify additional consideration individual signal terminations, power consumption, required cooling device. Since 68040 powered-up eight output buffer modes upon reset, actual maximum power consumption 68040 rated particular maximum operating frequency dependent upon power mode. Therefore, 68040 rated maximum power dissipation either large buffers small buffers particular frequency (refer 68040 Electrical specifications). This allows possibility some thermal management controlled upon reset. following equation provides rough method calculate maximum power consumption chosen output buffer mode PDSB (PDLB PDSB) (PINSLB PINSCLB) (Equation 4.1) where PDSB PDLB PINSLB PINSCLB Max. power dissipation output buffer mode selected Max. power dissipation small buffer mode (all outputs) Max. power dissipation large buffer mode (all outputs) Number pins large buffer mode Number pins capable large buffer mode
Table shows simplified relationship maximum power dissipation eight possible configurations output buffer modes. Table Maximum power dissipation output buffer mode configurations Output configuration Data Small buffer Small buffer Small buffer Small buffer Large buffer Large buffer Large buffer Large buffer Address transfer attrib. Small buffer Small buffer Large buffer Large buffer Small buffer Small buffer Large buffer Large buffer Misc. control signals Small buffer Large buffer Small buffer Large buffer Small buffer Large buffer Small buffer Large buffer PDSB PDSB (PDLB PDSB) PDSB (PDLB PDSB) PDSB (PDLB PDSB) PDSB (PDLB PDSB) PDSB (PDLB PDSB) PDSB (PDLB PDSB) PDSB (PDLB PDSB) Maximum power dissipation
calculate specific power dissipation specific design, termination method each signal must considered. example, signal output that connected would dissipate additional power were configured large buffer rather than small buffer mode.
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Relationships between thermal resistances temperatures Since maximum operating junction temperature been specified 125°C. maximum case temperature, obtained from (Equation 4.2) where Maximum case temperature Maximum junction temperature Maximum power dissipation device Thermal resistance between junction case (Equation 4.3)
general, ambient temperature, function following formula
Where thermal resistance from case ambient, only user-dependent parameter once buffer output configuration been determined. seen from equation (4.3), reducing case ambient thermal resistance increases maximum operating ambient temperature. Therefore, utilizing such methods heat sinks ambient cooling minimize higher ambient operating temperature lower junction temperature achieved. However, easier approach thermal evaluation uses following formulas alternatively, where thermal resistance from junction ambient CA). This total thermal resistance package, combination components, These components represent barrier heat flow from semiconductor junction package (case) surface from case outside ambient (JC). Although device related cannot influenced user, user dependent. Thus, good thermal management user significantly reduce achieving either lower semiconductor junction temperature higher ambient operating temperature. Thermal management techniques attain reasonable maximum ambient operating temperature, user must reduce barrier heat flow from semiconductor junction outside ambient JA). only accomplish this significantly reduce applying such thermal management techniques heat sinks ambient cooling. following paragraphs discuss some results thermal study 68040 device without using thermal management techniques using only air-flow cooling, using only heat sink, using heat sink combined with air-flow cooling. Thermal characteristics still sample size three 68040 packages tested free-air cooling with heat sink. Measurements showed that average 22.8°C/W with standard deviation 0.44°C/W. test performed with power being dissipated from within package. test determined that will decrease slightly increasing power dissipation range possible. Therefore, since variance within possible power dissipation range negligible, assumed calculation purposes that valid power levels. Using formulas introduced previously, Table shows results maximum power dissipation with heat sink air-flow (refer Table calculate other power dissipation values). Table Thermal parameters with heat sink air-flow Defined paramaters Watts Watts 125°C 125°C Measured Calculated (Equation 4.5) (Equation 4.4)
1°C/W 1°C/W
21.8°C/W 21.8°C/W
20.8°C/W 20.8°C/W
122°C 120°C 59.6°C 16°C
seen looking ambient temperature results, most users will want implement some type thermal management obtain more reasonable maximum ambient temperature. Thermal characteristics forced sample size three 68040 packages tested forced cooling wind tunnel with heat sink. This test performed with power being dissipated from within package. previously mentioned, since variance within possible power range negligible, assumed calculation purposes that constant power levels. Using previous formulas, Table shows results maximum power dissipation with air-flow heat sink (refer Table calculate other power dissipation values).
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Table Thermal parameters with forced flow heat sink Thermal Mgmt. Technique Air-flow velocity Defined parameters 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C Measured Calculated
1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W
11.7°C/W 10°C/W 8.9°C/W 8.5°C/W 8.3°C/W 11.7°C/W 10°C/W 8.9°C/W 8.5°C/W 8.3°C/W
10.7°C/W 9°C/W 7.9°C/W 7.5°C/W 7.3°C/W 10.7°C/W 9°C/W 7.9°C/W 7.5°C/W 7.3°C/W
122°C 122°C 122°C 122°C 122°C 120°C 120°C 120°C 120°C 120°C
89.9°C 95°C 98.3°C 99.5°C 100.1°C 66.5°C 75°C 80.5°C 82.5°C 83.5°C
reviewing maximum ambient operating temperatures, seen that using all-small-buffer configuration 68040 with relatively small amount flow (100 LFM), 0-70°C ambient operating temperature achieved. However, depending output buffer configuration available forced-air cooling, additional thermal management techniques required. Thermal characteristics with heat sink choosing heat sink designer must consider many factors heat sink size composition, method attachment, choice connection. following paragraphs discuss relationship these decisions thermal performance design noticed during experimentation. heat sink size most significant parameters consider selection heat sink. Obviously larger heat sink will provide better cooling. However, less obvious that most benefit larger heat sink type used experimentation would still conditions. Under forced-air conditions LFM, difference between becoms very small (0.4°C/W less). This difference continues decrease forced flow increases. particular heat sink used testing perimeter package surface area available within capacitor pads 68040 (1.48" 1.48") showed nice compromise between height thermal performance needs. heat sink base perimeter area 1.24" 1.30" heigh 0.49". pin-fin-type (i.e. nails) design composed alloy. heat sink shown Figure obtained through Thermalloy Inc. referencing part number 2338B.
Figure Heat sink example.
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heat sinks tested were made from extrusion products. planar face heat sink mating package should have good degree planarity curvature, curvature should convex central region heat sink surface provide intimate physical contact surface. heat sinks tested this criteria. Nonplanar, concave curvature central regions heat sink will result poor thermal contact package. specification needs determined planarity surface part heat sink design. Although there several ways attach heat sink package, easiest demountable heat sink attach called attach developed Thermalloy (see Figure heat sink clamped package with help steel spring plastic frame plastic shoes Besides height heat sink plastic frame, additional height added package. interface between ceramic package heat sink evaluated both (e.i., thermal grease) interfaces still air. thermal grease reduced quite significantly (about °C/W) still air. Therefore, used other testing done with heat sink. According other testing, attachment with thermal grease provided about same thermal performance thermal epoxy were used.
Figure Heat sink with attachment.
sample size 68040 package tested still with heat sink attachment method previously described. This test performed with power being dissipated from within package. Since variance within possible power range negligible, assumed calculation purposes that constant power levels. Table shows result assuming maximum power dissipation part (refer Table calculate other power dissipation values). Table Thermal parameters with heat sink air-flow Thermal Mgmt. Technique Heat sink 2338B 2338B Defined parameters 125°C 125°C Measured Calculated
1°C/W 1°C/W
14°C/W 14°C/W
13°C/W 13°C/W
122°C 120°C
83°C 55°C
Thermal characteristics with heat sink forced sample size three 68040 packages tested forced-air cooling wind tunnel with heat sink. This test performed with power being dissipated from within package. mentioned previously, variance within possible power range negligible assumed calculation purposes that valid power levels. Table shows results, assuming maximum power dissipation with flow heat sink thermal management (refer Table calculate other power dissipation values).
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Table Thermal parameters with heat sink air-flow Thermal Mgmt. Technique Air-flow Heat sink 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B Defined parameters 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C Measured Calculated
1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W
3.1°C/W 2.2°C/W 1.7°C/W 1.5°C/W 1.4°C/W 3.1°C/W 2.2°C/W 1.7°C/W 1.5°C/W 1.4°C/W
2.1°C/W 1.2°C/W 0.7°C/W 0.5°C/W 0.4°C/W 2.1°C/W 1.2°C/W 0.7°C/W 0.5°C/W 0.4°C/W
122°C 122°C 122°C 122°C 122°C 120°C 120°C 120°C 120°C 120°C
115.7°C 118.4°C 119.9°C 120.5°C 120.8°C 109.5°C 114°C 116.5°C 117.5°C 118°C
Thermal testing summary Testing proved that heat sink combination with relatively small amount air-flow (100 less) will easily realize 0-70°C ambient operating temperature 68040 with almost configuration output buffers. heat sink alone capable providing necessary cooling, depending particular heat sink height size restraints, maximum ambient operating temperature required, output buffer configuration chosen. Also forced cooling alone attain 0-70°C ambient operating temperature. However this factor highly dependent output buffer configuration chosen available forced cooling. Figure summary test results relationship between air-flow 68040.
Figure Relationship air-flow PGA.
3.4.2 Characteristics guaranted Table
Package Symbol CQFP Parameter Thermal resistance junction-to-ambient Thermal resistance junction-to-case Thermal resistance junction-to-ambient Thermal resistance junction-to-case Value Figure Unit °C/W °C/W °C/W °C/W
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Mechanical environment microcircuits shall meet mechanical environmental requirements either MIL-STD-883 class devices standard screening. Marking document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum Thomson logo, Manufacturer's part number, Class identification, Date-code inspection lot, identifier available, Country manufacturing. QUALITY CONFORMANCE INSPECTION DESC MIL-STD-883 accordance with MIL-M-38535 method 5005 MIL-STD-883. Group inspections performed each production lot. Group inspection performed periodical basis. ELECTRICAL CHARACTERISTICS General requirements static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below Table Static electrical characteristics electrical variants, Table Dynamic electrical characteristics 68040 MHz, MHz). static characteristics (Table 12), test methods refer 748-2 method number, where existing. dynamic characteristics (Table 13), test methods refer clause this specification. Indication column means minimum maximum operating temperature defined sub-clause 3.3.2. here above. Static characteristics Table Electrical characteristics 55°C TJmax 4.75 5.25 unless otherwise specified Notes Symbol Input high voltage Input voltage Undershoot Input leakage current BCLK, CDIS, AVEC IPLn, MDIS, PCLK, RSTI, SCn, TBI, TCI, TCK, CIOUT, LOCK, Characteristic Min. Max. Unit
ITSI
Hi-Z (off-state) leakage current
Signal input current Signal high input current Output high voltage Larger buffers Small buffers
LOCKE, SIZn, TDO, TIP, TLNn, TMn, TTn, UPAn TMS, TDI, TRST TMS, TDI, TRST
0.94
0.18 0.16
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Table Electrical characteristics (Continued) Symbol Output voltage Larger buffers Small buffers Power dissipation 125°C) Larger buffers enabled Small buffers enabled Capacitance Note Characteristic Min. Max. Unit
Note testing performed using worst-case test conditions unless otherwise specified. Note Note Note Note Maximum operating junction temperature (TJ) 125°C. Minimum case operating temperature (TC) 55°C. This device tested 125°C. Testing performed setting junction temperature 125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Note Capacitance periodically sampled rather than tested. Note Power dissipation vary between limits depending application. Dynamic characteristics Table Clock timing specifications (see Figure 55°C TJmax 4.75 5.25 unless otherwise specified Notes Frequency operation PCLK cycle time PCLK rise time Note PCLK fall time Note PCLK duty cycle measured Note PCLK pulse width high measured Notes PCLK pulse width measured Notes BCLK cycle time BCLK rise fall time BCLK duty cycle measured Note BCLK pulse width high measured Note BCLK pulse width measured Note PCLK, BCLK frequency stability Note PCLK BCLK skew 47.5 Characteristic Min. Max. 52.5 10.5 10.5 1000 Min. Max. 46.67 53.33 1000 Unit
Note testing performed using worst-case test conditions unless otherwise specified. Note Note Note Note Maximum operating junction temperature (TJ) 125°C. Minimum case operating temperature (TC) 55°C. This device tested 125°C. Testing performed setting junction temperature 125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Note Specification value maximum frequency operation. Note tested, shall guaranteed limits specified.
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Figure Clock input timing.
Table Output timing specifications (Note (Figures These output specifications only they must scaled lower operating frequencies. Refer 6804DH/AD further information. 55°C TJmax 4.75 5.25 unless otherwise specified Notes Characteristic
Large buffer Small buffer Large buffer Small buffer Unit Note Note Note Note Min. Max. Min. Max. Min. 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 Max. Min. 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 Max.
BCLK adress CIOUT, LOCK, LOCKE, SIZn, TLN, TMn, TTn, UPAn valid Note BCLK output invalid (output hold) BCLK valid BCLK valid BCLK data-out valid Note BCLK data-out invalid (output hold) Note BCLK output impedance Notes BCLK data-out high impedance BCLK multiplexed address valid Note BCLK multiplexed address driven Note BCLK multiplexed address high impedance Notes BCLK multiplexed data driven Note BCLK multiplexed data valid Note BCLK address, CIOUT, LOCK, LOCKE, SIZn, TLNn, TMn, TTn, UPAn high impedance Note BCLK high impedance BCLK valid
6.50
6.50
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Table Output timing specifications (Continued) Characteristic BCLK valid BCLK valid BCLK IPEND, PSTn, RSTO valid
Large buffer Small buffer Large buffer Small buffer Unit Note Note Note Note Min. Max. Min. Max. Min. 6.50 6.50 6.50 Max. Min. 6.50 6.50 6.50 Max.
Note Note Note Note Note Note Note
Output timing specified valid signal measured pin. Large buffer timing specified driving transmission line with length characterized one-way propagation delay, terminated through Large buffer output impedance typically resulting incident wave switching this environnement. Small buffer timing specified driving unterminated transmission line with length characterized one-way propagation delay. Small buffer output impedance typically small buffer specifications include approximately signal propagate lenght transmission line back.
Note testing performed using worst-case test conditions unless otherwise specified. Note following pins active CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, are_ AVEC, Note MDIS, RST0, RSTI, TBI, TCI, TEA, TIP, TRST, Note Note Note Note Maximum operating junction temperature (TJ) 125°C. Minimum case operating temperature (TC) 55°C. This device tested 125°C. Testing performed setting junction temperature 125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Note Timing specifications address output timing apply when normal operation selected. Note Specifications should used when multiplexed mode operation enabled. Note Timing specifications data output timing apply when normal operation selected. SpeNote cifications should used when multiplexed mode operation enabled.
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Table Input timing specifications (Figures 55°C TJmax 4.75 5.25 unless otherwise specified Notes Data-in valid BCLK (setup) BCLK data-in invalid (hold) BCLK data-in high impedance (read followed write) valid BCLK (setup) valid BCLK (setup) valid BCLK (setup) valid BCLK (setup) BCLK TEA, TCI, invalid (hold) AVEC valid BCLK (setup) BCLK AVEC invalid (hold) width high Data-in valid (setup) data-in invalid (hold) BCLK hold high BCLK Data-in valid BCLK (DLE mode setup) BCLK Data-in invalid (DLE mode hold) valid BCLK (setup) valid BCLK (setup) CDIS, MDIS valid BCLK (setup) IPLn valid BCLK (setup) BCLK CDIS, IPLn, MDIS invalid (hold) Address valid BCLK (setup) SIZn valid BCLK (setup) valid BCLK (setup) valid BCLK (setup) valid BCLK (setup) BCLK address SIZn, TTn, R/W, invalid (hold) valid BCLK (setup) BCLK invalid (hold) BCLK high impedance (68040 assumes mastership) RSTI valid BCLK BCLK RSTI invalid Mode select setup RSTI negated Note RSTI negated mode selects invalid Note Characteristic Min. Max. Min. 36.5 Max. Unit
Note testing performed using worst-case test conditions unless otherwise specified. Note following pins active CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, are_ AVEC, Note MDIS, RST0, RSTI, TBI, TCI, TEA, TIP, TRST, Note Note Note Note Maximum operating junction temperature (TJ) 125°C. Minimum case operating temperature (TC) 55°C. This device tested 125°C. Testing performed setting junction temperature 125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Note levels CDIS, MDIS, IPL2-IPL0 signals enable disable multiplexed mode, data latch Note enable mode, driver impedance selection respectively.
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Figure Read write timing.
Note Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT Table JTAG timing application (Figures 55°C TJmax 4.75 5.25 unless otherwise specified Notes frequency cycle time clock pulse width measured rise fall times TRST setup time falling edge TRST assert time Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance Characteristic Min. Max. Unit
Note testing performed using worst-case test conditions unless otherwise specified. Note Note Note Note Maximum operating junction temperature (TJ) 125°C. Minimum case operating temperature (TC) 55°C. This device tested 125°C. Testing performed setting junction temperature 125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
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Table Boundry scan instruction codes Instruction selected Extest Highz Sample preload DRVCTLT Shutdown Private DRVCTLS Bypass Test data register accessed Boundry scan Bypass Boundry scan Boundry scan Bypass Bypass Boundry scan Bypass
Switching test circuit waveforms
Figure Address data timing. Multiplexed mode.
Figure timing burst access.
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Figure arbitation timing.
Figure Snoop timing.
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Figure Snoop miss timing.
Figure Other signal timing.
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Figure Clock input timing diagram.
Figure TRST timing diagram.
Figure Boundry scan timing diagram.
Figure Test access port timing diagram.
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FUNCTIONAL DESCRIPTION Programming model 68040 integrates functions integer unit, MMU, FPU. shown Figure registers depicted programming model provide access control three units. registers partitioned into levels privilege user supervisor. User programs, executing user mode, only resources user model. System software, executing supervisor mode, unrestricted access processor resources. integer portion user programming model, consisting general-purpose, 32-bit registers control registers, same user programming model 68030. 68040 user programming model also incorporates 68882 programming model consisting eight, floating-point, 80-bit data registers, floating-point control register, floating-point status register, floating-point instruction address register. supervisor programming model used exclusively 68040 system programmers implement operating system functions, control, memory management subsystems. This supervisor user distinction 68000 architecture carefully planned that application software written execute nonprivileged user mode migrate 68040 from 68000 platform without modification. Since system software usually modified system designers when porting design, control features properly placed supervisor programming model. example, transparent translation registers 68040 only read written supervisor software programming resources user application programs unaffected existence transparent translation registers Registers D0-D7 data registers containing operands field bits), byte bit), word bit), long-word bit), quad-word bit) operations. Registers A0-A6 stack pointer registers (user, interrupt, master) address registers that used software stack pointers base address registers. Register user stack pointer user mode, either interrupt master stack pointer (A7' A7'') supervisor mode. supervisor mode, active stack pointer (interrupt master) selected based status register (SR). address registers used word long-word operations, general-purpose registers (D0-D7, A0-A7 Figure used index registers. eight, 80-bit, floating-point data registers (FP0-FP7) analogous integer data registers (D0-D7) 68000 Family processors. Floating-point data registers always containt extended-precision numbers. external operands, regardless data format, converted extended-precision values before being used floating-point calculation stored floating-point data register. program counter (PC) usually contains address instruction being executed 68040. During instruction execution exception processing, processor automatically increments contents places value appropriate. status register supervisor programming model) contains condition codes that reflect results previous operation used conditional instruction execution program. lower byte accessible user mode condition code register (CCR). Access upper byte restricted supervisor mode. part exception processing, vector number exception provides index into exception vector table. base address exception vector table stored vector base register (VBR). displacement exception vector added value when 68040 accesses vector table during exception processing. Alternate function code registers, (source destination), contain 3-bit function codes. Function codes considered extensions 32-bit linear address. Function codes automatically generated processor select address spaces data program accesses user supervisor modes. alternate function code registers used certain instructions explicitly specify function codes various operations. cache control register (CACR) controls enabling on-chip instruction data caches 68040. supervisor root pointer (SRP) user root pointer (URP) registers point root address translation table tree used supervisor mode user mode accesses. used logical address zero, used one. translation control register (TC) enables logical-to-physical address translation selects either page sizes. shown Figure there four transparent translation registers ITT0 ITT1 instruction accesses DTT0 DTT1 data accesses. These registers allow portions logical address space transparently mapped accessed without resident descriptors ATC. status register (MMUSR) contains status information from execution PTEST instruction. PTEST instruction searches translation tables logical address specified this instruction's effective address field DFC. 32-bit floating-point control register (FPCR) contains exception enable byte that enables disables traps each class floating-point exceptions mode byte that sets user-selectable modes. FPCR read written user cleared hardware reset restore operation null state. When cleared, FPCR provides IEEE standard defaults. floating-point status register (FPSR) contains condition code byte, quotient bits, exception status byte, accrued exception byte. bits FPSR read written user. Execution most floating-point instructions modifies this register. subset instructions that generate exception traps, 32-bit floating-point instruction address register (FPIAR) loaded with logical address instruction before instruction executed. This address then used floating-point exception handler locate floating-point instruction that caused exception. move floating-point data register (FMOVE) instruction from FPCR, FPSR, FPIAR) move multiple data registers (FMOVEN) instruction cannot generate floating-point exceptions therefore, these instructions modify FPIAR. Thus, FMOVE FMOVEM instructions used read FPIAR trap handler without changing previous value.
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Figure Programming model.
Data types addressing modes 68040 supports basic data types shown Table Some data types apply only integer unit, some only FPU, some both integer unit FPU. addition, instruction supports operations other data types such memory addresses. Table Data types Operand data type field Byte integer Word integer Long-word integer Quad-word integer byte Single-precision real Double-precision real Extended-precision real Integer unit. three integer data formats that common both integer unit (byte, word, long word) standard twos-complement data formats defined 68000 Family architecture. Whenever integer used floating-point operation, integer automatically converted extended-precision floating-point number before being used. ability effectively integers floating-point operations saves user memory because integer representation number usually requires fewer bits than equivalent floating-point representation. Size 1-32 bits bits bits bits bits bits bits bits bits bits Execution unit (IU*, FPU) data registers Memory-only, aligned 16-byte boundary 1-bit sign, 8-bit exponent, 23-bit mantissa 1-bit sign, 11-bit exponent, 52-bit mantissa 1-bit sign, 15-bit exponent, 64-bit mantissa Field consecutive bits Packaged digits byte Unpacked digit byte Notes
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Single- double-precision floating-point data formats implemented defined IEEE standard. These data formats main floating-point formats should used most calculations involving real numbers. extended-precision data format also conformance with IEEE standard, standard does specify this format level does single- double-precision. memory format consists bits (three long words). Only bits actually used other bits reserved future long-word alignment floating-point data structures memory. extended-precision format 15-bit exponent, 64-bit mantissa, 1-bit mantissa sign. Extended-precision numbers intended temporary variables, intermediate values, where extra precision needed. 68040 addressing modes shown Table register indirect addressing modes support post-increment, predecrement, offset, indexing, which particularly useful handling data structures common sophisticated applications high-level languages. program counter indirect mode also indexing offset capabilities this addressing mode typically required support position-independent software. addition these addressing modes, 68040 provides index sizing scaling features that enhance software performance. Data formats supported orthogonally arithmetic operations appropriate addressing modes. Table Addressing modes Addressing modes Register direct Date register direct Address register direct Register indirect Address register Address register Address register Address register indirect indirect with postincrement indirect with predecrement indirect with displacement (An) (An) (An) (d16, (d8, (bd, ([bd, An], ([bd, Xn], (d8, (bd, ([bd, PC], ([bd, Xn], xxx.W xxx.L (data) Syntax
Register indirect with index Address register indirect with index (8-bit displacement) Address register indirect with index (base displacement) Memory indirect Memory indirect postincrement Memory indirect preindexed Program counter indirect with displacement Program counter indirect with index indirect with index (8-bit displacement) indirect with index (base displacement Program counter memory indirect memory indirect postindexed memory indirect preindexed Absolute Absolute short Absolute long Immediate
Notes Data register, D0-D7 Address register, A0-A7 twos-complement sign-extended displacement added part effective address calculation size (d8) (d16) bits when omitted, assemblers value zero. Address data register used index register form SIZE*SCALE, where SIZE (indicates index register size) SCALE (index register multiplied SCALE) SIZE SCALE optional. twos-complement base displacement when present, size bits. Outer displacement added part effective address calculation after memory indirection optional with size bits. Program counter. (data) Immediate value bits. Effective address. Used indirect address long-word address.
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Instruction overview instruction provided 68040 listed Table instruction been tailored support high-level languages optimized those instructions most commonly executed (however, instructions listed fully supported). Many instructions operate bytes, words, long words, most instructions addressing modes Table Table Instruction summary Mnemonic *ABCD *ADD *ADDA *ADDI *ADDQ *ADDX *AND *ANDI *ASL, *Bcc *BCHG *BCLR *BFCHG *BFCLR *BFEXTS *BFEXTU *BFFFO *BFINS *BFSET *BFTST *BKPT *BRA *BSET *BSR *BTST *CAS *CAS2 *CHK *CHK2 *CINV *CLR *CMP *CMPA *CMPI *CMPM *CMP2 *CPUSH *DBcc *DIVS, DIVSL *DIVU, DIVUL *EOR *EORI *EXG *EXT, EXTB *ILLEGAL *JMP *JSR *LEA *LINK *LSL, Description decimal with extend address immediate quick with extend Logical Logical immediate Arithmetic shift left right Branch conditionally Test change Test clear Test field change Test field clear Signed field extract Unsigned field extract field find first field insert Test field Test field Breakpoint Branch Test Branch subroutine Test Compare swap operands Compare swap dual operands Check register against bounds Check register against upper lower bounds Invalidate cache entries Clear Compare Compare address Compare immediate Compare memory memory Compare register against upper lower bounds Push then invalidate cache entries Test condition, decrement branch Signed divide Unsigned divide Logical exclusive Logical exclusive immediate Exchange registers Sign extend Take illegal instruction trap Jump Jump subroutine Load effective address Link allocate Logical Shift left right Mnemonic *MOVE *MOVE16 *MOVEA *MOVE *MOVE *MOVE *MOVEC *MOVEM *MOVEP *MOVEQ *MOVES *MULS *MULU *NBCD *NEG *NEGX *NOP *NOT *ORI *PACK *PEA *PFLUSH *PTEST *RESET *ROL, *ROXL, ROXR *RTD *RTE *RTR *RTS *SBCD *Scc *STOP *SUB *SUBA *SUBI *SUBQ *SUBX *SWAP *TAS *TRAP *TRAPcc *TRAPV *TST UNLK UNPK Description Move 16-byte block move Move address Move condition code register Move status register Move user stack pointer Move control register Move multiple registers Move peripheral Move quick Move alternate address space Signed multiply Unsigned multiply Negate decimal with extend Negate Negate with extend operation Logical complement Logical inclusive Logical inclusive immediate Pack Push effective address Flush entry(ies) ATCs Test logical address Reset external devices Rotate left right Rotate with extend left right Return deallocate Return from exception Return restore codes Return from subroutine Substract decimal with extend conditionally Stop Subtract Subtract address Subtract immediate Subtract quick Subtract with extend Swap register words Test Trap Trap Trap Trap operand conditionally overflow operand
Unlink Unpack
68040 additions alterations 68030 68881 68882 instruction sets.
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Table Floating-point instructions Mnemonic *FABS *FADD *FBcc *FCMP *FDBcc *FDIV *FMOVE *FMOVEM *FMUL Description Floating-point absolute value Floating-point Branch floating-point condition Floating-point compare Floating-point decrement branch Floating-point divide Move floating-point register Move multiple floating-point registers Floating-point multiply Mnemonic *FNEG *FRESTORE *FSAVE *FScc **FSQRT *FSUB *FTRAPcc *FTST Description Floating-point negate Restore floating-point internal state Save floating-point internal state according floating-point condition Floating-point Square Root Floating-point substract Trap floating-point condition Floating-point test
68040 additions alterations 68030 68881 68882 instruction sets.
68040 floating-point instructions, commonly used subset 68882 instruction set, implemented hardware. remaining unimplemented instructions less frequently used efficiently emulated software, maintaining compatibility with 68881 68882 floating-point coprocessors. 68040 instruction includes MOVE16, user instruction that allows high-speed transfers 16-byte blocks between external devices such memory memory coprocessor memory. Instruction data caches Studies have shown that typical programs spend much their execution time main routines tight loops. Earlier members 68000 Family took advantage this locality reference phenomenon varying degrees. 68040 takes further advantage cache technology with two, independent, on-chip, physical address space caches, instructions data. caches reduce processor's external activity increase throughput lowering effective memory access time. typical system design, large caches 68040 yield very high rate, providing substantial increase system performance. Additionally, caches automatically burstfilled from external whenever cache miss occurs. autonomous nature caches allows instruction-stream fetches, data-stream fetches, third external access occur simultaneously with instruction execution. example, 68040 requires both instruction-stream access external peripheral access instruction resident on-chip cache, peripheral access proceeds unimpeded rather than being queued behind instruction fetch. data operand also required resident data cache, also accessed without hindering either instruction access from cache peripheral access external chip. parallelism inherent 68040 also allows multiple instructions that require external accesses execute concurrently while processor performing external access previous instruction.
6.4.1 Cache organization instruction data caches four-way set-associative with sets four, 16-byte lines total cache storage bytes each. shown Figure each 16-byte line contains address state information. State information each entry consists valid flag entire line both instruction data caches write status each long word data cache. write status data cache signifies whether long-word data dirty (meaning that data cache been modified been written back external memory) data copyback pages.
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Figure Cache organization overview.
caches accessed physical addresses from on-chip MMUs. translation upper bits logical address occurs concurrently with accesses into array cache lower address bits. output compared with field cache determine lines selected matches translated physical address. matches entry valid, then cache hit. cache hits access read, appropriate long word from cache line multiplexed onto appropriate internal bus. cache hits access write, data, regardless size, written appropriate portion corresponding longword entry cache. When data cache miss occurs previously valid cache line needed cache line, dirty data line will internally buffered copied back memory after cache line been loaded. Pushing dirty data forced CPUSH instruction. Cachability data each memory page controlled bits page descriptor each page. Cachable pages either writethrough copyback, with write-allocate misses writethrough pages. Non-cachable pages also specified noncachable forcing accesses these pages occur order instruction execution.
6.4.2 Cache coherency 68040 ability snoop external during accesses other masters maintain coherency between 68040's caches external memory systems. External write cycles snooped both instruction cache data cache whereas, external read cycles snooped only data cache. addition, external cycles flagged snoopable nonsnoopable. When external cycle marked snoopable, snooper checks caches coherency conflict based state corresponding cache line type external cycle.
Although internal execution units snooper circuit have access on-chip caches, snooper priority over execution units allow snooper resolve coherency discrepancies immediately.
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6.4.3 Cache instructions 68040 supports following instructions cache maintenance. Both instructions selectively operate data instruction cache.
CINV Invalidates single line, lines physical page, entire cache. CPUSH Pushes selected dirty data cache lines memory, then invalidates selected lines. Operand transfer mechanisms 68040 external synchronous supports multiple masters overlaps arbitration with data transfers. optimized perform high-speed transfers from external cache memory. data address buses each bits wide.
6.5.1 Transfer types 68040 provides signals (TT1-TT0) that define four types transfers normal access, MOVE16 access, alternate access, interrupt acknowledge access. Normal accesses identify normal memory references MOVE16 accesses memory accesses MOVE16 instruction alternate accesses identify accesses undefined address spaces (function code values interrupt acknowledge access used fetch interrupt vector during interrupt exception processing. 6.5.2 Burst transfer operation During burst read write cache transfers, values address transfer type signals change they address first requested item cache line. When 68040 request burst read transfer cache line, address indicates address long word line needed first, memory system expected provide data following order (modulo (long-word offsets). first address needed from offset nevertheless, four long words must transferred. Burst writes occur similar manner. 6.5.3 snooping snooping ensures that data main memory consistent with data on-chip caches. alternate master performing read transfer snooping enabled, snoop logic determines that on-chip data cache dirty data (data valid consistent with memory) this transfer, ther memory prevented from responding read request, 68040 supplies data directly master. alternate master performing write transfer snooping enabled, snooper determines that on-chip caches valid line this request, then snooper either invalidate update line selected snoop control signals.
Exception processing 68040 provides same extensions exception stacking process 68030. status register set, master stack pointer used task-related exceptions. When nontask-related exception occurs (i.e., interrupt), cleared, interrupt stack pointer used. This feature allows task's stack area carried within single processor control block, tasks initiated simply reloading master stack pointer setting bit. externally generated exceptions interrupts, errors, reset conditions. interrupts requests from external devices processor action whereas, error reset signals used access control processor initialization. internally generated exceptions come from instructions, address errors, tracing, breakpoints. TRAP, TRAPcc, TRAPVcc, FTRAPcc, CHK, CHK2, instructions generate exceptions part their instruction execution. Tracing behaves like very high-priority, internally generated interrupt whenever processed. other internally generated exceptions caused unimplemented floating-point instructions, illegal instructions, instruction fetches from addresses, privilege violations. Finally, generate exceptions, access violations when invalid descriptors encountered during table searches. Exception processing 68040 occurs following sequence internal copy made status register, vector number exception determined, current processor status saved, exception vector offset determined multiplying vector number four. This offset then added contents determine memory address exception vector. instruction address given exception vector fetched, normal instruction decoding execition started. Memory management units full addressing range 68040 Gbytes (4,294,967,296 bytes). However, most 68040 systems implement much smaller physical memory. Nonethless, using virtual memory techniques, system made appear have full Gbytes physical memory available each user program. independent instruction data MMUs fully support demandpaged virtual-memory operating systems with either page sizes. addition main function memory management, each protects supervisor areas from accesses user programs also provides write protection page-by-page basis. maximum efficiency, each operates parallel with other processor activities.
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6.7.1 Translation mechanism Because logical-to-physical address translation most frequently executed operations 68040 MMUs, this task been optimized. Each initiates address translation searching descriptor containing address translation information ATC. descriptor does reside ATC, then performs external cycles controller search translation tables physical memory. After being located, page descriptor loaded into ATC, address correctly translated access, provided exception conditions encountered. 6.7.2 Address translation cache integral part translation function previously described dual cache memory that stores recently used logicalto-physical address translation information (page descriptors) instruction date accesses. These caches 64-entry, four-way, associative. Each compare logical address incoming access against entries. entries matches, there hit, sends physical address controller, which then starts external cycle (provided there corresponding cache access). 6.7.3 Translation tables translation tables 68040 have threelevel tree structure reside main memory. Since only portion complete tree needs exist time, tree structure minimizes amount memory necessary tables most programs. shown Figure either user root pointer supervisor root pointer points first level table, depending values function code access. Table entries second level tree (pointer tables) contain pointers third level (page tables). Entries page tables contain either page descriptors indirect pointers page descriptors. mechanism performing table search operations uses portions logical address indices) each level search. addresses translation table entries physical addresses.
Figure Translation table structure.
There variations table searches both page sizes normal searches indirect searches. indirect search differs that entry third level page table contains pointer page descriptor rather than page descriptor itself. Entries translation tables contain control status information addition physical address information. Control bits specify write protection, limit access supervisor only, determine cachability data each memory page. Each page descriptor also user-programmable bits that appear UPA0 UPA1 signals during external access address modifier bits. global each page descriptor prevent flushing entry that page some PFLUSH instruction variants, allowing system entries remain resident during task swaps. these special PFLUSH instructions used, this user defined. MMUs automatically maintain access history information pages updating used modified status bits.
6.7.4 instructions instructions supported 68040 follows PFLUSH Allows flushing either selected entries function code logical address entire ATCs. PTEST Takes address function code searches translation tables corresponding entry, which then loaded into ATC. results search available status register often useful determining cause fault.
68040 instructions privileged only executed from supervisor mode.
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6.7.5 Transparent translation Four transparent translation registers, each instruction data accesses, have been provided 68040 allow portions logical address space transparently mapped accessed without need correponding entries resident ATC. Each register used define range logical addresses from Mbytes Gbytes with base address mask. addresses within these ranges mapped, optionally protected against user supervisor accesses write accesses. Logical addresses these areas become physical addresses memory access. transparent translation feature allows rapid movement large blocks data memory space without disturbing context on-chip ATCs incurring delays associated with translation table searches.
PREPARATION DELIVERY Packaging Microcircuits prepared delivery accordance with MIL-M-38510 standard. Certificate compliance offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 standard guarantying parameters tested temperature extremes entire temperature range. HANDLING devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical. PACKAGE MECHANICAL DATA pins
Millimeters Inches 46.863 47.625 1.845 1.875 46.863 47.625 1.845 1.875 2.3876 1.875 0.094 0.116 4.318 4.826 0.170 0.190 1.143 0.045 0.055 1.143 0.045 0.055 2.54 0.100 0.432 0.483 0.017 0.019 untinned leads (gold).
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pins CQFP cavity request)
Millimeters 3.30 0.23 0.05 0.038 0.635 typ. 33.91 0.25 0.89 0.13 63.5 0.51
Inches 0.130 .009 .002 .015 .025 typ. 1.335 .035 .005
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pins Gullwing CQFP cavity
Reduced count shown clarity, pins side
Symbol HD/HE
Millimeters 4.19 0.673 0.23 0.05 0.038 0.127 0.05 0.025 33.91 0.25 0.635 30.48 0.13 38.8 0.18 0.813 0.55 0.25 0.23
Inches 0.165 .0265 .008 .009 .002 .0015 .005 .002 .001 1.335 .025 .005 1.528 .007 .032 .008 .022 .009
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68040
ORDERING INFORMATION 10.1 MIL-STD-883 internal standard
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Note THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Note request. Note Standard process. Note request small quantity. 10.2 DESC Drawing 5962-93143
Note THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.
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68040
10.3 Detailed 68040 part list 10.3.1 Hi-REL product Commercial part number (see Note) TS68040MRB/C25 TS68040MRB/C33 TS68040MFB/C25 TS68040MFB/C33 TS68040DESC01XA TS68040DESC02XA TS68040DESC01XC TS68040DESC02XC TS68040DESC01YC TS68040DESC02YC TS68040DESC01ZA TS68040DESC01ZC TS68040DESC02ZA TS68040DESC02ZC TS68040MFB/C25 TS68040MFB/C33 TS68040MRD/T25 TS68040MRD/T33 TS68040MFD/T25 TS68040MFD/T33 Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC MIL-STD-883 MIL-STD-883 BURN BURN BURN BURN Package CQFP CQFP gold gold CQFP gold CQFP gold CQFP gullwing CQFP gullwing gold CQFP gullwing CQFP gullwing gold CQFP CQFP CQFP CQFP Temperature range (°C) Frequency (MHz) Drawing number data sheet data sheet data sheet data sheet 5962-9314301MXA 5962-9314302MXA 5962-9314301MXC 5962-9314302MXC 5962-9314301MYC 5962-9314302MYC 5962-9314301MZA 5962-9314301MZC 5962-9314302MZA 5962-9314302MZC data sheet data sheet data sheet data sheet data sheet data sheet
Note THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.
10.3.2 Standard product
Commercial part number (see Note) TS68040VR25 TS68040VR33 TS68040MR25 TS68040MR33 TS68040VF25 TS68040VF33 TS68040MF25 TS68040MF33 Norms standard standard standard standard standard standard standard standard Package CQFP CQFP CQFP CQFP Temperature range (°C) Frequency (MHz) Drawing number data sheet data sheet data sheet data sheet data sheet data sheet data sheet data sheet
Note THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Note available request.
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68040
This product manufactured THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES 38521 SAINT-EGREVE FRANCE. further information please contact THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES Route B.P. 91401 ORSAY Cedex FRANCE (33)(0) 1.69.33.00.00 (33)(0) 1.69.33.03.21. E-mail lafrique@tcs.thomson.fr
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ORDER CODE DSTS68040T/0298
Information furnished believed accurate reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES assumes responsability consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES products authorized critical components life support devices systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. 1998 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES Printed France rights reserved.
Graphic Express 01.46.55.27.24 10233 02/98

THIRD-GENERATION 32-BIT MICROPROCESSOR DESCRIPTION 68040 Thomson'

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