PCX750P/740P PowerPC750P/740P RISC MICROPROCESSOR Family Pid8t-75

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PCX750P/740P PowerPC750P/740P RISC MICROPROCESSOR Family Pid8t-75

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12.4SPECint95,8.4SPECfp95 @266Mhz (750P) w/1MB @133Mhz 13.5SPECint95, 9SPECfp95 @300Mhz (740P) MIPS 266Mhz Selectable clock dividers typical 4,2W 333Mhz, full operating conditions. Nap, doze sleep modes power savings Superscalar instructions clock cycle) 4G-Byte direct addressing range. 64-bit data 32-bit address interface. 32KB instruction data cache. independent execution units register files. Write-back write-through operations. fint 333Mhz fbus 100Mhz Compatible CMOS input output
PCX750P/740P
PowerPC750P/740P RISC MICROPROCESSOR Family Pid8t-750P/740P Specification Preliminary
Description
PCX750P PCX740P microprocessor (after named 750P/740P) low-power implementations PowerPC Reduced Instruction Computer (RISC) architecture. 750P/740P microprocessors designs superscalar, capable issuing three instructions clock cycle into independent execution units 740P/750P microprocessors uses 1,9/3,3-volts CMOS process technology maintains full interface compatibility with devices. 750P/740P provides four software controlable power-saving modes thermal assist unit management. 750P/740P microprocessors have separate 32-Kbyte, physically-addressed instruction data caches differ only that 750P features dedicated cache interface with on-chip tags. Both software bus-compatible with PowerPC603 PowerPC604 families, fully JTAG compliant. 740P microprocessor compatible with TSPC603e family.
suffix
suffix
CBGA255 CBGA360
Ceramic Ball Grid Array
CI-CGA255 CI-CGA360
Ceramic Ball Grid Array with Solder Column Interposer (SCI)
Screening
This product manufactured full compliance with CBGA upscreenings based upon ATMEL-Grenoble standards Full military temperature range (Tc=-55oC,+125oC) industrial temperature range (Tc=-40oC,+110oC) CI-CGA versions 740P 750P (TBC)
August 2000
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SUMMARY
GENERAL DESCRIPTION
SIMPLIFIED BLOCK DIAGRAM 1.1. General parameters 1.2. Features ASSIGNEMENTS 2.1. 740P package 2.2. 750P package 2.3. PINOUT LISTINGS 2.3.1. Pinout listing 740P, CBGA CI-CGA packages. 2.3.2. Pinout listing 750P, CBGA package. 2.4. Signal description 7.1.1. Mechanical Dimensions 740P CBGA package 7.1.2. Mechanical Dimensions 740P CI-CGA package 7.2. Parameters 750P 7.2.1. Mechanical Dimensions 750P CBGA package 7.2.2. Mechanical Dimensions 750P CI-CGA package CLOCK RELATIONSHIPS CHOICE SYSTEM DESIGN INFORMATION 9.1. Power Supply Filtering 9.2. Decoupling Recommendations 9.3. Connection Recommendations 9.4. Output Buffer Impedance 9.5. Pull-up Resistor Requirements
DETAILED SPECIFICATION
SCOPE APPLICABLE DOCUMENTS REQUIREMENTS 3.1. General 3.2. Design construction 3.2.1. Terminal connections 3.3. Absolute maximum rating 3.4. Recommendated operating conditions 3.5. Thermal characteristics 3.5.1. Package characteristics 3.5.2. Thermal management assistance 3.5.3. Thermal Management Information 3.6. Power consideration 3.6.1. Power management 3.6.2. Power dissipation ELECTRICAL CHARACTERISTICS 4.1. Static characteristics 4.2. Dynamic characteristics 4.2.1. Clock Specifications 4.2.2. Input Specifications 4.2.3. Output Specifications 4.2.4. Clock Specifications 4.2.5. Input Specifications 4.2.6. Output Specifications 4.2.7. IEEE 1149.1 Timing Specifications
DEFINITIONS ORDERING INFORMATION
PREPARATION DELIVERY 5.1. Packaging 5.2. Certificate compliance HANDLING PACKAGE MECHANICAL DATA 7.1. Parameters 740P
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750P/740P
750P/740P
GENERAL DESCRIPTION
SIMPLIFIED BLOCK DIAGRAM
750P targeted power systems supports following power management features-doze, nap, sleep, dynamic power management. 750P consists processor core internal combined with dedicated cache interface bus.
Instruction Fetch Branch Unit Completion
Control Unit
ICache System Unit Dispatch BHT/BTIC
GPRs FXU1 FXU2 Rename Buffers
FPRs Rename Buffers
DCache
Tags
Cache
Figure PCX750P Block Diagram
1.1. General parameters
general parameters 750P/740P following Technology 0.18 CMOS, five-layer metal size 7.56 8.79 mm2) Transistor count 6.35 million Logic design Fully-static Packages 740P: Surface mount ceramic ball grid array (CBGA) column interposer ceramic grid array CI-CGA without interface 750P: Surface mount ceramic ball grid array (CBGA) column interposer ceramic grid array CI-CGA with interface Core power supply 1.9V "100 power supply 3.3V
1.2. Except cache interface that supported PowerPC version, major features implemented 750P architecture follow:
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Level (L2) cache interface (not implemented TSPC740P)
Internal cache controller 4K-entry tags; external data SRAMs 256K, 512K, Mbyte 2-way associative cache support Copy-back write-through data cache page basis, 64-byte (256K/512K) 128-byte (1-Mbyte) sectored line size Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, pipelined (reg-reg) late-write synchronous burst SRAMs Core-to-L2 frequency divisors ÷1.5, ÷2.5, supported
Branch processing unit
Four instructions fetched clock branch processed cycle (plus resolving speculations) speculative stream execution, additional speculative stream fetch 512-entry branch history table (BHT) dynamic prediction 64-entry, 4-way associative branch target instruction cache (BTIC) minimize branch delay slots
Dispatch unit
Full hardware detection dependencies (resolved execution units) Dispatch instructions independent units (system, branch, load/store, fixed-point unit fixed-point unit floating-point) Serialization control (predispatch, postdispatch, execution serialization)
Load/store unit
cycle load store cache access (byte, half-word, word, double-word) Effective address generation Hits under misses (one outstanding miss) Single-cycle misaligned access within double word boundary Alignment, zero padding, sign extend integer register file Floating-point internal format conversion (alignment, normalization) Sequencing load/store multiples string operations Store gathering Cache instructions Big- little-endian byte addressing supported Misaligned little-endian support hardware
Fixed-point units
Fixed-point unit (FXU1)-multiply, divide, shift, rotate, arithmetic, logical Fixed-point unit (FXU2)-shift, rotate, arithmetic, logical Single-cycle arithmetic, shift, rotate, logical Multiply divide support (multi-cycle) Early multiply
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750P/740P
750P/740P
interface
Compatible with processor interface 32-bit address 64-bit data Bus-to-core frequency multipliers 3.5x, 4.5x, 5.5x, 6.5x, 7.5x supported
Decode
Register file access Forwarding control Partial instruction decode
Floating-point unit
Support IEEE-754 standard single- double-precision floating-point arithmetic cycle latency, cycle throughput, single-precision multiply-add cycle latency, cycle throughput, double-precision cycle latency, cycle throughput, double-precision multiply-add Hardware support divide Hardware support denormalized numbers Time deterministic non-IEEE mode
System unit
Executes logical instructions miscellaneous system instructions Special register transfer instructions
Cache structure
32K, 32-byte line, 8-way associative instruction cache 32K, 32-byte line, 8-way associative data cache Single-cycle cache access Pseudo-LRU replacement Copy-back write-through data cache page page basis) Supports PowerPC memory coherency modes Non-blocking instruction data cache (one outstanding miss under hits) snooping instruction cache
Memory management unit
entry, 2-way associative instruction entry, 2-way associative data Hardware reload TLBs instruction BATs data BATs Virtual memory support exabytes (252) virtual memory Real memory support gigabytes (232) physical memory
Testability
LSSD scan design JTAG interface
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Integrated power management
Low-power 1.9/3.3-volt design Three static power saving modes: doze, nap, sleep Automatic dynamic power reduction when internal functional units idle On-chip thermal sensor control logic Thermal Managment Interrupt software regulation junction temperature.
Integrated Thermal Management Assist Unit
Reliability serviceability-Parity checking cache buses
ASSIGNEMENTS 2.1. 740P package
pinout 740P, CBGA CI-CGA packages viewed from surface.
111213 141516 Scale View
Substrate Assembly Encapsulant
CBGA255
scale
Substrate Assembly Encapsulant
Figure Pinout 740P, CBGA CI-CGA Packages Viewed from Surface 6/42
750P/740P
View
CI-CGA255
750P/740P
2.2. 750P package
pinout 750P, CBGA CI-CGA packages viewed from surface.
index
1112 1516 1819
Scale
View
Substrate Assembly Encapsulant
CBGA360
scale
Substrate Assembly Encapsulant
Figure Pinout 750P, CBGA CI-BGA Packages Viewed from Surface
View
CI-CGA360
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2.3. PINOUT LISTINGS
2.3.1.Pinout listing 740P, CBGA CI-CGA packages.
Table Pinout Listing 740P, CBGA CI-CGA Packages
Signal Name A[0-31] Number C16, D13, D14, D15, D16, E13, E15, E16, F13, F14, F15, F16, G13, G15, H16, J15, P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, T10, K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, C12, E11, E14, F10, F12, G11, H10, H12, J10, J12, K11, L10, L12, M11, M14, Active High
AACK AP[0-3] ARTRY AVDD CKSTP_IN CKSTP_OUT CLK_OUT DBDIS DBWO DH[0-31]
High High
Input Input Output Output Input Output Output Input Input Input
DL[0-31]
High
DP[0-7] DRTRY
High
Input
HRESET
Input
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750P/740P
750P/740P
Table Pinout Listing 740P, CBGA CI-CGA Packages
Signal Name L1_TSTCLK L2_TSTCLK LSSD_MODE (No-Connect) OVDD J16, E10, E12, G12, G14, K12, K14, M10, M12, A13, D10, B13, A15, B16, C14, Number Active High High Input Input Input Input Input
PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TLBISYNC TRST TSIZ[0-2] TT[0-4]
High High High High High High High High
Input Input Output Output Input Input Input Input Input Input Input Output Input Input Input Input Output Output
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Table Pinout Listing 740P, CBGA CI-CGA Packages
Signal Name Number F11, G10, H11, J11, K10, Active
VOLTDET Notes:
High
Output
These test signals factory only must pulled OVdd normal machine operation. OVdd inputs supply power drivers inputs supply power processor core. Internally tied 740P CBGA package indicate power supply that low-voltage processor present. This signal power supply input. 2.3.2.Pinout listing 750P, CBGA package.
Table Pinout Listing 750P, CBGA CI-CGA Packages
Signal Name A[0-31] Number A13, H11, B13, C13, D13, F12, W12, W11, V11, W10, U10, M11, R10, Active High
AACK AP[0-3] ARTRY AVDD CKSTP_OUT CKSTP_IN CLKOUT DBDIS DBWO DH[0-31]
High High High High
Input Input Output Output Output Input Output Input Input Input
DL[0-31]
P11, V13, U12, P12, T13, W13, High U13, V10, T11, U11, V12,
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750P/740P
750P/740P
Table Pinout Listing 750P, CBGA CI-CGA Packages
Signal Name DP[0-7] DRTRY Number D10, D14, D16, E12, F10, F14, F16, G11, H10, H12, H15, J11, K10, K12, K14, K16, L11, M10, M12, M15, N11, P10, P14, P16, R12, T10, T14, L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, V14, U16, T19, N18, H14, F17, C19, D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, A19, W19, K114,K194 D12, E11, R11, Active High Input
HRESET L1_TSTCLK L2ADDR[0-16]
High High
Input Input Input Output
L2AVDD L2CE L2CLKOUTA L2CLKOUTB L2DATA[0-63]
High
Output Output Output
L2DP[0-7] L2OVDD L2SYNC_IN L2SYNC_OUT L2_TSTCLK1 L2WE L2ZZ LSSD_MODE1 (No-Connect) OVDD
High High High High High
Input Output Input Output Output Input Input
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Table Pinout Listing 750P, CBGA CI-CGA Packages
Signal Name PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TLBISYNC TRST TSIZ[0-2] TT[0-4] VOLTDET Notes: These test signals factory only must pulled OVdd normal machine operation. OVdd inputs supply power drivers inputs supply power processor core. Internally tied L2OVDD 750P CBGA package indicate power present cache interface. This signal power supply input. Caution: this different from 740P CBGA package. These pins reserved potential future additional address pins. C10, D11, B12, C12, G10, G12, J10, J12, L10, L12, N10, Number Active High High High High High High High High High Input Input Output Output Input Input Input Input Input Input Input Output Input Input Input Input Output Output Output
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750P/740P
750P/740P
2.4. Signal description
L2VDD L2AVDD ADDRESS ARBITRATION A[0-31] ADDRESS AP[0-3] L2ADDR 16-0 L2DATA 0-63 L2DP L2CE
supported 740P
CACHE ADDRESS/ DATA
ADDRESS START
L2WE L2CLK-OUT L2SYNC_OUT L2SYNC_IN L2ZZ SRESET HRESET CKSTP_IN CKSTP_OUT RSRV TBEN TLBISYNC QREQ QACK
CACHE CLOCK/CONTROL
TT[0-4] TBST TS1Z[0-2] TRANSFER ATTRIBUTE
PCX750P
INTERRUPTS RESET
AACK ADDRESS TERMINATION ARTRY DATA ARBITRATION DATA TRANSFER DBWO 0-63 DBDIS
PROCESSOR STATUS CONTROL
SYSCLK, PLL_CFG CLK_OUT
CLOCK CONTROL
JTAG:COP Factory Test
TEST INTERFACE
DATA TERMINATION
DRTRY
VDD(I:O) AVDD
Figure 750P microprocessor signal groups
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DETAILED SPECIFICATION
SCOPE
This drawing describes specific requirements microprocessor 750P, compliance with ATMEL Grenoble standard screening.
APPLICABLE DOCUMENTS
MIL-STD-883 Test methods procedures electronics. MIL-PRF-38535 appendix General specifications microcircuits.
REQUIREMENTS 3.1. General
microcircuits accordance with applicable documents specified herein.
3.2. Design construction
3.2.1. Terminal connections Depending package, terminal connections shall shown table1, table Figure
3.3. Absolute maximum rating
Table Absolute Maximum Ratings
Characteristic Core supply voltage supply voltage supply voltage supply voltage supply voltage Input voltage Storage temperature range Notes: Functional tested operating conditions given Table Absolute maximum ratings stress ratings only, functional operation maximums guaranteed. Stresses beyond those listed affect device reliability cause permanent damage device. Caution: must exceed OVdd more than 0.3V time including during power-on reset. Caution: OVdd must exceed Vdd/AVdd more than time including during power-on reset. Caution: Vdd/AVdd must exceed OVdd more than 0.4V time including during power-on reset. Caution overshoot/undershoot voltage maximum duration shown figure bis. AVdd L2AVdd OVdd L2OVdd Tstg Symbol Value -0.3 -0.3 -0.3 -0.3 (3.5) -0.3 (3.5) -0.3 Unit
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750P/740P
750P/740P
Figure shows allowable undershoot overshoot voltage 750P 740P (L2) OVdd (L2) OVdd
0.3V
1.0V
exceed tSYSCLK Figure Overshoot/Undershoot Voltage
3.4. Recommendated operating conditions Table Recommendated Operating Conditions
Characteristic Core supply voltage supply voltage supply voltage supply voltage supply voltage Input voltage Case temperature AVdd L2AVdd OVdd L2OVdd Symbol Value 3.135 3.465 3.135 3.465 OVdd to+125 Unit
Note: These recommended tested operating conditions. Proper device operation outside these conditions guaranteed.
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3.5. Thermal characteristics
3.5.1.Package characteristics
Table Package Thermal Characteristics
Characteristic CBGA CI-CGA packages thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, junction-to-lead thermal resistance (typical) CI-CGA package thermal resistance, junction-to-lead thermal resistance (typical) Symbol Value 0.03 Rating °C/W °C/W °C/W
board designer choose between several types heat sinks place 750P. There several commercially-available heat sinks 750P provided following vendors: exposed-die packaging technology, shown Table intrinsic conduction thermal resistance paths follows
junction-to-case top-of-die exposed silicon) thermal resistance
junction-to-ball thermal resistance
Figure depicts primary heat transfer path package with attached heat sink mounted printed-circuit board. Heat generated active side chip conducted through silicon, then through heat sink attach material thermal interface material), finally heat sink where removed forced-air convection. Since silicon thermal resistance quite small, first-order analysis, temperature drop silicon neglected. Thus, heat sink attach material heat sink conduction/convective thermal resistances dominant terms. External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Junction Package/Leads Printed-Circuit Board
External Resistance
Radiation
Convection
(Note internal versus external package resistance)
Figure Package with Heat Sink Mounted Printed-Circuit Board
3.5.2.Thermal management assistance 750P incorporates thermal management assist unit (TAU) composed thermal sensor, digital-to-analog converter, comparator, control logic, dedicated special-purpose registers (SPRs). Specifications thermal sensor portion found Table More information this feature given MPC750P RISC Microprocessor User's manual.
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750P/740P
750P/740P
Table Thermal Sensor Specifications
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, vTct)125
Characteristic Temperature range Comparator settling time Resolution
Unit
Notes
Notes: temperature junction temperature die. thermal assist unit's output does indicate absolute temperature, must interpreted software derive absolute junction temperature. information about calibration TAU, Motorola application note AN1800/D "programming thermal Assist Unit 750P Microprocessor This specification reflects temperature span supported design. comparator settling time value must converted into number clocks that need written into THRM3 SPR. Guaranteed design characterization.
3.5.3.Thermal Management Information This section provides thermal management information ceramic ball grid array (CBGA) package air-cooled applications. Proper thermal control design primarily dependent upon system-level design-the heat sink, airflow thermal interface material. reduce die-junction temperature, heat sinks attached package several methods-adhesive, spring clip holes printed-circuit board package, mounting clip screw assembly; Figure This spring force should exceed pounds force.
CBGA Package
Heat Sink
Heat Sink Clip
Printed-Circuit Board
Figure Package Exploded Cross-Sectional View with Several Heat Sink Options
Ultimately, final selection appropriate heat sink depends many factors, such thermal performance given velocity, spatial volume, mass, attachment method, assembly, cost.
Option
Adhesive Thermal Interface Material
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3.5.3.1. Adhesives Thermal Interface Materials
Silicone Sheet (0.006 inch) Bare Joint Floroether Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease
Specific Thermal Resistance (Kin2/W)
Contact Pressure (psi)
Figure Thermal Performance Select Thermal Interface Material
thermal interface material recommended package lid-to-heat sink interface minimize thermal contact resistance. those applications where heat sink attached spring clip mechanism, Figure shows thermal performance three thinsheet thermal-interface materials (silicone, graphite/oil, floroether oil), bare joint, joint with thermal grease function contact pressure. shown, performance these thermal interface materials improves with increasing contact pressure. thermal grease significantly reduces interface thermal resistance. That bare joint results thermal resistance approximately times greater than thermal grease joint. Heat sinks attached package means spring clip holes printed-circuit board (see Figure This spring force should exceed pounds force. Therefore, synthetic grease offers best thermal performance, considering interface pressure. board designer choose between several types thermal interface. Heat sink adhesive materials should selected based upon high conductivity, adequate mechanical strength meet equipment shock/vibration requirements.
3.5.3.2. Heat Sink Selection Example preliminary heat sink sizing, die-junction temperature expressed follows:
Where:
die-junction temperature inlet cabinet ambient temperature temperature rise within computer cabinet junction-to-case thermal resistance adhesive interface material thermal resistance heat sink base-to-ambient thermal resistance power dissipated device During operation die-junction temperatures (Tj) should maintained less than value specified Table temperature cooling component greatly depends upon ambient inlet temperature temperature rise within electronic cabinet. electronic cabinet inlet-air temperature (Ta) range from temperature rise within cabinet (Tr) range thermal resistance thermal interface material (int) typically about Assuming CBGA package 2.2, power consumption (Pd) watts, following expression obtained:
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750P/740P
750P/740P
Die-junction temperature: (2.2 Thermalloy heat sink #2328B, heat sink-to-ambient thermal resistance (sa) versus airflow velocity shown Figure
Thermalloy #2328B Pin-fin Heat Sink
Heat Sink Thermal Resistance (?C/W)
Approach Velocity (m/s)
Figure Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Assuming velocity m/s, have effective thus (2.2 +1.0 resulting die-junction temperature approximately which well within maximum operating temperature component. Other heat sinks offered Chip Coolers, IERC, Thermalloy, Wakefield Engineering, Aavid Engineering offer different heat sinkto-ambient thermal resistances, need flow. Though junction-to-ambient heat sink-to-ambient thermal resistances common figure-of-merit used comparing thermal performance various microelectronic packaging technologies, should exercise caution when only using this metric determining thermal management because single parameter adequately describe three-dimensional heat flow. final die-junction operating temperature, only function component-level thermal resistance, system-level design operating conditions. addition component's power consumption, number factors affect final operating die-junction temperature-airflow, board population (local heat flux adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system temperature rise, altitude, etc. complexity many variations system-level boundary conditions today's microelectronic equipment, combined effects heat transfer mechanisms (radiation, convection conduction) vary widely. these reasons, recommend using conjugate heat transfer models board, well system-level designs. expedite system-level thermal analysis, several "compact" thermal-package models available within FLOTHERM®. These available upon request.
3.6. Power consideration
3.6.1.Power management 750P provides four power modes, selectable setting appropriate control bits HIDO registers. four power modes follows Full-power: This default power state 750P. 750P fully powered internal functional units operating full processor clock speed. dynamic power management mode enabled, functional units that idle will automatically enter low-power state without affecting performance, software execution, external hardware.
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Doze: functional units 750P disabled except time base/decrementer registers snooping logic. When processor doze mode, external asynchronous interrupt, system management interrupt, decrementer exception, hard soft reset, machine check brings 750P into full-power state. 750P doze mode maintains fully powered state locked system external clock input (SYSCLK) transition full-power state takes only processor clock cycles. Nap: mode further reduces power consumption disabling snooping, leaving only time base register powerred state. 750P returns full-power state upon receipt external asynchronous interrupt, system management interrupt, decrementer exception, hard soft reset, machine check input (MCP). return full-power state from state takes only processor clock cycles. When processor mode, QACK negated, processor doze mode support snooping. Sleep: Sleep mode minimizes power consumption disabling internal functional units, after which external system logic disable SUSCLK. Returning 750P full-power state requires enabling SYSCLK, followed assertion external asynchronous interrupt, system management interrupt, hard soft reset, machine check input (MCP) signal after time required relock PPL. 3.6.2.Power dissipation
Table Power Consumption
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, -55Tc<125°C
Processor (CPU) Frequency Full-On Mode Typical Maximum Doze Mode Maximum Mode Maximum Sleep Mode Maximum 2.50 2.65 2.85
Unit
Notes
Sleep Mode-PLL Disabled Typical Maximum
Notes: These values apply valid ratios. values include Supply Power (OVdd L2OVdd) PLL/DLL supply power (AVdd L2AVdd). OVdd L2OVdd power system dependent, typically <10% power. Worst case power consumption AVdd L2AVdd Maximum power measured 2.0V Typical power average value measured AVdd L2AVdd 1.9V, OVdd L2OVdd 3.3V system executing typical applications benchmark sequences. Full-On mode measured using worst-case instruction sequence.
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750P/740P
750P/740P
ELECTRICAL CHARACTERISTICS 4.1. Static characteristics
Table Electrical Specifications
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, -55v
Characteristic Input high voltage (all inputs except SYSCLK) Input voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input voltage Input leakage current, OVdd Hi-Z (off-state) leakage current, OVdd Output high voltage, Output voltage, Capacitance,
Symbol CVIH CVIL ITSI
3.465 3.465
Unit
Notes
Notes: signals, reference OVdd while L2OVdd reference signals. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) IEEE 1149.1 boundary scan (JTAG) signals. Capacitance periodically sampled rather than 100% tested. leakage measured nominal OVdd Vdd, both OVdd must vary same direction (for example, both OVdd vary either -5%).
4.2. Dynamic characteristics
After fabrication, parts sorted maximum processor core frequency shown Section 4.2.1.,"Clock Specifications" tested conformance specifications that frequency. These specifications 275, 300, processor core frequencies. processor core frequency determined (SYSCLK) frequency settings PLL_CFG[0-3] signals. Parts sold maximum processor core frequency.
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4.2.1.Clock Specifications Table provides clock timing specifications defined Figure
Table Clock Timing Specifications
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, -55v
Characteristic
"150
"150
"150
Unit
Notes
Processor frequency frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise fall time SYSCLK duty cycle measured 1.4V SYSCLK jitter Internal relock time
Notes: Caution: SYSCLK frequency PLL_CFG[0-3] settings must chosen such that resulting SYSCLK (bus) frequency, (core) frequency, (VCO) frequency exceed their respective maximum minimum operating frequencies. Refer PLL_CFG[0-3] signal description Table "PLL Configuration," valid PLL_CFG[0-3] settings Rise fall times SYSCLK input measured from 2.4V. Timing guaranteed design characterization. total input jitter (short term long term combined) must under "150 Relock timing guaranteed design characterization. PLL-relock time maximum amount time required lock after stable SYSCLK reached during power-on reset sequence. This specification also applies when been disabled subsequently re-enabled during sleep mode. Also note that HRESET must held asserted minimum clocks after PLL-relock time during power-on reset sequence.
Figure provides SYSCLK input timing diagram.
CVIH
SYSCLK
CVIL
Midpoint Voltage (1.4V)
Figure SYSCLK Input Timing Diagram 22/42
750P/740P
750P/740P
4.2.2.60x Input Specifications Table provides input timing specifications 750P defined Figure Figure Input timing specifications provided Section 4.2.5., Input Specifications".
Table Input Timing Specifications1
=AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, -55v Tct125
Characteristic
275, 300,
Unit
Notes
Address/Data/Transfer Attribute Inputs Valid SYSCLK (Input Setup) Other Inputs Valid SYSCLK (Input Setup) Mode select input setup HRESET (DRTRY, TLBISYNC) SYSCLK Address/Data/Transfer Attribute Inputs Invalid (Input Hold) SYSCLK Other Inputs Invalid (Input Hold) HRESET mode select input hold (DRTRY, TLBISYNC)
tsysclk
4,5,6,7
4,6,7
Notes: input specifications measured from level (0.8 2.0V) signal question 1.4V rising edge input SYSCLK. Input output timings measured pin. Address/Data/Transfer Attribute inputs composed following-A[0-31], AP[0-3], TT[0-4], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. other signal inputs composed following-TS, ABB, DBB, ARTRY, AACK, DBG, DBWO, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. setup hold time with respect rising edge HRESET (see Figure tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. Guaranteed design characterization. This specification configuration mode select only. Also note that HRESET must held asserted minimum clocks after re-lock time during power-on reset sequence.
Figure provides input timing diagram 750P.
SYSCLK
INPUTS
Midpoint Voltage (1.4V)
Figure Input Timing Diagram
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Figure provides mode select input timing diagram 750P.
HRESET
MODE PINS 2.0V
Figure Mode Select Input Timing Diagram
4.2.3.60x Output Specifications Table provides output timing specifications 750P defined Figure Output timing specifications provided Section 4.2.6. Output Specifications."
Table Output Timing Specifications1
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, Tct125 pF(2)
Characteristic
275, 300,
Unit
Notes
SYSCLK Output Driven (Output Enable Time) SYSCLK Output Valid (TS, ABB, ARTRY, DBB) SYSCLK other Outputs Valid (all except ABB, ARTRY, DBB) SYSCLK Output Invalid (Output Hold) SYSCLK Output High Impedance (all except ABB, ARTRY, DBB) SYSCLK ABB, High Impedance after precharge SYSCLK ARTRY High Impedance before precharge
tsysclk
4,6,8
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750P/740P
750P/740P
Table Output Timing Specifications1
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, Tct125 pF(2)
SYSCLK ARTRY Precharge Enable 0.2*tsysclk +1.0
3,4,7
Maximum Delay ARTRY Precharge SYSCLK ARTRY High Impedance After Precharge
tsysclk tsysclk
4,7,8
Notes: output specifications measured from 1.4V rising edge SYSCLK level (0.8 signal question. Both input output timing measured pin. maximum timing specifications assume This minimum parameter assumes tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration parameter question. Output signal transitions from 2.0V OVdd 0.8V. Nominal precharge width tsysclk. Nominal precharge width ARTRY tsysclk. Guaranteed design characterization.
SYSCLK
OUTPUTS (Except ABB, ARTRY, DBB)
ABB,
ARTRY
Midpoint Voltage (1.4V)
Figure Output Timing Diagram
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4.2.4.L2 Clock Specifications L2CLK frequency programmed Configuration Register (L2CR[4:6] core-to-L2 divisor ratio. Table example core frequencies various divisors. Table provides potential range L2CLK output timing specifications defined Figure minimum L2CLK frequency Table specified maximum delay internal DLL. variable-tap introduces full clock period delay L2CLKOUTA, CLKOUTB, L2SYNC signals that returning SYNC_OUT signals that returning L2SYNC_IN signal phase aligned with next core clock (divided divisor ratio). choose core-to-L2 divisor which results frequency below this minimum, L2CLKOUT signals provided SRAM clocking will phase aligned with PCX750P core clock SRAMs. maximum L2CLK frequency shown Table core frequency divided one. Very SRAM designs will able operate this mode. Most designs will select greater core-to-L2 divisor provide longer L2CLK period read write access SRAMs. maximum L2CLK frequency application PCX750P will function timings 750P, timings SRAM, loading, printed circuit board trace length. ATMEL-Grenoble similarly limited system constraints cannot perform tests interface socketed part functional tester maximum frequencies Table Therefore functional operation timing information tested core-toL2 divisors greater. input output signals latched enabled respectively internal L2CLK (which SYSCLK multiplied core frequency divided down L2CLK frequency). other words, timings Table Table entirely independent L2SYNC_IN. closed loop system, where L2SYNC_IN driven through board trace L2SYNC_OUT, L2SYNC_IN only controls output phase L2CLKOUTA L2CLKOUTB which used latch enable darta SRAMs. However, since closed loop system L2SYNC_IN held phase alignment with internal L2CLK, signals Table Table referenced this signal rather than not-externally-visible internal L2CLK. During manufacturing test, these times actually measured relative SYSCLK.
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750P/740P
750P/740P
Table L2CLK Output Timing Specifications
recommended operating conditions (see Table
Characteristic
12.5 12.5
12.5 12.5
12.5 12.5 Unit L2CLK Notes
L2CLK frequency L2CLK cycle time L2CLK duty cycle Internal DLL-relock time capture window L2CLKOUT output-to-output skew L2CLKOUT output jitter
Notes: L2CLK outputs L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUTC, L2CLK_OUTD L2SYNC_OUT pins. L2CLK frequency core frequency settings must chosen such that resulting L2CLK frequency core frequency exceed their respective maximum minimum operating frequencies. maximum L2LCK frequency will system dependent. L2CLK_OUTA L2CLK_OUTB must have equal loading. nominal duty cycle L2CLK measured midpoint voltage. re-lock time specified terms L2CLKs. number table must multiplied period L2CLK compute actual time duration nanoseconds. Re-lock timing guaranteed design characterization. L2CR[L2SL] should L2CLK frequencies less than MHz. This adds more delay each DLL. Allowable skew between L2SYNC_OUT L2SYNC_IN. minimum skew value allows several taps negative adjustment without rolling over maximum tap. Exceptionally short paths from L2SYNC_OUT L2SYNC_IN 750P been observed result missing L2CLKOUT pulses L2CLKOUT pulses incorrect duty cycle. Guaranteed design tested. This output jitter number represents maximum delay forward back from current phase comparator seeks minimize phase difference between L2SYNC_IN internal L2CLK. This number must comprehended timing analysis. input jitter SYSCLK affects L2CLKOUT address/data/control signals equally therefore already comprehended timing does have considered timing analysis.
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L2CLK_OUT timing diagram shown Figure
Single-Ended Clock Mode
L2CLK_OUTA
L2CLK_OUTB
L2SYNC_OUT
Midpoint Voltage (L2OVdd/2)
Differential Clock Mode L2OVdd L2CLK_OUTB
L2CLK_OUTA
L2SYNC_OUT
Midpoint Voltage (L2OVdd/2)
Figure L2CLK_OUT Output Timing Diagram
Table shows input timing diagrams 750P.
L2SYNC_IN
INPUTS
Midpoint Voltage (1.4V)
Figure Input Timing Diagrams
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750P/740P
750P/740P
4.2.5.L2 Input Specifications input interface timing specifications found Table
Table Input Interface Timing Specifications1
AVdd L2AVdd "100 OVdd L2OVdd Vdc, Vdc, -55v t125
Characteristic
Processor Frequency 275-333
Unit
Notes
29,30
L2SYNC_IN rise fall time Data parity input setup L2SYNC_IN L2SYNC_IN data parity input hold
Notes: input specifications measured from level (0.8V 2.0V) signal question midpoint voltage rising edge input L2SYNC_IN. Input timings measured pins (see Figure 14). Rise fall times L2SYNC_IN input measured from 2.4V.
4.2.6.L2 Output Specifications Table provides output interface timing specifications 750P defined Figure
Table Output Interface Timing Specifications1
AVdd L2AVdd "100 OVdd L2OVdd =3.3 Vdc, Vdc, t125 pF(3)
Characteristic
L2CR[14-15] equivalent 1.25
1,45
Unit
Notes
1,75
L2SYNC_IN output valid L2SYNC_IN output hold L2SYNC_IN high impedance
0.75
Notes: outputs measured from midpoint voltage rising edge L2SYNC_IN level (0.8V 2.0V) signal question. output timings measured pins. 2.The outputs valid both single-ended differential L2CLK modes. flow-thru pipelined reg-reg synchronous burst RAMs, L2CR[14-15] recommended. pipelined delay-write synchronous burst SRAMs, L2CR[14-15] recommended. maximum timing specifications assume This measurement assumes Reserved future use.
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Figure shows output timing diagrams 750P.
L2SYNC_IN
OUTPUTS
L2DATA
Midpoint Voltage (1.4V)
Figure Output Timing Diagrams
4.2.7.IEEE 1149.1 Timing Specifications Table provides IEEE 1149.1 (JTAG) timing specifications defined Figure Figure Figure Figure
Table JTAG Timing Specifications (Independent SYSCLK)
AVdd L2AVdd "100 mV,OVdd=L2OVdd=3.3 Vdc, Vdc, -55tTc<125
Characteristic frequency operation
33.3
Unit
Notes
cycle time clock pulse width measured 1.4V rise fall times Specification obsolete, intentionally omitted TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time output data valid output high impedance TMS, data setup time
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750P/740P
750P/740P
TMS, data hold time data valid high impedance
Notes: TRST asynchronous level sensitive signal. setup time test purposes only. Non-JTAG signal input timing with respect TCK. Non-JTAG signal output timing with respect TCK. Guaranteed design characterization.
Figure provides JTAG clock input timing diagram.
Midpoint Voltage
Figure JTAG Clock Input Timing Diagram
Figure provides TRST timing diagram.
TRST
Figure TRST Timing Diagram
Figure provides boundary-scan timing diagram.
DATA INPUTS
INPUT DATA VALID
DATA OUTPUTS
OUTPUT DATA VALID
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
Figure Boundary-Scan Timing Diagram
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Figure provides test access port timing diagram.
TDI,
INPUT DATA VALID
OUTPUT DATA VALID
OUTPUT DATA VALID
Figure Test Access Port Timing Diagram
PREPARATION DELIVERY 5.1. Packaging
Microcircuits prepared delivery accordance with MIL-PRF-38535
5.2. Certificate compliance
offers certificate compliances with each shipment parts, affirming products compliance either with MIL-PRF-883 guarantiyng parameters tested temperature extremes entire temperature range.
HANDLING
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect static buildup. However, following handling practices recommended: Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical. CI-CGA packages, specific tray take care highest heigth package compared with normal CBGA.
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750P/740P
750P/740P
PACKAGE MECHANICAL DATA 7.1. Parameters 740P
package parameters provided following list. package types 255-lead CBGA CI-CGA
Package outline Interconnects Pitch
Minimum module height Maximum module height Ball column diameter
ball array 1.27 mil)
2.45 (CBGA) 3,45 (CI-CGA) 3.00 (CBGA) 4.00 (CI-CGA 0.89 mil)
7.1.1.Mechanical Dimensions 740P CBGA package
Figure provides mechanical dimensions bottom surface nomenclature 740P, CBGA package.
CORNER
0.15
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. SIDE CORNER INDEX METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE CORNER DESIGNATED WITH BALL MISSING FROM ARRAY.
MILLIMETERS
INCHES
21.000 1.10
0.827 0.035 0.043
21.000 2.45
0.827 0.118 0.037
3.000 0.096
0.820 0.930 0.032
1.270
0.050 0.039
0.790 0.990 0.031
255X
0.15
0.635 2.00
0.025 0.074 0.327 0.354 0.335 0.362
Figure Mechanical Dimensions Bottom Surface Nomenclature 740P (CBGA)
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7.1.2.Mechanical Dimensions 740P CI-CGA package
Figure provides mechanical dimensions bottom surface nomenclature 740P, CI-CGA package
NOTES
DIMENSIONING TOLERANCING ASME Y14.5M 1994. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS 21.000 21.000 3.84 0.790 0.990 1.270 1.545 1.695 0.635 3.02 0.10 0.25 0.35
Figure Mechanical Dimensions Bottom Surface Nomenclature 740P (CI-CGA)
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750P/740P
750P/740P
7.2. Parameters 750P
package parameters provided following list. package type 360-lead CBGA CI-CGA.
Package outline Interconnects Pitch
Minimum module height Maximum module height Ball column diameter
ball array 1.27 mil)
2.65 (CBGA) 3,65 (CI-CGA) 3.20 (CBGA) 4,20 (CI-CGA) 0.89 mil)
7.2.1.Mechanical Dimensions 750P CBGA package Figure provides mechanical dimensions bottom surface nomenclature 750P, CBGA package.
INDEX
0.15 0.35
NOTES: Dimensioning tolerancing ASME Y14.5M-1994 Dimensions millimeters. side corner index metalized feature with various shapes. Bottom side corner designated with ball missing from array. Dimension maximum solder ball diameter measured parallel datum define area occupied underfill. Actual size this area smaller than shown. minimum clearance from package edge chip capacitors.
VIEW
Capacitors present devices. Caution must taken short.
Millimeters 2.72 1.10 0.82 0.82 25.00 22.86 2.75 6.00 25.00 22.86 3.00 8.00 1.27 14.3 11.00 12.5 9.00 3.20 1.00 1.30 0.93
0.15
360X
BOTTOM VIEW
Figure Mechanical Dimensions Bottom Surface Nomenclature 750P
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7.2.2.Mechanical Dimensions 750P CI-CGA package
Figure provides mechanical dimensions bottom surface nomenclature 750P, CI-CGA package.
INDEX
0.15 0.35
NOTES: Dimensioningand tolerancing ASME Y14.5M-1994 Dimensions millimeters. side corner index metalized feature with various shapes. Bottom side corner designated with ball missing from array. Dimension maximum solder ball diameter measured parallel datum define area occupied underfill. Actual size this area smaller than shown. minimum clearance from package edge chip capacitors.
VIEW
Capacitors present devices. Caution must taken short.
Millimeters
0.15
3.72 1.545 1.10 0.82 0.82 25.00 22.86 2.75 6.00 25.00 22.86 3.00 8.00 1.27
4.20 1.695 1.30 0.93
12.5 9.00
360X
14.3 11.00
Figure Mechanical Dimensions Bottom Surface Nomenclature 750P (CI-CGA)
CLOCK RELATIONSHIPS CHOICE
750P's configured PLL_CFG[0-3] signals. given SYSCLK (bus) frequency, configuration signals internal frequency operation. configuration 750P shown Table nominal frequencies. Table provides sample core-to-L2 frequencies.
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750P/740P
750P/740P
Table 750P Microprocessor Configuration
PLL_CFG [0-3] Bus-toCore Multiplier 1000 Sample Bus-to-Core Frequency (VCO Frequency MHz) Core-to Multiplier 33.3 66.6 83.3 (500) (525) (533) (600) (500) (600) (650) (560) (500) (533) (600) (640) (666) (600) (660) (585) (666) (600)
1110
3.5x
1010
0111
4.5x
1011
1001
5.5x
1101
0101
6.5x
0010
0001
7.5x
1100
0011 1111
off/bypass
off, SYSCLK clocks core circuitry directly, bus-to-core implied off, core clocking occurs
Notes: PLL_CFG[0-3] settings listed reserved. sample bus-to-core frequencies shown reference only. Some configurations select bus, core, frequencies which useful, supported, tested PCX750P; Section 4.2.1. "Clock Specifications," valid SYSCLK frequencies. PLL-bypass mode, SYSCLK input signal clocks internal processor directly, disabled, mode mode operation. This mode intended factory only. Note: timing specifications given this document apply PLL-bypass mode. clock-off mode, clocking occurs inside 750P regardless SYSCLK input.
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750P generates clock external synchronous data SRAMs dividing core clock frequency 750P. divided-down clock then phase-adjusted on-chip delay-lock-loop (DLL) circuit should routed from 750P external RAMs. separate clock output, L2SYNC_OUT sent half distance SRAMs then returned input L2SYNC_OUT sent half distance SRAMs then returned input L2SYNC_IN that rising-edge clock seen external RAMs aligned clocking internal latches interface. core-to-L2 frequency divisor selected through L2CLK bits L2CR register. Generally, divisor must chosen according frequency supported external RAMs, frequency 750P core, phase adjustment range that supports. Table shows various example clock frequencies that obtained given core frequencies.
Table Sample Core-to-L2 Frequencies
Core Frequency 183.3 137.5 91.66
Note: core frequencies reference only. Some configurations select core frequencies which useful, supported, tested 750P; Section 4.2.4. Clock Specifications," valid L2CLK frequencies. L2CR[L2SL] should L2CLK frequencies less than MHz.
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750P/740P
750P/740P
SYSTEM DESIGN INFORMATION 9.1. Power Supply Filtering
AVdd L2AVdd power signals provided 750P provide power clock generation phase-locked loop cache delay-locked loop respectively. ensure stability internal clock, power supplied AVdd input signal should filtered using circuit similar shown Figure circuit should placed close possible AVdd ensure filters much noise possible. identical separate circuit should placed close possible L2AVdd pin.
AVdd L2AVdd)
Figure Power Supply Filter Circuit
9.2. Decoupling Recommendations
750P's dynamic power management feature, large address data buses, high operating frequencies, 750P generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components 750P system, 750P itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVdd (and L2OVdd CBGA) 750P. also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, power planes PCB, utilizing short traces minimize inductance. These capacitors should vary value from provide both high- low-frequency filtering, should placed close possible their associated OVdd pins. Suggested values pins-220 (ceramic), 0.01 (ceramic), (ceramic). Suggested values OVdd pins-0.01 (ceramic), (ceramic), (tantalum). Only (surface mount technology) capacitors should used minimize lead inductance. addition, recommended that there several bulk storage capacitors distributed around PCB, feeding OVdd planes, enable quick recharging smaller chip capacitors. These bulk capacitors should have (equivalent series resistance) rating ensure quick response time necessary. They should also connected power ground planes through vias minimize inductance. Suggested bulk capacitors-100 (AVX tantalum) (AVX tantalum).
9.3. Connection Recommendations
ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied Vdd. Unused active high inputs should connected GND. (no-connect) signals must remain unconnected. Power ground connections must made external Vdd, OVdd, pins 750P. External clock routing should ensure that rising-edge clock coincident input SRAMs L2SYNC_IN input 750P. L2CLKOUTA network could used only, L2CLKOUTB network could also used depending loading, frequency, number SRAMs.
9.4. Output Buffer Impedance
750P drivers were characterized over process, voltage, temperature. measure external resistor connected chip pad, either OVdd OGND. Then, value such resistor varied until voltage OVdd/2; Figure output impedance actually average components, resistances pull-up pull-down devices. When Data held low, closed (SW2 open), trimmed until OVdd/2. then becomes resistance pull-down devices. When Data held high, closed (SW1 open), trimmed until OVdd/2. then becomes resistance pull-up devices. With properly designed driver close each other value. Then RN)/2.
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OVdd
Data
OGND
Figure Driver Impedance Measurement
Table summarizes signal impedance results. driver impedance values were derived simulation 65°C. process varies, output impedance will reduced several ohms.
Table Impedance Characteristics
2.6V, OVdd 3.3V,
Process
Symbol
Unit Ohms
9.5. Pull-up Resistor Requirements
750P requires high-resistive (weak: pull-up resistors several control signals interface maintain control signals negated state after they have been actively negated released PCX750P other masters. These signals ABB, DBB, ARTRY. addition, 750P open-drain style output that requires pull-up resistors (weak stronger: KW-10 used system. This signal CKSTP_OUT. During inactive periods bus, address transfer attributes driven master float high-impedance state relatively long periods time. Since 750P must continually monitor these signals snooping, this float condition cause excessive power draw input receivers 750P other receivers system. recommended that these signals pulled through weak pull-up resistors restored some manner system. snooped address transfer attribute inputs A[0-31], AP[0-3], TT[0-4], TBST, GBL. data input receivers normally turned when read operation progress require pull-up resistors data bus. Other data receivers system, however, require pullups, that those signals otherwise driven system during inactive periods. data signals
DH[0-31], DL[0-31], DP[0-7].
address data parity used system, respective parity checking disabled through HID0, input receivers those pins disabled, those pins require pull-up resistors should left unconnected system. parity generation disabled through HID0, then parity checking should also disabled through HID0, parity pins left unconnected system. pull-up resistors normally required interface.
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750P/740P
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DEFINITIONS Datasheet status Objective specification This datasheet contains target goal specification discussion with customer application validation. This datasheet contains target goal specification product development. This datasheet contains preliminary data. Additional data published later could include simulation result. This datasheet contains also characterization results. This datasheet contains final product specification. Limiting values Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. ATMEL-Grenoble customers using selling these products such applications their risk agree fully indemnify ATMEL-Grenoble damages resulting from such improper sale. Validity Before design phase.
Target specification Preliminary specification site
Valid during design phase. Valid before characterization phase. Valid before industrialization phase. Valid production purpose.
Preliminary specification site Product specification
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ORDERING INFORMATION PCX750P Revision level Rev.2.2 Type (PCX750P prototype) divider confirmed) L:Any valid configuration
Temperature range -55, +125 -40, +110
internal processor speed Package CBGA CI-CGA
Screening level Upscreening Test
availability different versions, contact your Atmel-Grenoble sale office
Information furnished believed accurate reliable. However Atmel-Grenoble assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Atmel-Grenoble. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. AtmelGrenoble products authorized critical components life support devices systems without express written approval from Atmel-Grenoble.
2000 Atmel-Grenoble- Printed France rights reserved.
This product manufactured Atmel-Grenoble- 38521 SAINT-EGREVE FRANCE. further information please contact Atmel-Grenoble Route B.P. 91401 ORSAY Cedex FRANCE Phone (0)1 (0)1
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750P/740P

PCX750P/740P PowerPC750P/740P RISC MICROPROCESSOR Family Pid8t-75

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