High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Block

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28F008SA-L 8-MBIT MBIT FLASHFILE MEMOR
High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Low-Voltage Operation Extended Cycling Capability Block Erase Cycles Block Erase Cycles Chip Automated Byte Write Block Erase Command User Interface Status Register System Performance Enhancements Status Output Erase Suspend Capability
High-Performance Read Maximum Access Time Deep Power-Down Mode Typical SRAM-Compatible Write Interface Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry Standard Packaging 40-Lead TSOP 44-Lead PSOP ETOX Nonvolatile Flash Technology Byte Write Block Erase
Intel's 28F008SA-L Mbit FlashFile Memory highest density nonvolatile read write solution solidstate storage 28F008SA-L's extended cycling symmetrically-blocked architecture fast access time write automation very power consumption provide more reliable lower power lighter weight higher performance alternative traditional rotating disk technology 28F008SA-L brings capabilities portable computing Application operating system software stored resident flash memory arrays provide instant-on rapid execute-in-place protection from obsolescence through in-system software updates Resident software also extends system battery life increases reliability reducing disk drive accesses high-density data acquisition applications 28F008SA-L offers more cost-effective reliable alternative SRAM battery Traditional high-density embedded applications such telecommunications take advantage 28F008SA-L's nonvolatility blocking minimal system code requirements flexible firmware modular software designs 28F008SA-L offered 40-lead TSOP (standard reverse) 44-lead PSOP packages assignments simplify board layout when integrating multiple devices flash memory array subsystem This device uses integrated Command User Interface state machine simplified block erasure byte write 28F008SA-L memory consists separately erasable 64-Kbyte blocks Intel's 28F008SA-L employs advanced CMOS circuitry systems requiring power consumption noise immunity access time provides superior performance when compared with magnetic storage media deep power-down mode lowers power consumption typical thru crucial portable computing handheld instrumentation other low-power applications power control input also provides absolute data protection during system power-up down Manufactured Intel's micron ETOX process 28F008SA-L provides highest levels quality reliability cost-effectiveness
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Other brands names property their respective owners Information this document provided connection with Intel products Intel assumes liability whatsoever including infringement patent copyright sale Intel products except provided Intel's Terms Conditions Sale such products Intel retains right make changes these specifications time without notice Microcomputer Products have minor variations this specification known errata
COPYRIGHT
INTEL CORPORATION 1995
December 1995
Order Number 290435-005
28F008SA-L
Status Register indicates status when successfully completes desired byte write block erase operation output gives additional indicator activity providing capability both hardware signal status (versus software polling) status masking (interrupt masking background erase example) Status polling using minimizes both overhead system power consumption When indicates that performing block erase byte write operation high indicates that ready commands block erase suspended device deep powerdown mode Maximum access time (tACC) over commercial temperature range over supply voltage range active current (CMOS Read) typical maximum When pins CMOS Standby mode enabled Deep Powerdown mode enabled when minimizing power consumption providing write protection current deep powerdown typical Reset time required from switching high until outputs valid read attempts Equivalently device wake time from high until writes Command User Interface recognized 28F008SA-L With reset Status Register cleared
PRODUCT OVERVIEW
28F008SA-L high-performance 8-Mbit 608-bit) memory organized Mbyte bytes) bits each Sixteen 64-Kbyte 536-byte) blocks included 28F008SA-L memory shown Figure this specification block erase operation erases sixteen blocks memory typically seconds independent remaining blocks Each block independently erased written cycles Erase Suspend mode allows system software suspend block erase read data execute code from other block 28F008SA-L 28F008SA-L available 40-lead TSOP (Thin Small Outline Package thick) 44lead PSOP (Plastic Small Outline) packages Pinouts shown Figures this specification Command User Interface serves interface between microprocessor microcontroller internal operation 28F008SA-L Byte Write Block Erase Automation allow byte write block erase operations executed using two-write command sequence Command User Interface internal Write State Machine (WSM) automatically executes algorithms timings necessary byte write block erase operations including verifications thereby unburdening microprocessor microcontroller Writing memory data performed byte increments typically within byte write block erase currents typical maximum byte write block erase voltage
28F008SA-L
Figure Block Diagram
290435-
28F008SA-L
Table Description Symbol -A19 -DQ7 Type INPUT INPUT OUTPUT Name Function ADDRESS INPUTS memory addresses Addresses internally latched during write cycle DATA INPUT OUTPUTS Inputs data commands during Command User Interface write cycles outputs data during memory array Status Register Identifier read cycles data pins active high float tri-state when chip deselected outputs disabled Data internally latched during write cycle CHIP ENABLE Activates device's control logic input buffers decoders sense amplifiers active high deselects memory device reduces power consumption standby levels RESET DEEP POWERDOWN Puts device deep powerdown mode active high gates normal operation also locks block erase byte write operations when active providing data protection during power transitions active resets internal automation Exit from Deep Powerdown sets device read-array mode OUTPUT ENABLE Gates device's outputs through data buffers during read cycle active WRITE ENABLE Controls writes Command User Interface array blocks active Addresses data latched rising edge pulse READY BUSY Indicates status internal Write State Machine When indicates that performing block erase byte write operation high indicates that ready commands block erase suspended device deep powerdown mode always active does float tri-state when chip deselected data outputs disabled BLOCK ERASE BYTE WRITE POWER SUPPLY erasing blocks array writing bytes each block NOTE With VPPLMAX memory contents cannot altered DEVICE POWER SUPPLY 10%) GROUND
INPUT
INPUT
INPUT INPUT
OUTPUT
28F008SA-L
Standard Pinout
290435
Reverse Pinout
290435
Figure TSOP Lead Configurations
28F008SA-L
Figure TSOP Serpentine Layout
NOTE Connect pins each device common power supply outputs leave inputs disconnected
290435-
28F008SA-L
290435
Figure PSOP Lead Configuration
290435
Figure 28F008SA-L Array Interface Intel3 80L186EB Embedded Microprocessor
28F008SA-L
PRINCIPLES OPERATION
FFFFF
28F008SA-L includes on-chip write automation manage write erase functions Write State Machine allows 100% TTL-level control inputs fixed power supplies during block erasure byte write minimal processor overhead with RAM-like interface timings After initial device powerup after return from deep powerdown mode (see Operations) 28F008SA-L functions read-only memory Manipulation external memory-control pins allow array read standby output disable operations Both Status Register intelligent identifiers also accessed through Command User Interface when VPPL This same subset operations also available when high voltage applied addition high voltage enables successful block erasure byte writing device functions associated with altering memory contents byte write block erase status intelligent identifier accessed Command User Interface verified thru Status Register Commands written using standard microprocessor write timings Command User Interface contents serve input which controls block erase byte write circuitry Write cycles also internally latch addresses data needed byte write block erase operations With appropriate command written register standard microprocessor read timings output array data access Intelligent Identifier codes output byte write block erase status verification Interface software initiate poll progress internal byte write block erase stored 28F008SA-L blocks This code copied executed from system during actual flash memory update After successful completion byte write block erase code data reads from 28F008SA-L again possible Read Array command Erase suspend resume capability allows system software suspend block erase read data execute code from other block
F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000
64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-byte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block
Figure Memory
Command User Interface Write Automation
on-chip state machine controls block erase byte write freeing system processor other tasks After receiving Erase Setup Erase Confirm commands state machine controls block pre-conditioning erase returning progress Status Register output Byte write similarly controlled after destination address expected data supplied program erase algorithms past Intel flash memories regulated state machine including pulse repetition where required internal verification margining data
28F008SA-L
first task write appropriate read mode command Command User Interface (array Intelligent Identifier Status Register) 28F008SA-L automatically resets Read Array mode upon initial device powerup after exit from deep powerdown 28F008SA-L four control pins which must logically active obtain data outputs Chip Enable device selection control when active enables selected memory device Output Enable data input output (DQ0 -DQ7) direction control when active drives data from selected memory onto must also Figure illustrates read cycle waveforms
Data Protection
Depending application system designer choose make power supply switchable (available only when memory byte writes block erases required) hardwired VPPH When VPPL memory contents cannot altered 28F008SA-L Command User Interface architecture provides protection from unwanted byte write block erase operations even when high voltage applied Additionally functions disabled whenever below write lockout voltage VLKO when 28F008SA-L accommodates either design practice encourages optimization processor-memory interface two-step byte write block erase Command User Interface write sequence provides additional software write protection
Output Disable
With logic-high level (VIH) device outputs disabled Output pins (DQ0 -DQ7) placed high-impedance state
OPERATION
Flash memory reads erases writes in-system local cycles from flash memory conform standard microprocessor cycles
Standby
logic-high level (VIH) places 28F008SA-L standby mode Standby operation disables much 28F008SA-L's circuitry substantially reduces device power consumption outputs (DQ0 -DQ7) placed high-impedence state independent status 28F008SA-L deselected during block erase byte write device will continue functioning consuming normal active power until operation completes
Read
28F008SA-L three read modes memory read from blocks information read from Intelligent Identifier Status Register either VPPL VPPH
Table Operations Mode Read Output Disable Standby Deep PowerDown Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes DQ0-7 DOUT High High High
NOTES Refer Characteristics When VPPL memory contents read written erased control pins addresses VPPL VPPH Characteristics VPPL VPPH voltages when Write State Machine executing internal block erase byte write algorithms when busy Erase Suspend mode deep powerdown mode Command writes involving block erase byte write only successfully executed when VPPH Refer Table valid during write operation
28F008SA-L
status information when accessed during write erase modes reset occurs with flash memory reset proper initialization would occur because flash memory would providing status information instead array data Intel's Flash Memories allow proper initialization following system reset through input this application controlled same RESET signal that resets system
Deep Power-Down
28F008SA-L offers deep power-down feature entered when Current draw thru typical deep powerdown mode with current draw through typically During read modes -low deselects memory places output drivers high-impedence state turns internal circuits 28F008SA-L requires time tPHQV (see Characteristics-ReadOnly Operations) after return from powerdown until initial memory access outputs valid After this wakeup interval normal operation restored Command User Interface reset Read Array upper bits Status Register cleared value 10000 upon return normal operation During block erase byte write modes will abort either operation Memory contents block being altered longer valid data will partially written erased Time tPHWL after goes logic-high (VIH) required before another command written This during system reset important with automated write erase devices When system come reset expects read from flash memory Automated flash memories provide
Intelligent Identifier Operation
Intelligent Identifier operation outputs manufacturer code device code 28F008SA-L system then automatically match device with proper block erase byte write algorithms manufacturer- device-codes read Command User Interface Following write Command User Interface read from address location 00000H outputs manufacturer code (89H) read from address 00001H outputs device code (A2H) necessary have high voltage applied read Intelligent Identifiers from Command User Interface
Table Command Definitions Command Read Array Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Erase Suspend Erase Resume Byte Write Setup Write Alternate Byte Write Setup Write First Cycle Second Cycle Cycles Notes Req'd Operation Address Data Operation Address Data Write Write Write Write Write Write Write Write Write Write Write Write Read Read
NOTES operations defined Table Identifier Address manufacturer code device code Address within block being erased Address memory location written Data read from Status Register Table description Status Register bits Data written location Data latched rising edge Data read from Intelligent Identifiers Following Intelligent Identifier command read operations access manufacture device codes Either recognized Byte Write Setup command Commands other than those shown above reserved Intel future device implementations should used
28F008SA-L
Write
Writes Command User Interface enable reading device data Intelligent Identifiers They also control inspection clearing Status Register Additionally when VPPH Command User Interface controls block erasure byte write contents interface register serve input internal state machine Command User Interface itself does occupy addressable memory location interface register latch used store command address data information needed execute command Erase Setup Erase Confirm commands require both appropriate command data address within block erased Byte Write Setup command requires both appropriate command data address location written while Byte Write command consists data written address location written Command User Interface written bringing logic-low level (VIL) while Addresses data latched rising edge Standard microprocessor write timings used Refer Write Characteristics Waveforms Write Operations Figure specific timing parameters
COMMAND DEFINITIONS
When VPPL applied read operations from Status Register Intelligent Identifiers array blocks enabled Placing VPPH enables successful byte write block erase operations well Device operations selected writing specific commands into Command User Interface Table defines 28F008SA-L commands
Read Array Command
Upon initial device powerup after exit from deep powerdown mode 28F008SA-L defaults Read Array mode This operation also initiated writing into Command User Interface Microprocessor read cycles retrieve array data device remains enabled reads until Command User Interface contents altered Once internal Write State Machine started block erase byte write operation device will recognize Read Array command until completed operation Read Array command functional when VPPL VPPH
Intelligent Identifier Command
28F008SA-L contains Intelligent Identifier operation initiated writing into Command
Table Status Register Definitions
WSMS
VPPS
WRITE STATE MACHINE STATUS Ready Busy ERASE SUSPEND STATUS Erase Suspended Erase Progress Completed ERASE STATUS Error Block Erasure Successful Block Erase BYTE WRITE STATUS Error Byte Write Successful Byte Write STATUS Detect Operation Abort 2-SR RESERVED FUTURE ENHANCEMENTS These bits reserved future should masked when polling Status Register
NOTES Write State Machine Status must first checked determine byte write block erase completion before Byte Write Erase Status checked success Byte Write Erase Status bits ``1''s during block erase attempt improper command sequence entered Attempt operation again status detected Status Register must cleared before another byte write block erase operation attempted Status unlike converter does provide continuous indication level interrogates level only after byte write block erase command sequences have been entered informs system been switched Status guaranteed report accurate feedback between VPPL VPPH
28F008SA-L
User Interface Following command write read cycle from address 00000H retrieves manufacturer code read cycle from address 00001H returns device code terminate operation necessary write another valid command into register Like Read Array command Intelligent Identifier command functional when VPPL VPPH Interface followed Erase Confirm command (D0H) These commands require both appropriate sequencing address within block erased Block preconditioning erase verify handled internally Write State Machine invisible system After two-command erase sequence written 28F008SA-L automatically outputs Status Register data when read (see Figure Block Erase Flowchart) detect completion erase event analyzing output Status Status Register When erase completed Erase Status should checked erase error detected Status Register should cleared Command User Interface remains Read Status Register mode until further commands issued This two-step sequence set-up followed execution ensures that memory contents accidentally erased Also reliable block erasure only occur when VPPH absence this high voltage memory contents protected against erasure block erase attempted while VPPL Status will ``1'' Erase attempts while VPPL VPPH produce spurious results should attempted
Read Status Register Command
28F008SA-L contains Status Register which read determine when byte write block erase operation complete whether that operation completed successfully Status Register read time writing Read Status Register command (70H) Command User Interface After writing this command subsequent read operations output data from Status Register until another valid command written Command User Interface contents Status Register latched falling edge whichever occurs last read cycle must toggled before further reads update Status Register latch Read Status Register command functions when VPPL VPPH
Clear Status Register Command
Erase Status Byte Write Status bits ``1''s Write State Machine only reset Clear Status Register Command These bits indicate various failure conditions (see Table allowing system software control resetting these bits several operations performed (such cumulatively writing several bytes erasing multiple blocks sequence) Status Register then polled determine error occurred during that sequence This adds flexibility device used Additionally Status MUST reset system software before further byte writes block erases attempted clear Status Register Clear Status Register command (50H) written Command User Interface Clear Status Register command functional when VPPL VPPH
Erase Suspend Erase Resume Commands
Erase Suspend command allows block erase interruption order read data from another block memory Once erase process starts writing Erase Suspend command (B0H) Command User Interface requests that suspend erase sequence predetermined point erase algorithm 28F008SA-L continues output Status Register data when read after Erase Suspend command written Polling Status Erase Suspend Status bits will determine when erase operation been suspended (both will ``1'') will also transition this point Read Array command written Command User Interface read data from blocks other than that which suspended only other valid commands this time Read Status Register (70H) Erase Resume (D0H) which time will continue with erase process Erase Suspend Status Status bits Status Register will automatically cleared will return After Erase Resume command written 28F008SA-L automatically outputs Status Register data when read (see Figure Erase Suspend Resume Flowchart) must remain VPPH while 28F008SA-L Erase Suspend
Erase Setup Erase Confirm Commands
Erase executed block time initiated two-cycle command sequence Erase Setup command (20H) first written Command User
28F008SA-L
Byte Write Setup Write Commands (40H 10H)
Byte write executed two-command sequence Byte Write Setup command (40H 10H) written Command User Interface followed second write specifying address data (latched rising edge written then takes over controlling byte write write verify algorithms internally After twocommand byte write sequence written 28F008SA-L automatically outputs Status Register data when read (see Figure Byte Write Flowchart) detect completion byte write event analyzing output Status Status Register Only Read Status Register command valid while byte write active When byte write complete Byte Write Status should checked byte write error detected Status Register should cleared internal verify only detects errors ``1''s that successfully write ``0''s Command User Interface remains Read Status Register mode until further commands issued byte write attempted while VPPL Status will ``1'' Byte write attempts while VPPL VPPH produce spurious results should attempted
bits Figure shows system software flowchart device byte write entire sequence performed with VPPH Byte write abort occurs when transitions drops VPPL Although halted byte data partially written location where byte write aborted Block erasure repeat byte write required initialize this data known value
AUTOMATED BLOCK ERASE
above Quick-Erase algorithm prior Intel Flash devices implemented internally including preconditioning block data operation erase success high voltage presence monitored reported through Status Register Additionally command other than Erase Confirm written device following Erase Setup both Erase Status Byte Write Status bits will ``1''s When issuing Erase Setup Erase Confirm commands they should written address within address range block erased Figure shows system software flowchart block erase Erase typically takes seconds block Erase Suspend Erase Resume command sequence allows suspension this erase operation read data from block other than that which erase being performed system software flowchart shown Figure entire sequence performed with VPPH Abort occurs when transitions falls VPPL while erase progress Block data partially erased this operation repeat erase required obtain fully erased block
EXTENDED BLOCK ERASE BYTE WRITE CYCLING
Intel designed extended cycling capability into ETOX flash memory technologies 28F008SA-L designed byte write block erase cycles each sixteen 64-Kbyte blocks electric fields advanced oxides minimal oxide area cell subjected tunneling electric field combine greatly reduce oxide stress probability failure 20-Mbyte solid-state drive using array 28F008SA-Ls MTBF (Mean Time Between Failure) million hours(1) over times more reliable than equivalent rotating disk technology
DESIGN CONSIDERATIONS Three-Line Output Control
28F008SA-L will often used large memory arrays Intel provides three control inputs accommodate multiple memory connections Three-line control provides lowest possible memory power dissipation complete assurance that data contention will occur efficiently these control inputs address decoder should enable while should connected memory devices system's READ control line This assures that only selected memory devices have active outputs while deselected memory devices Standby Mode should connected system Powergood signal prevent unintended writes during system power transitions Powergood should also toggle during system reset
AUTOMATED BYTE WRITE
28F008SA-L integrates Quick-Pulse programming algorithm prior Intel Flash Memory devices on-chip using Command User Interface Status Register Write State Machine (WSM) On-chip integration dramatically simplifies system software provides processor interface timings Command User Interface Status Register operation internal verify high voltage presence monitored reported output appropriate Status Register
(1)Assumptions 10-Kbyte file written every minutes (20-Mbyte array) (10-Kbyte file) file writes before erase required (2000 files writes erase) cycles 28F008SA-L block) million file writes file writes) write) min) MTBF
28F008SA-L
28F008SA-L returns when finished executing internal algorithm connected interrupt input system controller active times tristated 28F008SA-L inputs brought also when device Erase Suspend deep powerdown modes
Operation Write
Polling
Byte Write Block Erase
full CMOS output that provides hardware method detecting byte write block erase completion transitions time tWHRL after write erase command sequence written
Command Byte Write Setup
Comments Data (10H) Address Byte written
Write
Byte Write
Data written Address Byte written
Standby Read
Check Ready Busy Read Status Register Check Ready Busy Toggle update Status Register
Repeat subsequent bytes
290435
Full status check done after each byte after sequence bytes Write after last byte write operation reset device Ready Array Mode
FULL STATUS CHECK PROCEDURE
Operation Optional Read
Command
Comments already have read Status Register data Ready polling above Check Detect
Standby
Standby
Check Byte Write Error
MUST cleared during byte write attempt before further attempts allowed Write State Machine only cleared Clear Status Register Command cases where multiple bytes written before full status checked error detected clear Status Register before attempting retry other error recovery
290435
Figure Automated Byte Write Flowchart
28F008SA-L
Operation Write
Command Erase Setup
Comments Data Address Within block erased Data Address Within block erased Check Ready Busy Read Status Register Check Ready Busy Toggle update Status Register
Write
Erase
Standby Read
Repeat subsequent bytes
290435
Full status check done after each block after sequence blocks Write after last block erase operation reset device Ready Array Mode
FULL STATUS CHECK PROCEDURE
Operation Optional Read
Command
Comments already have read Status Register data Ready polling above Check Detect
Standby
Standby
Check Both Command Sequence Error
Standby
Check Block Erase Error
MUST cleared during block erase attempt before further attempts allowed Write State Machine
290435
only cleared Clear Status Register Command cases where multiple blocks erased before full status checked error detected clear Status Register before attempting retry other error recovery
Figure Automated Block Erase Flowchart
28F008SA-L
Operation Write
Command Erase Suspend Read Status Register
Comments Data
Write
Data
Standby Read
Check Ready Busy Read Status Register Check Ready Busy Toggle Update Status Register Check Suspended
Standby
Write
Read Array
Data
Read
Read array data from block other than that being erased Erase Resume Data
Write
290435
Figure Erase Suspend Resume Flowchart
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling System designers interested supply current issues standby current levels (ISB) active current levels (ICC) transient peaks produced falling rising edges Transient current magnitudes depend device outputs' capacitive inductive loading Two-line control proper decoupling capacitor selection will suppress transient voltage peaks Each device should have ceramic capacitor connected between each between These high frequency inherent-inductance capacitors should placed close possible package leads Additionally
every devices electrolytic capacitor should placed array's power supply connection between bulk capacitor will overcome voltage slumps caused board trace inductances
Trace Printed Circuit Boards
Writing flash memories while they reside target system requires that printed circuit board designer attention power supply trace supplies memory cell current writing erasing similar trace widths layout considerations given power Adequate supply traces decoupling will decrease voltage spikes overshoots
28F008SA-L
28F008SA-L ensures that Command User Interface reset Read Array mode power system designer must guard against spurious writes voltages above VLKO when active Since both must command write driving either will inhibit writes Command User Interface architecture provides added level protection since alteration memory contents only occurs after successful completion two-step command sequences Finally device disabled until brought regardless state control inputs This provides additional level memory protection
Transitions Command Status Registers
Byte write block erase completion guaranteed drops below VPPH Status Status Register ``1'' Clear Status Register command MUST issued before further byte write block erase attempts allowed Otherwise Byte Write Erase Status bits Status Register will ``1''s error detected transitions during byte write block erase also abort operations Data partially altered either case command sequence must repeated after normal operation restored Device poweroff transitions clear Status Register initial value 10000 upper bits Command User Interface latches commands issued system software altered transitions actions state upon powerup after exit from deep powerdown after transitions below VLKO Read Array Mode After byte write block erase complete even after transitions down VPPL Command User Interface must reset Read Array mode Read Array command access memory array desired
Power Dissipation
When designing portable systems designers must consider battery power consumption only during device operation also data retention during system idle time Flash nonvolatility increases usable battery life because 28F008SA-L does consume power retain code data when system addition 28F008SA-L's deep powerdown mode ensures extremely power dissipation even when system power applied example portable other power sensitive applications using array 28F008SA-Ls solid-state storage lower standby sleep modes producing negligable power consumption access 28F008SA-L again needed part again read following tPHQV tPHWL wakeup cycles required after first raised back Characteristics Read-Only Write Operations Figures more information
Power Down Protection
28F008SA-L designed offer protection against accidental block erasure byte writing during power transitions Upon power-up 28F008SA-L indifferent which power supply powers first Power supply sequencing required Internal circuitry
28F008SA-L
ABSOLUTE MAXIMUM RATINGS
Operating Temperature C(1) During Read During Block Erase Byte Write Temperature Under Bias Storage Temperature Voltage (except VPP) with Respect Program Voltage with Respect during Block Erase Byte Write Supply Voltage with Respect Output Short Circuit Current
NOTICE This data sheet contains information products sampling initial production phases development specifications subject change without notice Verify with your local Intel Sales office that have latest data sheet before finalizing design
0V(2)
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
0V(2 0V(2)
mA(4)
NOTES Operating temperature commercial product defined this specification Minimum voltage input output pins During transitions this level undershoot periods Maximum voltage input output pins which during transitions overshoot periods Maximum voltage overshoot periods Output shorted more than second more than output shorted time specifications valid both voltage ranges Characteristics voltage range specific specification
OPERATING CONDITIONS
Symbol Parameter Operating Temperature Supply Voltage Supply Voltage Notes
Unit
CHARACTERISTICS
Symbol ICCS Parameter Input Load Current
Read Program Erase Notes
Unit
Test Condition VOUT IOUT
Output Leakage Current Standby Current
ICCD
Deep PowerDown Current
28F008SA-L
CHARACTERISTICS (Continued)
Symbol ICCR Parameter Read Current Notes Unit Test Condition IOUT CMOS Inputs IOUT Inputs Byte Write Progress Block Erase Progress Block Erase Suspended
ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VOH1 VOH2 VPPL VPPH VLKO
Byte Write Current Block Erase Current Erase Suspend Current Standby Current Deep PowerDown Current Read Current Byte Write Current Block Erase Current Erase Suspend Current Input Voltage Input High Voltage Output Voltage Output High Voltage (TTL) Output High Voltage (CMOS) during Normal Operations during Erase Write Operations Erase Write Lock Voltage
VPPH Byte Write Progress VPPH Block Erase Progress VPPH Block Erase Suspended
CAPACITANCE(5)
Symbol COUT
Unit Condition VOUT
Parameter Input Capacitance Output Capacitance
28F008SA-L
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device deselected 28F008SA-L read while Erase Suspend Mode current draw ICCES ICCR Includes Block Erases Byte Writes inhibited when VPPL guaranteed range between VPPH VPPL Sampled 100% tested
CHARACTERISTICS
Symbol ICCS Parameter Input Load Current Output Leakage Current Standby Current
Notes
Unit
Test Condition
VOUT IOUT IOUT CMOS Inputs IOUT Inputs Byte Write Progress Block Erase Progress Block Erase Suspended
ICCD ICCR
Deep PowerDown Current Read Current
ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VOH1 VOH2 VPPL
Byte Write Current Block Erase Current Erase Suspend Current Standby Current Deep PowerDown Current Read Current Byte Write Current Block Erase Current Erase Suspend Current Input Voltage Input High Voltage Output Voltage Output High Voltage (TTL) Output High Voltage (CMOS) during Normal Operations
VPPH Byte Write Progress VPPH Block Erase Progress VPPH Block Erase Suspended
28F008SA-L
CHARACTERISTICS (Continued)
Symbol VPPH VLKO Parameter during Erase Write Operations Erase Write Lock Voltage Notes Unit Test Condition
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device deselected 28F008SA-L read while Erase Suspend Mode current draw ICCES ICCR Includes Block Erases Byte Writes inhibited when VPPL guaranteed range between VPPH VPPL
INPUT OUTPUT REFERENCE WAVEFORM
TESTING LOAD CIRCUIT(2)
290435 test inputs driven Logic ``1'' Logic ``0'' Input timing begins output timing ends Input rise fall times (10% 90%) Includes Capacitance
290435
CHARACTERISTICS
Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tACC tPWH tOLZ
Read-Only Operations(1)
Versions Parameter
28F008SA-150 Notes Unit
Read Cycle Time Address Output Delay Output Delay High Output Delay Output Delay Output High Output High Output High Output High
Output Hold from Addresses Change Whichever First
NOTES Input Output Reference Waveform timing measurements delayed after falling edge without impact Sampled 100% tested
28F008SA-L
Figure Waveform Read Operations
290435-
28F008SA-L
CHARACTERISTICS
Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL tVPH tVPS tWPH
Write Operations(1)
Versions Parameter
28F008SA-L200 Notes Unit
Write Cycle Time High Recovery Setup Pulse Width Going High Going High Going
Going
Setup Data Setup Data Hold from
Address Setup
Going High High High
Address Hold from Hold from
High
Pulse Width High High Going
Duration Byte Write Operation Duration Block Erase Operation Write Recovery before Read Hold from Valid High
NOTES Read timing characteristics during erase byte write operations same during read-only operations Refer Characteristics Read-Only Operations Sampled 100% tested Refer Table valid byte write block erasure Refer Table valid byte write block erasure on-chip Write State Machine incorporates byte write block erase system functions overhead standard Intel flash memory including byte program verify (byte write) block precondition precondition verify erase erase verify (block erase) Byte write block erase durations measured completion VOH) should held VPPH until determination byte write block erase success
28F008SA-L
BLOCK ERASE BYTE WRITE PERFORMANCE
Parameter Block Erase Time Block Write Time Byte Write Time Notes
28F008SA-L-200 Typ(1) (Note Unit
NOTES Excludes System-Level Overhead Contact your Intel representative information maximum byte write specification
28F008SA-L
Figure Waveform Write Operations
290435-
28F008SA-L
ALTERNATIVE -CONTROLLED WRITES
Versions Symbol tAVAV tPHEL tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHQV1 tEHQV2 tEHGL tQVVL tVPH tVPS tEPH Write Cycle Time High Recovery Setup Pulse Width Going High Going High Going Parameter
28F008SA-L200 Notes Unit
Going
Setup Data Setup Data Hold from
Address Setup
Going High High High
Address Hold from Hold from
High
Pulse Width High High Going
Duration Byte Write Operation Duration Block Erase Operation Write Recovery before Read Hold from Valid High
NOTES Chip-Enable Controlled Writes Write operations driven valid combination systems where defines write pulsewidth (within longer timing waveform) setup hold inactive times should measured relative waveform Sampled 100% tested Refer Table valid byte write block erasure Refer Table valid byte write block erasure Byte write block erase durations measured completion VOH) should held VPPH until determination byte write block erase success
28F008SA-L
Figure Alternate Waveform Write Operations
290435-
28F008SA-L
ORDERING INFORMATION
290435
VALID COMBINATIONS E28F008SA-L200 F28F008SA-L200
PA28F008SA-L200
ADDITIONAL INFORMATION References
28F008SA Datasheet 28F008SA Mbit (1Mbit Flash Memory SmartDie Product Specification ``28F008SA Hardware Interfacing'' ``28F008SA Software Drivers'' ``28F008SA Automation Algorithms'' ``The Intel 28F008SA Flash Memory'' ``ETOX Flash Memory Technology'' Order Number 290429 271296 292094 292095 292099 294011 290412
AP-359 AP-360 AP-364 ER-27 ER-28
Revision History
Number Description Modified Erase Suspend Flowchart Lowered VLKO from Combined Standby Current Read Current into Standby Current Spec with Test Conditions Characteristics Table) Removed Speed renamed JEDEC standardization compatibility Changed IPPS standby current specifications from Characteristics tables Changed ICCR test condition from Changed ICCS spec from Added IPPR spec Corrected IPPS spec typo Added VOHZ (Output High Voltage CMOS) spec Changed Operating Temp range (read) from C-70 C-70 Changed range from Program Erase Added Byte Write Time spec Changed intelligent identifier device code from supply voltage (program erase) same read ICCD changed Characteristics Read-only operation tAVAV tAVQV tELQV tPHQV tGLQV Corrected ICCS typical value read

High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Block

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