WITH RISK COST REDUCTION MADE EASY today's market, cost

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

WITH RISK COST REDUCTION MADE EASY today's market, cost

Datasheet Thumbnail

Top Searches for this datasheet

FPGA/CPLD CONVERSION SERVICE
WITH
RISK
COST REDUCTION MADE EASY
today's market, cost reduction must maintain competitiveness. products need designed fast, before competition catches FPGA/CPLD usage provides early feedback designers. This allows them tune application prior production. FPGAs provide flexible combination between quick design cycle pre-production phases. specific design, customer paying FPGA resources that used. Programming associated PROM costs remain. soon customer's design frozen, cost manufacturability become important criteria. This where Atmel® conversion service helps purchasing engineering. Ultimate Logic
Equivalent complexity, much smaller FPGA,
Atmel ULC, engineering resources. Atmel's innovative design flow, based Verify-before-silicon techniques, allows Atmel deliver in-system guaranteed parts. There financial obligation does work customer's application
technologies). (sign-off required 0.18
Conversion (ULC) offers pin-to-pin, drop-in replacement customer's FPGA, generating immediate cost savings. Atmel does work. FPGAs converted with minimum involvement customer's
Atmel guarantees working ULC.
With more than years experience 1,800 successful conversions, Atmel proven ability convert FPGAs help maximize cost reduction.
Cost Reduction Easy
FPGA replacement, immediate cost savings with risk
Minimum customer engineering involvement
In-system Guarantee Risk-Free
Verify-before-silicon technique*
Charged only parts work
0.35 technologies
FPGA device, programming resources total silicon area! With Atmel ULCs, these programming resources
removed thereby saving cost. customer possibility smaller packages save board space additional cost.
FPGA Basic Cell Layout (110
These programming resources total silicon area!
ings ands! eliver licatio that
High-end Modem Banking Machine
Sound Card Automotive
extended range design manufacturing capability available within Atmel offers costWORLD CLASS TECHNOLOGY
effective solutions. Complexity Kgates I/Os
ASIC gates* I/Os 2.5V/3.3V 0.35 Metal Layers I/O: 3.3V/5V Kbits DPRAM 1400 ASIC gates* I/Os 2.5V/3.3V 0.35 Metal Layers buffer pitch I/O: 3.3V/5V
2900 ASIC gates* I/Os 1.8V 0.18 Metal Layers I/O: 1.8V/3.3V 1730 Kbits DPRAM
1999
ASIC gate FPGA gates)
2001
2003
Memory Blocks Supported Altera® Xilinx® DPRAM blocks others (Actel Quicklogic etc.) 0.35 Kbits DPRAM ASIC gates. 0.18 1730 Kbits DPRAM 2900 ASIC gates.
Special IO's Supported CMOS, TTL, LVCMOS, LVTTL, PECL, (33/66 MHz) levels, GTL/GTL+, HSTL, SSTL2, SSTL3, CCT, AGP, LVDS. Telecommunication: core, 32/64, CAN, controller, etc. Communication: Reed-Solomon® decoder, Viterbi® decoder, HDLC, APCM. Others: 8051, FFT, PWM, etc. Power Supply
PLL/DLL 100% compatible with Altera Xilinx.
Power Consumption 1.8V, 2.5V, 3.3V static consumption about less than Virtex®, Apex® series. dynamic consumption about less than Virtex, Apex series. 3.3V core with tolerant/compliant I/Os. 2.5V core with 3.3V tolerant/compliant I/Os. 1.8V core with 3.3V tolerant/compliant I/Os. Extensive Packaging Capabilities Latest fine pitch (1.0 compatible with Frequency Matrix 0.35 0.18 Core (MHz) Periphery (MHz) Xilinx Altera. Count: from 1156. Body Size: from CQFP, PQFP, TQFP, VQFP, JLCC, PLCC, PBGA, SOIC, TSOP, PDIP, Chip Scale, etc.
Feasibility Study Flow Atmel performs feasibility study every design before final conversion verification work started. This allows Atmel confirm size, package conversion lead-time, also discuss technical issues with customer. feasibility study, Atmel requires:
WORK
Design netlist (edif, Verilog®, VHDL, etc.) Test vectors available)
Circuit pinout checklist completed
FPGA Netlist
Customer Pinout
Checklist
Retarget/Optimization
Atmel Bonding Diagram
Synthesis Atmel Tool (Leonardo®, Synopsys®, etc.)
Atmel Netlist
Design Rule Check
Atmel Tool
Pre-Layout Functional Simulations
ModelSim (Mentor
Fault Simulations/ATPG
Advisor (Mentor)
Conversion Flow After receiving initial purchase order, design team proceeds with conversion verification programmable logic device ULC.
Atmel Netlist Formal Proof Scan, JTAG Insertion
Clock Tree Synthesis Circuit Layout
Atmel Tool GateEnsemble® (Cadence®)
Atmel Netlist Delays Static Timing Analysis
Prime Time (Synopsys)
Adjust Timing Functional Simulations
ModelSim (Mentor)
Programmed Parts
Functional Timing Comparison
Atmel Tool Tester (Schlumberger S15®, Nextest Maverick®)
First Article Delivery ULCs manufactured prototypes delivered validation application. After customer approval, full production started. Pre-production parts available upon request.
CUSTOMER
Conversion Centers Near Customers USA: Europe: Jose Nantes France Eching Germany Camberley Milan Italy Nantes France
Asia Pacific:
Optional Improvements:
Multiple FPGAs single Stack Capability: Atmel house external memory used along with FPGA ASIC into single package.
Boundary scan insertion JTAG insertion
Stacking Technology Customer Service Dedicated Product Line
Close customer interface support First Pass Success conversions done since 1998
Delivery Plan Agreement Consignment stock available Accounts
Field Application Support Dedicated engineers available interface with customers technical issues.
Quality Test
100% Atmel parts tested Optimized fault coverage Quality reliability monitoring
Obsolete ASICs
Atmel also converts ASICs into ULCs with similar conditions customers want develop second source avoid process obsolescence with their current ASIC vendor.
FPGA/CPLD
FPGA
CPLD
Altera
FLEX10K FLEX6000 ACEX
STRATIX CYCLONE APEXII
FLEX8000 APEX20K APEX20KC
MAX7000/A/B/S MAX9000
MAX5000 MAX3000/A
WWW.ATMEL.COM
Xilinx
XC4000E/EX/XL/XV/XLA XC3000 Spartan Spartan XC5200 Virtex VirtexE SpartanII SpartanIIE Spartan-3 VirtexII
XC9500 XC7000
XC9500XV/XL
CoolRunner® XPLA2/XPLA3 CoolRunnerII
Actel
SX-A Series ProASIC
3200DX ACT3 1200XL ACT1 ACT2
Lattice
ispLSI5000V ispLSI6000 ispLSI8000 ipsLSI1000E/EA ispLSI2000/V/VE/E/VL/A ispLSI3000 MACH1 MACH2 MACH3 4/4A/4LV MACH5/5A/5LV
Agere®
ATT3000 ORCA2C-A ORCA2T-A ORCA2T-B ORCA3/3+
QuickLogic Cypress
pASIC1/2/3 Flash370 MAX340 Ultra37000 Delta39K
FPGA/CPLDs continually being introduced programmable logic vendors. device version device interested converting listed, contact your local Atmel sales representative sales office.
Xilinx Others Lattice Actel Altera
Percentage 1,800 successful conversions FPGA/CPLD vendors.
Atmel Corporation 2325 Orchard Parkway Jose, 95131 TEL.: (408) 441-0311 FAX.: (408) 487-2600 Regional Headquarters Europe Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland TEL.: (41) 26-426-5555 FAX.: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong TEL.: (852) 2721-9778 FAX.: (852) 2722-1369 Japan Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL.: (81) 3-3523-3551 FAX.: (81) 3-3523-7581 Product Contact Chantrerie 70602 44306 Nantes Cedex France TEL.: (33) FAX.: (33) Site http://www.atmel.com
Atmel Corporation 2003. rights reserved. Atmel® combinations thereof registered trademarks Atmel Corporation subsidiaries. Other terms products trademarks others. Actel® registered trademark Actel Corporation, Agere® registered trademark Agere Systems, Inc., Altera® registered trademark Altera Corporation, Cypress® registered trademark Cypress Semiconductor Corporation, Advisor®, ModelSim® registered trademarks Mentor Graphics, Apex®, Gate Ensemble®, Reed-Solomon®, Viterbi® registered trademarks Cadence Design Systems, Inc., Innoveda DxDesigner® registered trademark Innoveda, Inc., Lattice® registered trademark Lattice Semiconductor Corporation, Leonardo Spectrum® registered trademark Synopsys, Nextest Maverick® registered trademark Nextest Systems Corporation, Prime Time® registered trademark Synopsys, Inc., QuickLogic registered trademark QuickLogic Corporation®, Sclumberger S15® registered trademark Schlumberger Technology, CoolRunner®, Spartan®, Virtex®, Xilinx® registered trademarks Xilinx, Inc. Ref.: 4011B-ULC-11/03/15M

WITH RISK COST REDUCTION MADE EASY today's market, cost

Top Searches for this datasheet

Other recent searches