Olive Family ADM6305 -Five-port 10/100M Ethernet Switch Controlle
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Olive Family
ADM6305 -Five-port 10/100M Ethernet Switch Controller
Overview
ADM6305, single chip, 10/100Mbps five-port stand-alone switching controller with built-in data buffer memory which provides cost simple solution though high integration design. Five Reduced interfaces designed 10BASE/100BASE ports. controller, switch engines data buffer memory built-in. chip desktop SOHO applications, each 10/100M port directly connects either 10BASE 100BASE devices. Additionally, ADM6305 breaks distance limitation 10BASE class 100BASE repeaters, increases throughput.
Features
Non-blocking five-port 10/100M switching controller with controller switching engine included cost simple solution 100BASE-TX, 100BASE-FX, 10BASE applications. Configurable 10/100BASE Reduced interfaces 1MII+ 4RMII mode provided. single clock input, 50M, RMII system Speed auto negotiation function ports Store-and- forward operation support. Full line speed capability 14880 packet/sec 148810 packet/sec 100M, with blocking. Broadcast storming prevention Support groups port-based VLAN. Full-duplex (IEEE802.3x) three-way half-duplex flow control (Back pressure). Data buffer SSRAM embedded, support: Port-based, VLAN tag, TCP/IP TOS/DS. Intelligently back-pressure flow control turned on/off port with priority frames Buffer management included. 93C46 EEPROM interface. Dynamic configured 8051 Buffer full faulty provided. Bridging functions such Local address filtering. direct mapping hashing schemes better address coverage. Short routing decision time. Aging function included with configurable aging time. Embedded entries address table. power CMOS technology with 3.3V tolerance 100-pins Plastic Quad Flat Package.
ADMtek Incorporate 00/04/05
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Olive plus Specification
Block Diagram
N-WAY Monitor
EEPROM Configuration
Data Buffer
Link Table
Control Fabric
From port port
TMAC RMAC TMAC RMAC
TMAC RMAC From port port
RMII
RMII
RMII
From port port
Example System Diagram
ADM6305 5-port switch
EEPROM (Option)
Quad PHYceiver
Single PHYceiver
Transformer
Transformer
ADMtek Incorporated 00/04/05
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Diagram
RXD2[1]
RXD2[0]
RXDV2
RXD1[1]
RXD1[0]
RXD0[3]
RXD0[2]
RXD0[1]
RXD0[0]
TXD2[1]
TXD2[0]
TXD1[1]
TXD1[0]
RXDV1
VDDo
TXE2
TXE1
VDDi
TXE3
RXDV0 RXC0 TXC0 TXD0[3] TXD0[2] TXD0[1] TXD0[0] TXE0 VDDo COL0 CRS0 VDDi MII# TEST[1] TEST[0] RESET# high_port[4] VDDi high_port[3] high_port[2] high_port[1] high_port[0] RECALL EEDO/NA16#
TXD3[0] TXD3[1]
RXDV3 VDDi RXD3[0] RXD3[1] REFCLK VDDo TXE4 TXD4[0] TXD4[1] RXDV4 RXD4[0] RXD4[1] VDDi VDDo
OLIVE plus
ADM6305
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
VDDi
VDDo
MDIO
QFLED#
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EESK/XFC#
EECS/BP1
EEDI/BP0
Olive plus Specification
Descriptions
Name Type Descriptions EEPROM Interface
EEDO EEDI EESK EECS EEDO: Data Output serial EEPROM. Internally pull (50K Ohm). Inputs configuration information ADM6305. EEDI: Data Input serial EEPROM. Internally pull down (50K Ohm). ADM6305 outputs data EEPROM EESK: Clock input serial EEPROM. Internally pull ADM6305 outputs clock signal EEPROM Chip Select serial EEPROM. Internally pull down. EECK/s:50ns, h:0ns Transmit Enable. TXE0~4 shows that ADM6305 presenting recovered decoded data TXD0~4[1:0]. TXE0~4 indicates that presenting di-bits TXD0~4[1:0] Reduced transmission. TXE0~4 shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented Reduced MII. TXE0~4 shall negative prior first REFCLK rising edge following final di-bit frame. TXE0~4 shall transition synchronously with REFCLK. Transmit Data. These bundle signals output from ADM6305 Reduced connecting device. These signals transited synchronously with rising edge TXE0~4. When TXE0~4 being asserted, each period TXE0~4, ADM6305 drives recovered encoded data into TXD0~4[1:0] transmission. While TXE0~4 de-asserted, TXD0~4[1:0] will have effect upon Reduced connecting device. TXD0~4[1:0] shall transition synchronously with REFCLK. When TXE0~4 being asserted, TXD0~4[1:0] accepted transmission PHY. TXD0~4[1:0] shall "00" indicate idle when TXE0~4 de-asserted. Values TXD0~4[1:0] other than "00" when TXE0~4 de-asserted reserved out-of-band signaling defined). Values other than "00" TXD0~4[1:0] while TXE0~4 de-asserted shall ignored PHY.
Reduced Interface
TXE0 TXE1 TXE2 TXE3 TXE4
TXD0[1:0] TXD1[1:0] TXD2[1:0] TXD3[1:0] TXD4[1:0]
TXC0 TXD0[3:2]
Transmit Clock port0 mode. Transmit Data port0 mode.
ADMtek Incorporated 00/04/05
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Olive plus Specification RXDV0 RXDV1 RXDV2 RXDV3 RXDV4 Carrier Sense Receive Data Valid. RXDV2, RXDV3 internally pull down. RXDV0~4 shall asserted when receiver idle. specific definition idle 10BASE-T 100BASE-X contained IEEE 802.3 IEEE 802.3u. RXDV0~4 also shows that receiving data presented RXD0~4[1:0] from Reduced connecting device. RXDV0~4 being asserted asynchronous detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when non-contiguous zeroes bits detected, carrier said detected. Loss carrier shall result de-assertion RXDV0~4 synchronous cycles REFCLK which presents first di-bit nibble onto RXD0~4[1:0]. additional bits presented RXD0~4[1:0] following initial de-assertion RXDV0~4, then shall assert RXDV0~4 cycles REFCLK which present second di-bit each nibble, de-assert RXDV0~4 cycles REFCLK which present first di-bit nibble. During false carrier event, RXDV0~4 shall remain asserted duration carrier activity. data RXD0~4[1:0] considered valid once RXDV0~4 being asserted. However, since assertion RXDV0~4 asynchronous relative REFCLK, data RXD0~4[1:0] shall "00" until proper receive signal decoding takes place. Receive Data. RXD2[1:0], RXD3[1:0] internally pull down. These bundle signals input from Reduced connecting device. RXD0~4[1:0] shall transition synchronously REFCLK. each clock period which RXDV0~4 being asserted, RXD0~4[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD0~4[1:0] transferred instead recovered data. RXD0~4[1:0] shall "00" indicate idle when RXDV0~4 deasserted. Values RXD0~4[1:0] other than "00" when RXDV0~4 recovered from RXDV0~4 de-asserted reserved out-of-band signaling defined). Values other than "00"on RXD0~4[1:0] while RXDV0~4 recovered from RXDV0~4 deasserted shall ignored MAC. Upon assertion RXDV0~4, shall ensure that RXD0~4[1:0]="00"until proper receive decoding takes place. These pins will high impedance, ignore input when RXDV0~4 negative. Receive Clock port0 mode. Receive Data. 0[3:2] internally pull down port0 mode. Carrier Sense port0 mode. Collision port0 mode. Internally pull Active low. This tied reversing Reduced (port0 only). There internal pull high default configuration. ADM6305 also provides 1MII+4RMII mode customer specific requirement. default address consecutive numbers follows: 7(for port MII), 11(for port RMII). P.S.: addresses must consecutive numbers, otherwise, ADM6305 won't recognize address PHY. Management Data Clock. Provides reference clock MDIO signal
RXD0[1:0] RXD1[1:0] RXD2[1:0] RXD3[1:0] RXD4[1:0]
100,
RXC0 RXD0[3:2] CRS0 COL0 MII#
MDIO
Management Data Input/output. This provides channels ADM6305 Transceivers transfer control information status.
Display
QFLED# Buffer Full Faulty Display. This occurs when packet lost flow control disabled. flow control enabled PAUSE frames sent, buffer full will flash. found faulty, will always (See function description) Industrial Road, SBIP, Hsin-Chu Version 1.10
ADMtek Incorporated 00/04/05
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Olive plus Specification High Priority Frame high_port[0] high_port[1] high_port[2] high_port[3] high_port[4] Priority setting port0~port4. Internally pull down. high high priority
Configuration
Back Pressure Mode. Internally pull down. BP0~1 modes define different backpressure methods. Each BPA1~3 different algorithm described EEPROM section. following shows ADM6305 configuration back pressure Back Pressure Disable BPA1 (Back Pressure Algorithm Enable BPA2 (Back Pressure Algorithm Enable BPA3 (Back Pressure Algorithm Enable aborted after continuous times collision pull down. Internally pull Full Duplex Flow Control. Internally pull When 802.3 flow control disable, PAUSE frame will sent. (default) Clock reference input 50MHz Reduced MII. Synchronous clock reference receiving, transmitting, control interface. RESET#. Active low. power reset initiate ADM6305 state machines statuses enter initial default state. Besides, will turned when power testing failed. Whenever level changed, ADM6305 recalls EEPROM 8051-like controller configuration data. Internally pull down. Test mode. Internally pull down Test mode. Internally pull down 2.5V 3.3V
NA16# XFC#
Miscellaneous
REFCLK RESET#
RECALL TEST[0] TEST[1] Power Vddi Vddo
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
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Olive plus Specification
EEPROM Content
EEPROM setting must 16-bit mode.
Offset
Content
Check Pattern System Configuration
Description
Must 017C Inter Frame half -duplex mode only. Default zero bittime). sign bit. When zero, means negative. present decimal value time (times four). example, 1010, equal 104. Configurable aging time. Default sec. When one, fast aging time sec) set. zero, aging timer disabled. other value, list below. Aging time (Default) Aging time Aging time 1200 Aging time 2400 Aging time 4800 Aging time 9600 Aging time 38400 Broadcast storming mode. This mode only broadcast Destination address Disable (Default) blocks blocks blocks Maximum Length data field frame format. Maximum length 1536 bytes (Default) Maximum length 1518 bytes Maximum length 1522 bytes Reserved Continuous 16-time collision abort packet enabled zero. Default zero. EEPROM setting higher priority than pin's. Hashing algorithm selection. zero, direct mapping algorithm selected. Otherwise, hashing algorithm adopted. Default zero. Over written address. Default zero, which means overwritten address allowed whenever same address entry condition occurred after hashing algorithm implementation finished.
Must zero. Back Pressure Back- Must Must -Jam number algorithm mode disable carrier (Default) (Default) Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADMtek Incorporated 00/04/05
Olive plus Specification Auto-negotiation monitor N-WAY monitor disable port [4:0]. Enable (Default) Port disable port[4:0]. Enable (Default)
Full/half operation. Each presents dedicated port number. Lower intended smaller port number. stands full duplex, half duplex. Speed setting port [4:0]. Speed operation, 10Mbps 100Mbps. port. stands 100Mbps, 10Mbps. Port-Groups Operation Port group [4:0], Default 00h. Port group [4:0], Default FFh. Port-Groups Operation Port group [4:0], Default 00h. Port group [4:0], Default 00h. 802.3x flow control port enabled port [4:0], stands Enable (Default). Back pressure enabled, must Half duplex mode. enable port 802.3x flow control enabled port [4:0]. stands Disable pin) 802.3x flow control Force 802.3x flow control (ignore port [4:0]. enabled, must full duplex. stands disable (Default). Write FC-bit (10th bit) register4 port [4:0], stands Enable (Default). Reserved Must 112H Reserved Must 132H Reserved Must Reserved Must Reserved Must 150H Reserved Must 170H Reserved Must 150H Reserved Must 170H Reserved Must Reserved Must Reserved Must 15~8 Must Priority Frame operation Auto turn BP/FC, priority packet port [4:0]. stands disable (Default) -Round-robin(sequential) number high priority frame example follows: bit11 bit10 bit9 bit8 Weighted ratio unlimited Weighted ratio Weighted ratio Weighted ratio (Default) Must Must Priority enabled, stands enable (Default).
Speed Half/Full Duplex setting when N-Way monitor disable
priority port VLAN
priority port [4:0], stands check (Default). port. e.g. port port VLAN priority port [4:0], stands check (Default). port. e.g. port port First, ADM6305 will check specific bits recorded type field packet format verify VLAN status packets, then threshold VLAN. default threshold packet high priority. (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
Olive plus Specification
[63:48](tos_pri)(tos_pri_drop), Default First, ADM6305 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. [47:32](tos_pri)(tos_pri_drop), Default First, ADM6305 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. [31:16](tos_pri)(tos_pri_drop), Default First, ADM6305 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. [15: 0](tos_pri)(tos_pri_drop), Default First, ADM6305 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. rewrite register address. These bits present register address selection. rewrite. Default zero (disable). start Default 00H. This means range from sequence default value set. Remember start always remain consistent with first port setting PHY. N/A. rewrite data. After rewrite register address selected, register each port rewrite data. Must 10dH
operation
operation Reserved
Function Description
ADMtek Incorporated 00/04/05 Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive plus Specification
ADM6305 high performance, cost, quality assurance 5-port Fast Ethernet Controller dedicated 5-port switch solutions. This chip operates 50MHz fully complies with IEEE series specifications, including Physical layers. switch operations include forwarding scheme, packet filtering, address learning, buffer management, display, etc. Packets from Reduced interface should stored memory. Then, source address learning, packet filtering, retransmission known unknown port(s) implemented based real application.
Reset Restart
When ADM6305 starts embedded memory self-test mode.
Port Interface 10/100Mbps Reduced Interface
Each port ADM6305 supports Reduced interfaces, which uses pins, TXE0~4, TXD0~4[1:0], RXDV0~4, RXD0~4[1:0]. Feature setting chosen configuration pin. RMII specification following characteristics: supports 10Mbps 100Mbps data rates single clock reference sources from from external source) provides independent 2-bit wide (di-bit) transmit receive data paths RMII Specification Signals Signal Name Direction with respect REFCLK Input
Direction with respect Usage Input Output Synchronous clock reference receive, transmit control interface RXDV Output Input Carrier Sense RXD[1:0] Output Input Receive Data Input Output Transmit Enable TXD[1:0] Input Output Transmit Data detail description (please assignment). addition, ADM6305 also provides mode port only relevant settings described previous pages description.
Buffer Management
buffer memory embedded ADM6305 five port switch operations, which designed based output queuing dynamic shared memory management architecture.
Media Access Control
ADM6305 implements functions IEEE 802.3 protocol such frame formatting, collision handling, etc. ADM6305 generates 56-bit preamble Start Frame delimiter while packet being sent. half-duplex mode, listening before transmitting allows prevent traffic jam. Whenever collision occurs, packet will delayed random time, then resent.
EEPROM Dynamic configured 8051
EEPROM configuration option 5-port switch setting. This setting also called through Recall triggered controller like 8051. EEPROM recall after power-on reset. configuration changed without reset. Toggling "recall" will read EEPROM again, while 8051 will emulate signal like EEPROM.
Operation Modes
ADMtek Incorporated 00/04/05 Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive plus Specification
Reduced interface PHYs transceivers operate 10/100Mbps full half-duplex mode. keep consistent operation speed, these parts (PHY switching controller) will automatically adjusted mode through MDC/MDIO pins. ADM6305 also provides fixed speed operation mode configured EEPROM dynamic configuration controller like 8051. modes support full wire speed operations without interference.
Automatic Address Learning, Forwarding, Filtering Function
Address Recognition ADM6305 provides 1Kbytes embedded address table implement address recognition. Self-learning bridge function based source address packets field. Look-up table different hashing algorithms strengthen bridge ability with high performance assurance. Configurable aging time also supported. entry hashing table calculated 32-bit polynomial (called hashing function) direct mapping called simple hashing function well address called input data Direct mapping function allocated lowest bits SA/DA address buffer address entry. Hashing function selection offset EEPROM. Each (Destination Address) passes through hashing function gets 10-bit entry point embedded SRAM. record empty, packet broadcast, treated unknown frame. Otherwise, record read, then address storage from current packet compared. addresses same, port number decided, packet forwarded assigned port. addresses different, incoming packet also treated unknown packet. broadcast packet will pass through other ports without address recognition. Learning Process Address learning process composed packets hashing function described above. each incoming packet, ADM6305 will check whether packet errorless whether content entry address SRAM assigned. packet will compared source address, port number. both fields match packet information, aging status revised learnt address. addresses matches, port number different, port number reassigned. When entry collides, address ignored record keeps one. Last possibility, record free, address port number incoming packet stored. following diagram describes general operations address learning recognition.
Direct Mapping Hashing Function
[0:9] Address Entry Point
AAA-1 AAA+1 Address Look-up Table
Fig.
Address Learning Recognition
Forwarding Scheme ADM6305 forwarding scheme adopts store-and-forward method. Each determined outgoing packet buffer incoming port directly sent assigned port. forwarding scheme unknown packets treated same broadcast packet. ADM6305 also requires first- in-first-out service, prevent packets disorder.
IEEE 802.3 Congestion Control
half duplex operation, ADM6305 supports back pressure feature. When buffer full, packet 802.3x control frame sent connected segment, which called "back pressure". ADM6305 implements "Alternative back pressure" based either three algorithms described EEPROM section. free blocks buffer memory match below threshold, packet directly transmitted regardless routing decision. Full duplex flow control, ADM6305 follows IEEE 802.3x standard. delay time PAUSE frame zero maximum value. feature allows ADM6305 handle remote-side PAUSE frame. full duplex flow control, state machine threshold values described EEPROM, too. ADMtek Incorporated 00/04/05 Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive plus Specification octets octets octets octets 2octets octets
Destination Address
Source Address
Type Opcode
Pause Time
IEEE 802.3x PAUSE Frame Format diagram shown above IEEE 802.3x Pause frame format. fields listed below. Destination Address: destination address (Generally content 0x0180C2000001) Source Address: source address Type: PAUSE frame type 0x8808 Opcode value fixed, 0x0001 (PAUSE operation) Pause Time: number slot-time PAD: zeroes ADM6305, PAUSE frame received from certain port with 0x0180C2000001 0xFFFFFFFFFFFF, ADM6305 will stop ports transmission packets timer until timeout another PAUSE frame with zero time. buffer full full duplex mode, ADM6305 will send PAUSE frame with maximum delay time, defer receiving packet. When enough buffer released, PAUSE frame with zero delay sent.
Auto-negotiation Operations
When MDC/MDIO pins communicate with transceivers, ADM6305 10/100Mbps half/full duplex mode independently. Otherwise, ADM6305 adjust speed itself according auto-negotiation with PHYceiver.
Priority Frame (CoS) Operations
ADM6305 packets high priority follows: Port Number (set pin), VLAN tag, TCP/IP TOS/DS (both EEPROM 8051-like controller) scheme weighted round robin. priority setting port means that packets received port will priority frames; ADM6305 also judge priority frames checking specific bits VLAN TCP/IP TOS/DS included frame format. ADM6305 will check specific bits recorded type field packet format ensure VLAN TCP/IP TOS/DS status packets, then threshold VLAN TCP/IP TOS/DS declare priority packets. addition, scheme weighted round robin used judging high priority frames, which utilizes notion weighted ratio priority frame normal frame decide frame priority level. When port receives priority frame, back pressure 802.3x flow control will turned until priority frame occurs within seconds, then turn back pressure 802.3x flow control again.
VLAN Broadcast Storming Prevention
ADM6305 supports VLAN function ease administration logical groups stations that communicate they were same LAN, move, change numbers these groups. ADM6305 also supports port-groups scheme effectively prevent broadcast storming from interfering with whole transmission efficiency between ports. ports divided into groups while broadcast storming starting, then broadcast frames transmitted destination port belonging other groups will prohibited. During this time, ports belonging different groups independent. Only destination port broadcast frames same group will allowed. Furthermore, scheme port-group dividing very flexible. overlapped port-groups allowed during some operations, example, port shared groups, other operations between these groups remain independent except overlapped port. Only overlapped port could same different VLAN port-groups.
Inter-Frame
idle time between continuous packets from same port. default value 10Mbps 9.6usec 0.96usec 100Mbps. mode only from TXE. ADMtek Incorporated 00/04/05 Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive plus Specification
MDC, MDIO Interface
Olive plus MDIO
MDIO
Fig. specific application Serial Management Interface There pins Serial Management Interface ADM6305. (Management Data Clock) input pin. functions interface device. MDIO bi-directional interface device. following conditions true, ADM6305 will register register connected transceiver. First, IEEE 802.3x flow control enabled. Then, port number Flow Control Write EEPROM offset enabled. Then, ADM6305 full duplex simultaneously with Transceiver. After write operation through MDIO, auto-negotiation restarted ADM6305 gain information remote 802.3x flow control. Finally, ultimate operation flow control set.
Interface
ADM6305 supports only assigned which represents buffer full test fault. When ADM6305 reset, off. While testing mode, test embedded data buffer address table fails, will flash once, about sec, then stay Next, testing other embedded memory fails, will flash twice, about 1.6sec. After tests successful, status down, about 3.2sec minimum. back pressure full duplex flow control set, buffer full will flash every 200ms, then stay 3.2sec based packet PAUSE frame sent. arrival packet dropped, will flash every 50ms, then stay 3.2sec.
Absolute Maximum Ratings
Supply Voltage (Vcc Input Voltage ADMtek Incorporated 00/04/05 -0.5 -0.5 Industrial Road, SBIP, Hsin-Chu Version 1.10 (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive plus Specification Output Voltage Storage Temperature Ambient Temperature Protection -0.5 (-85°F 302°F) 70°C (32°F 158°F) 2000V
Specifications
Parameter Description
Cinp Lpinp Supply Voltage Power Supply Input Voltage Input HIGH Voltage Input Leakage Current Input HIGH Leakage Current Output Voltage Output HIGH Voltage Input Capacitance Inductance
Condition
2.5V
-0.5
Typical
Units
0.8V 2.0V Iout =2~8mA Iout =-2~-8mA
specifications
EEPROM Timing
EECK
EECS EEDI
EEDO
Parameter Description
Condition
4000
Units
EECK (50% duty cycle) Clock 50MHz EECS/EEDI delay from falling Clock 50MHz EECK idle time EECS Clock 50MHz EEDO valid before rising EECK EEDO hold after rising EECK
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
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Olive plus Specification
RMII Transmit Receive Timing
REF_CLK TX_EN
Preamble
Data
REF_CLK CRS_DV
Preamble
Data
Symbol
Thold
Parameter
Type
Units
REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, Data setup REF_CLK rising edge TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, Data hold from REF_CLK rising edge
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
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Olive plus Specification
ADM6305 Package
ADMtek
plus
Olive
ADM6305
xxxxxxxxxxxxxxxx
SYMBO
inch 0.01 0.098 0.009 0.004 0.547 0.783 0.107 0.012 0.551 0.787 0.026 0.018 0.024 0.063 0.030 0.45 0.134 0.114 0.015 0.008 0.555 0.791 0.25 0.22 0.09 13.9 19.9
2.72 0.30 20.00 0.65 0.60 1.60 0.003 0.75 3.40 0.38 0.20 14.1 20.1
17.2mm 23.2mm
0.076
ADMtek Incorporated 00/04/05
Industrial Road, SBIP, Hsin-Chu Version 1.10
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