Flash Electrical Chip-Erase Second Typical Quick-Pulse Programming Alg

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Flash Electrical Chip-Erase Second Typical Quick-Pulse Programming Alg

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M28F010 1024K (128K CMOS FLASH MEMOR
Flash Electrical Chip-Erase Second Typical Quick-Pulse Programming Algorithm Typical Byte-Program Second Typical Chip-Program Single High Voltage Writing Erasing CMOS Power Consumption Maximum Active Current Maximum Standby Current Command Register Architecture Microprocessor Microcontroller Compatible Write Interface Noise Immunity Features Tolerance Maximum Latch-Up Immunity through Processing
ETOX-III Flash-Memory Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience Compatible with JEDEC-Standard Byte-Wide EPROM Pinouts Program Erase Cycles Minimum Available Three Product Grades (TC) (TC) (TC)
Intel's M28F010 1024-Kbit byte-wide in-system re-writable CMOS nonvolatile flash memory organized bytes bits available 32-pin hermetic CERDIP package M28F010 also available 32-contact leadless chip carrier J-lead Flatpack surface mount packages offers most cost-effective reliable alternative updatable nonvolatile memory M28F010 adds electrical chiperasure reprogramming EPROM technology Memory contents M28F010 erased reprogrammed socket PROM programmer socket on-board during subassembly test insystem during final test in-system after-sale M28F010 increases memory flexibility while contributing time- cost-savings targeted alterable code- data-storage applications where traditional EEPROM functionality (byte erasure) either required cost-effective M28F010 also appropriate where EPROM ultraviolet erasure impractical time consuming
271111
Figure M28F010 Block Diagram
January 1996
Order Number 271111-005
M28F010
271111 271111 271111
Figure M28F010 Configurations Table Description Symbol -A16 -DQ7 Type INPUT INPUT OUTPUT Name Function ADDRESS INPUTS memory addresses Addresses internally latched during write cycle DATA INPUT OUTPUT Inputs data during memory write cycles outputs data during memory read cycles data pins active high float tri-state when chip deselected outputs disabled Data internally latched during write cycle CHIP ENABLE Activates device's control logic input buffers decoders sense amplifiers active high deselects memory device reduces power consumption standby levels OUTPUT ENABLE Gates devices output through data buffers during read cycle active WRITE ENABLE Controls writes control register array Write enable active Addresses latched falling edge data latched rising edge pulse Note With memory contents cannot altered ERASE PROGRAM POWER SUPPLY writing command register erasing entire array programming bytes array DEVICE POWER SUPPLY 10%) GROUND INTERNAL CONNECTION device driven left floating
INPUT
INPUT INPUT
M28F010
271111
Figure M28F010 M80C186 System
PRINCIPLES OPERATION
Flash-memory augments EPROM functionality with in-circuit electrical erasure reprogramming M28F010 introduces command register manage this functionality command register allows 100% TTL-level control inputs fixed power supplies during erasure programming maximum EPROM compatibility absence high voltage M28F010 read-only memory Manipulation external memory-control pins yields standard EPROM read standby output disable intelligent Identifier operations same EPROM read standby output disable operations available when high voltage applied addition high voltage enables erasure programming device functions associated with altering memory contents intelligent Identifier erase erase verify program program verify accessed command register
Commands written register using standard microprocessor write timings Register contents serve input internal state-machine which controls erase programming circuitry Write cycles also internally latch addresses data needed programming erase operations With appropriate command written register standard microprocessor read timings output array data access intelligent Identifier codes output data erase program verification command register only alterable when high voltage Depending upon application system designer choose make power supply switchable available only when memory updates desired When high voltage removed contents register default read command making M28F010 read-only memory Memory contents cannot altered
M28F010
Table M28F010 Operations Pins Operation Read Output Disable READ-ONLY Standby intelligent Identifier (Mfr)(2) intelligent Identifier (Device)(2) Read READ WRITE Output Disable Standby(4) Write VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH VID(7) VID(7) Data Tri-State Tri-State Data Data Data Out(3) Tri-State Tri-State Data In(5) VPP(1) -DQ7
NOTES VPPL ground no-connect with resistor tied ground defined Characteristics Section VPPH programming voltage specified device Refer Characteristics When VPPL memory contents read written erased Manufacturer device codes also accessed command register write sequence Refer Table other addresses Read operations with VPPH access array data intelligent Identifier codes With high voltage standby current equals (standby) Refer Table valid Data-In during write operation intelligent Identifier high voltage Refer Characteristics
system designer choose ``hardwire'' making high voltage supply constantly available this instance operations performed conjunction with command register M28F010 designed accommodate either design practice encourage optimization processor-memory interface
supply switchable available only when memory updates desired When VPPL contents register default read command making 28F010 read-only memory this mode memory contents cannot altered system designer choose ``hardwire'' making high voltage supply constantly available this case Command Register functions inhibited whenever below write lockout voltage VLKO (See Power Down Protection) 28F010 designed accommodate either design practice encourage optimization processor-memory interface OPERATIONS Read M28F010 control functions both which must logically active obtain data outputs Chip-Enable (CE) power control should used device selection Output-Enable (OE) output control should used gate data from output pins independent device selection Figure illustrates read timing waveforms
Integrated Stop Timer
Sucessive command write cycles define durations program erase operations specifically program erase time durations normally terminated associated program erase verify commands integrated stop timer provides simplified timing control over these operations thus eliminating need maximum program erase timing specifications Programming erase pulse durations minimums only When stop timer terminates program erase operation device enters inactive state remains inactive until receiving appropriate verify reset command
Write Protection
command register only active when high voltage Depending upon application system designer choose make pow-
M28F010
When high (VPPH) read operation used access array data output intelligent Identifier codes access data program erase verification When (VPPL) read operation only access array data Output Disable With Output-Enable logic-high level (VIH) output from device disabled Output pins placed high-impedance state Standby With Chip-Enable logic-high level standby operation disables most M28F010's circuitry substantially reduces device power consumption outputs placed high-impedance state independent Output-Enable signal M28F010 deselected during erasure programming program erase verification device draws active current until operation terminated intelligent Identifier Operation intelligent Identifier operation outputs manufacturer code (89H) device code (B4H) Programming equipment automatically matches device with proper erase programming algorithms With Chip-Enable Output-Enable logic level raising high voltage activates operation Data read from locations 0000H 0001H represent manufacturer's code device code respectively manufacturer- device-codes also read command register instances where M28F010 erased reprogrammed target system Following write command register read from address location 0000H outputs manufacturer code (89H) read from address 0001H outputs device code (B4H) Write Device erasure programming accomplished command register when high voltage applied contents register serve input internal state-machine state-machine outputs dictate function device command register itself does occupy addressable memory location register latch used store command along with address data information needed execute command command register written bringing WriteEnable logic-low level (VIL) while Chip-Enable Addresses latched falling edge Write-Enable while data latched rising edge Write-Enable pulse Standard microprocessor write timings used three high-order register bits encode control functions other register bits must zero only exception reset command when written register Register bits correspond data inputs Refer Write Characteristics Erase Programming Waveforms specific timing parameters
M28F010
Placing high voltage enables read write operations Device operations selected writing specific data patterns into command register Table defines these M28F010 register commands
COMMAND DEFINITIONS When voltage applied contents command register default enabling read-only operations
Table Command Definitions Command Cycles First Cycle Second Cycle
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3) Read Memory Read intelligent Identifier Codes(4) Set-up Erase Erase(5) Erase Verify(5) Set-up Program Program(6) Program Verify(6) Reset(7) Write Write Write Write Write Write Write Read Write Read Write Read Write
NOTES operations defined Table Identifier address manufacturer code device code Address memory location read during erase verify Address memory location programmed Addresses latched falling edge Write-Enable pulse Data read from location during device identification (Mfr Device B4H) Data read from location during erase verify Data programmed location Data latched rising edge Write-Enable Data read from location during program verify latched Program command Following Read inteligent command read operations access manufacturer device codes Figure illustrates Quick-Erase Algorithm Figure illustrates Quick-Pulse Programming Algorithm second cycle must followed desired command register write
M28F010
high voltage applied absence this high voltage memory contents protected against erasure Refer Erase Characteristics Waveforms specific timing parameters Erase-Verify Command erase command erases bytes array parallel After each erase operation bytes must verified erase verify operation initiated writing into command register address byte verified must supplied latched falling edge Write-Enable pulse register write terminates erase operation with rising edge Write-Enable pulse M28F010 applies internally-generated margin voltage addressed byte Reading from addressed byte indicates that bits byte erased erase-verify command must written command register prior each byte verification latch address process continues each byte array until byte does return data last address accessed case where data read another erase operation performed (Refer Set-up Erase Erase) Verification then resumes from address last-verified byte Once bytes array have been verified erase step complete device programmed this point verify operation terminated writing valid command Program Set-up) command register Figure Quick-Erase algorithm illustrates commands operations combined perform electrical erasure M28F010 Refer Erase Characteristics Waveforms specific timing parameters Set-up Program Program Commands Set-up program command-only operation that stages device byte programming Writing into command register performs set-up operation Once program set-up operation performed next Write-Enable pulse causes transition active programming operation Addresses internally latched falling edge Write-Enable pulse Data internally latched rising edge Write-Enable pulse rising edge Write-Enable also begins programming operation programming operation terminates with next rising edge Write-Enable used write program-verify command Refer Program-
Read Command While high erasure programming memory contents accessed read command read operation initiated writing into command register Microprocessor read cycles retrieve array data device remains enabled reads until command register contents altered default contents register upon power-up This default value ensures that spurious alteration memory contents occurs during power transition Where supply hard-wired M28F010 device powers-up remains enabled reads until commandregister contents changed Refer Read Characteristics Waveforms specific timing parameters Intelligent Identifier Command Flash-memories intended applications where local alters memory contents such manufacturer- device-codes must accessible while device resides target system PROM programmers typically access signature codes raising high voltage However multiplexing high voltage onto address lines desired system-design practice M28F010 contains intelligent Identifier operation supplement traditional PROM-programming methodology operation initiated writing into command register Following command write read cycle from address 0000H retrieves manufacturer code read cycle from address 0001H returns device code terminate operation necessary write another valid command into register Set-up Erase Erase Commands Set-up Erase command-only operation that stages device electrical erasure bytes array set-up erase operation performed writing command register commence chip-erasure erase command (20H) must again written register erase operation begins with rising edge Write-Enable pulse terminates with rising edge next Write-Enable pulse Erase-Verify Command) This two-step sequence set-up followed execution ensures that memory contents accidentally erased Also chip-erasure only occur when
M28F010
ming Characteristics Waveforms specific timing parameters Program-Verify Command M28F010 programmed byte-by-byte basis Byte programming occur sequentially random Following each programming operation byte just programmed must verified program-verify operation initiated writing into command register register write terminates programming operation with rising edge Write-Enable pulse program-verify operation stages device verification byte last programmed address information latched M28F010 applies internally-generated margin voltage byte microprocessor read cycle outputs data successful comparison between programmed byte true data means that byte successfully programmed Programming then proceeds next desired byte location Figure M28F010 Quick-Pulse Programming algorithm illustrates commands combined with operations perform byte programming Refer Programming Characteristics Waveforms specific timing parameters Reset Command reset command provided means safely abort erase- program-command sequences Following either set-up command (erase program) with consecutive writes will safely abort operation Memory contents will altered valid command must then written place device desired state EXTENDED ERASE PROGRAM CYCLING EEPROM cycling failures have always concerned users high electrical field required thin oxide EEPROMs tunneling literally tear apart oxide defect regions combat this some suppliers have implemented redundancy schemes reducing cycling failures insignificant levels However redundancy requires that cell size doubled expensive solution Intel designed extended cycling capability into ETOX-II flash memory technology Resulting improvements cycling reliability come without increasing memory cell size complexity First advanced tunnel oxide increases charge carrying ability ten-fold Second oxide area cell subjected tunneling electric field one-tenth that common EEPROMs minimizing probabili8 oxide defects region Finally peak electric field during erasure approximately lower than EEPROM lower electric field greatly reduces oxide stress probability failure increasing time wearout factor device programmed erased using Intel's Quick-Pulse Programming Quick-Erase algorithms Intel's algorithmic approach uses series operations (pulses) along with byte verification completely reliably erase program device QUICK-PULSE PROGRAMMING ALGORITHM Quick-Pulse Programming algorithm uses programming operations duration Each operation followed byte verification determine when addressed byte been successfully programmed algorithm allows programming operations byte although most bytes verify first second operation entire sequence programming byte verification performed with high voltage Figure illustrates Quick-Pulse Programming algorithm QUICK-ERASE ALGORITHM Intel's Quick-Erase algorithm yields fast reliable electrical erasure memory contents algorithm employs closed-loop flow similar Quick-Pulse Programming algorithm simultaneously remove charge from bits array Erasure begins with read memory contents M28F010 erased when shipped from factory Reading data from device would immediately followed device programming devices being erased reprogrammed uniform reliable erasure ensured first programming bits device their charged state (Data 00H) This accomplished using Quick-Pulse Programming algorithm approximately seconds Erase execution then continues with initial erase operation Erase verification (data FFH) begins address 0000H continues through array last address until data other than encountered With each erase operation increasing number bytes verify erased state Erase efficiency improved storing address last byte verified register Following next erase operation verification starts that stored address location Erasure typically occurs second Figure illustrates Quick-Erase algorithm
M28F010
Command Operation
Comments
Standby
Wait Ramp VPPH(1)
Initialize Pulse-Count
Write
Set-up Program Program
Data
Write
Valid Address Data
Standby Write Program(2) Verify
Duration Program Operation (tWHWH1) Data Stops Program Operation tWHGL Read Byte Verify Programming
Standby Read
Standby
Compare Data Output Data Expected
Write
Read
Data Resets Register Read Operations Wait Ramp VPPL(1)
Standby
271111
NOTES Characteristics value VPPH power supply hard-wired device switchable When switched VPPL ground no-connect with resistor tied ground defined Characteristics Section Refer Principles Operation
Program Verify only performed after byte programming final read compare performed (optional) after register written with Read command CAUTION algorithm MUST FOLLOWED ensure proper reliable operation device
Figure M28F010 Quick-Pulse Programming Algorithm
M28F010
Command Operation
Comments
Entire Memory Must Before Erasure
Quick-Pulse Programming Algorithm (Figure Standby Wait Ramp VPPH(1)
Initialize Addresses Pulse-Count Write Write Standby Set-up Erase Erase Data Data Duration Erase Operation (tWHWH2) Erase Verify Addr Byte Verify Data Stops Erase Operation tWHGL Read Byte Verify Erasure
Write Standby Read
Standby
Compare Output Increment Pulse-Count
Write Standby
Read
Data Resets Register Read Operations Wait Ramp VPPL(1)
271111
NOTES Characteristics value VPPH power supply hard-wired device switchable When switched VPPL ground no-connect with resistor tied ground defined Characteristics Section Refer Principles Operation
Erase Verify performed only after chip-erasure final read compare performed (optional) after register written with read command CAUTION algorithm MUST FOLLOWED ensure proper reliable operation device
Figure M28F010 Quick-Erase Algorithm
M28F010
DESIGN CONSIDERATIONS Two-Line Output Control
Flash-memories often used larger memory arrays Intel provides read-control inputs accommodate multiple memory connections Two-line control provides lowest possible memory power dissipation complete assurance that output contention will occur efficiently these control inputs address-decoder output should drive chip-enable while system's read signal controls flashmemories other parallel memories This assures that only enabled memory devices have active outputs while deselected devices maintain power standby condition
Trace Printed Circuit Boards
Programming flash-memories while they reside target system requires that printed circuit board designer attention power supply trace supplies memory cell current programming similar trace widths layout considerations given power Adequate supply traces decoupling will decrease voltage spikes overshoots
Power Down Protection
M28F010 designed offer protection against accidental erasure programming during power transitions Upon power-up M28F010 indifferent which power supply powers first Power supply sequencing required Internal circuitry M28F010 ensures that command register reset read mode power system designer must guard against active writes voltages above VLKO when active Since both must command write driving either will inhibit writes control register architecture provides added level protection since alteration memory contents only occurs after successful completion two-step command sequences
Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling System designers interested three supply current (ICC) issues standby active transient current peaks produced falling rising edges chip-enable capacitive inductive loads device outputs determine rnagnitudes these peaks Two-line control proper decoupling capacitor selection will suppress transient voltage peaks Each device should have ceramic capacitor connected between between Place high-frequency low-inherent-inductance capacitors close possible devices Also every eight devices electrolytic capacitor should placed array's power supply connection between bulk capacitor will overcome voltage slumps caused printedcircuit-board trace inductance will supply charge smaller capacitors needed
M28F010 Power Dissipation
When designing portable systems designers must consider battery power consumption only during device operation also data retention during system idle time Flash nonvolatility increases usable battery life your system because M28F010 does consume power retain code data when system Table illustrates power dissipated when updating M28F010
Table M28F010 Typlcal Update Power Dissipation(4) Operation Array Program Program Verify Array Erase Erase Verify Complete Cycle Notes Power Dissipation (Watt-Seconds)
NOTES Bytes typical Prog Pulses (tWHWH1 Formula calculate typical Program Program Verify Power IPP2 typical tWHGL IPP4 typical) Bytes typical Prog Pulses (tWHWH1 ICC2 typical tWHGL ICC4 typical Formula calculate typical Erase Erase Verify Power (VPP3 typical tERASE typical IPP5 typical tWHGL Bytes) (ICC3 typical tERASE typical ICC5 typical tWHGL Bytes) Complete Cycle Array Preprogram Array Erase Program ``Typicals'' guaranteed based limited number samples from production lots
M28F010
ABSOLUTE MAXIMUM RATINGS
Case Temperature Under Bias Storage Temperature Voltage with Respect Ground Voltage with Respect Ground Supply Voltage with Respect Ground During Erase Program Supply Voltage with Respect Ground Output Short Circuit Current
0V(1) 5V(1
NOTICE This data sheet contains preliminary information products production specifications subject change without notice Verify with your local Intel Sales office that have latest data sheet before finalizing design
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
0V(1 0V(1)
mA(3)
NOTES Minimum input voltage During transitions inputs undershoot periods less than Maximum voltage output pins which overshoot periods less than Maximum voltage overshoot periods less than Output shorted more than second more than output shorted time
OPERATING CONDITIONS
Symbol VPPL VPPH Description during Read-Only Operations during Read Write Operations Units Comments NOTE Erase Program Inhibited when VPPL
MIL-STD-883
Symbol Description Operating Temperature (Instant Digital Supply Voltage
Units
Extended Temperature
Symbol Description Case Temperature (Instant Digital Supply Voltage
Units
Avionics Grade
Symbol Description Case Temperature (Instant Digital Supply Voltage
Units
M28F010
CHARACTERISTICS
Symbol ICCS ICC1 ICC2 ICC3 IPPS IPP1 IPP2 IPP3 VOH1 Parameter
NMOS COMPATIBLE
Limits
Unit
Comments VOUT IOUT Programming Progress Erasure Progress VPPL VPPH VPPL VPPH Programming Progress VPPH Erasure Progress
Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Leakage Current Read Current Programming Current Erase Current Input Voltage Input High Voltage Output Voltage Output High Voltage intelligent Identifer Voltage intelligent Identifier Current
M28F010
CHARACTERISTICS
Symbol ICCS ICC1 ICC2 ICC3 IPPS IPP1 IPP2 IPP3 VOH1 VOH2 Parameter
CMOS COMPATIBLE
Limits
(Over Specified Operating Conditions) Unit Comments VOUT IOUT Programming Progress Erasure Progress VPPL VPPH VPPL VPPH Programming Progress VPPH Erasure Progress
Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Leakage Current Read Current Programming Current Erase Current Input Voltage Input High Voltage Output Voltage intelligent Identifer Voltage intelligent Identifier Current
Output High Voltage
CAPACITANCE Symbol COUT Parameter Address Control Capacitance Output Capacitance Limits VOUT Unit Conditions
M28F010
TESTING INPUT OUTPUT WAVEFORM
LOAD CIRCUIT
271111
Testing Inputs driven VOH1 logic ``1'' logic ``0'' Testing measurements made logic ``1'' logic ``0'' Rise Fall time
271111 includes Capacitance
TEST CONDITIONS Input Rise Fall Times (10% 90%) Input Pulse Levels VOH1 Input Timing Reference Level Output Timing Reference Level
CHARACTERISTICS
Versions Symbol tAVAV tELQV Characteristic Read Cycle Time Chip Enable Access Time
Read-Only Operations
M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit
tAVQV tACC Address Access Time tGLQV Output Enable Access Time tELQX Chip Enable Output
tGLQX tOLZ Output Enable Output tGHQZ Output Disable Output High Output Hold from Address Change(1) Write Recovery Time before Read
tWHGL
NOTE Whichever occurs first
M28F010
Figure Waveforms Read Operations
271111-
M28F010
CHARACTERISTICS
Versions Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL Characteristic Write Cycle Time Address Set-Up Time Address Hold Time Data Set-up Time Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Alternative Write Pulse Width
Write Erase Program Operations(1
M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit
tWHEH
tWLWH Write Pulse Width tELEH
tWHWL tWPH Write Pulse Width High tWHWH1 Duration Programming Operation Duration Erase Operation Set-Up Time Chip Enable
tWHWH2 tVPEL
NOTES Read timing characteristics during read write operations same during read-only operations Refer Characteristics Read-Only Operations Chip-Enable Controlled Writes Write operations driven valid combination Chip-Enable Write-Enable systems where Chip-Enable defines write pulse width (within longer Write-Enable timing waveform) set-up hold inactive Write-Enable times should measured relative Chip-Enable waveform
M28F010
ERASE PROGRAMMING PERFORMANCE Parameter Chip Erase Time Chip Program Time Erase Program Cycles Limits 5(1) 2(1) 24(2) Cycles Excludes Programming Prior Erasure Excludes System-Level Overhead Unit Comments
NOTES Cycles Minimum byte programming time excluding system overhead msec msec program msec write recovery) while maximum msec byte msec loops allowed algorithm) chip programming time specified lower than worst case allowed programming algorithm since most bytes program significantly faster than worst case byte
271111
Figure M28F010 Typical Programming Time Temperature
271111
Figure M28F010 Typical Programming Time Voltage
M28F010
271111
Figure M28F010 Typical Erase Time Temperature
271111
Figure M28F010 Typical Erase Time Voltage
M28F010
Figure Waveforms Programming Operations
Alternative Write Timing
271111-
M28F010
Figure Waveforms Erase Operations
271111-
M28F010
ADDITIONAL INFORMATION
Order Number ER-20 ``ETOX Flash Memory Technology ER-24 ``The Intel 28F010 Flash Memory'' RR-60 ``ETOX Flash Memory Reliability Data Summary'' AP-316 ``Using Flash Memory In-System Reprogrammable Nonvolatile Storage'' AP-325 ``Guide Flash Memory Reprogramming'' 294005 294008 293002 292046 292059

Flash Electrical Chip-Erase Second Typical Quick-Pulse Programming Alg

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