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ONE TECHNOLOGY WAY · P.O.BOX 9106 · NORWOOD, MASSACHUSETTS 02062-9106 · 617 / 329-4700

DV DD V SS AV DD DV DD REF OUT

ONE TECHNOLOGY WAY · P.O.BOX 9106 · NORWOOD, MASSACHUSETTS 02062-9106 · 617 / 329-4700
DV DD V SS AV DD DV DD REF OUT
APPLICATION NOTE
Evaluation Board for the AD7710, 24-Bit Sigma Delta A / D Converter
AD7710
RFS MODE TFS DGND AGND SYNC AIN1(+) SDATA A0
RFS TFS A0
9-WAY D-TYPE CONNECTOR
SYNC SDATA
AIN1(-)
DRDY SCLK
DRDY SCLK DGND
AIN2(+) MCLK IN AIN2(-)
10MHz
MCLK OUT V SS REF IN(-) AV DD REF IN(+)
V BIAS I OUT
REF OUT
IC2 AD680
Figure 1. Evaluation Board Basic Schematic Diagram
Link No. LK1
Function This option selects the serial interface mode for the AD7710. It is a double link (both links must be moved together for correct operation) which sets the AD7710 MODE pin and configures the bi-directional buffer on the serial clock. With both links in position A , the MODE input is low putting the device into its external clocking mode and the AD7710 SCLK pin is configured as an input and the serial clock buffer (74HC125) is configured as an input. With both links in position B , the MODE input is high putting the device into its self-clocking mode and the AD7710 SCLK pin is configured as an output and the serial clock buffer (74HC125) is also configured as an output.
This option selects the master clock source for the AD7710. The master clock source comes from the on-board crystal or from an external clock source via SKT6. It is a double link (both links must be moved together for correct operation). With both links in position A, the external clock is selected. The external clock for the AD7710 must be applied to SKT6 which is routed to the MCLK IN pin of the AD7710. With both links in position B, the on-board 10 MHz crystal (XTAL 1) provides the master clock for the device. With the links in this position, the crystal is connected between the MCLK IN and MCLK OUT pins of the AD7710.
LK7-LK10
These links are in series with the AIN1(+), AIN1(-), AIN2(+) and AIN2(-) analog inputs respectively. With link LK7 in place, SKT2 is connected directly to the AIN1(+) input. With LK8 in place, SKT3 is connected directly to the AIN1(-) input. With link LK9 in place, SKT4 is connected directly to the AIN2(+) input. With LK10 in place, SKT5 is connected directly to the AIN2(-) input. These links may be removed so that the input signals at SKT2 to SKT5 can be connected to the component grid for signal conditioning before being applied to the analog inputs of the AD7710.
This link is used to short out the schottky diode, D1, on the AVDD supply when the device is operated with AV DD and DVDD driven from the same supply. When AVDD and DVDD are driven from different supplies, and the shortcircuit current capability of the DVDD supply is too large for the schottky diode, D2, then link option LK11 should be removed placing diode D1 in series with the AVDD line.
Table I. Link Options
LK4 Position A B C C
LK5 Position A A A B
REF IN(+) Voltage REF OUT AD680 VOUT SKT7 I / P SKT7 I / P
REF IN(-) Voltage AGND AGND AGND SKT8 I / P
Table II. Reference Link Options
LK6 Postion A B C
VBIAS Input REF OUT AGND SKT9 I / P
AD7710 acts as a slave device in the serial system and data is clocked out of the part on the falling edge of the externally-applied SCLK and is clocked into the device during the high time of the same externallyapplied clock. Table IV gives the link option positions for the interface modes. Note, inputs A0, SYNC, TFS and RFS all have 10k pull-up resistors to DVDD.
Table III VBIAS Link Options
The VBIAS voltage does have an effect on the AVDD power supply rejection performance of the AD7710. If the VBIAS voltage tracks the AVDD supply, it improves the power supply rejection from the AV DD supply line from 80 dB to 95 dB typ. Using an external zener diode, connected between the AV DD line and the VBIAS input, as the source for the VBIAS voltage gives the improvement in the AV DD power supply rejection performance. CLOCK GENERATION There are two clock source options for the master clock for the AD7710 selected by link, LK2. This is a double link option and the device will not operate correctly unless both links of LK2 are in the same position. When both links are in position B, the on-board 10 MHz crystal oscillator is connected between the MCLK IN and MCLK OUT pins of the AD7710 and this generates the master clock for the AD7710. With both links in position A, MCLK OUT is left open-circuit and MCLK IN is connected directly to SKT6. An external, CMOS-compatible, clock applied to SKT6 will provide the master clock for the AD7710. The frequency of this clock must be in the range from 400 kHz to 10 MHz. Note, for AVDD voltages in excess of +5.25 V, the AD7710 is only specified to operate with a master clock frequency of 8 MHz. AD7710 INTERFACE MODE SELECTION The AD7710 may be set up for either of two serial interface modes. These are controlled on the evaluation board by link option LK1. This is a double link option and the device will not operate correctly in either of the modes unless both links of LK1 are in the same position. The modes are as follows: 1. The Self-Clocking Mode can be used with processors which allow an external device to clock their serial port including most digital signal processors and microcontrollers such as the 68HC11 and 68HC05. It also allows easy interfacing to serial-parallel conversion circuits, allowing interfacing to 74XX299 Universal Shift registers without any additional decoding. In this mode, the AD7710 acts as the master device in the serial system and data is clocked out of the part on the falling edge of the internally generated SCLK and is clocked into the device during the high time of the same internally-generated clock. The External Clocking Mode, is designed for systems which provide a serial clock output which is synchronised to the serial data output including microcontrollers such as the 8XC51, 68HC11 and 68HC05 and most digital signal processors. In this mode, the
LK1 Postion A B
Interface Mode External-Clocking Mode Self-Clocking Mode
Table IV. Interface Mode Selection
EVALUATION BOARD INTERFACING Interfacing to the evaluation board is via a 9-way D-Type connector, SKT1. The pinout for this connector is shown in Figure 2 and its pin designations are given in Table V. The port can be used in both the Self-Clocking Mode and the External Clocking Mode. The port has nine lines which are described below.
Figure 2. Pin Configuration for SKT1, D-Type Connector
Mnemonic SCLK DRDY RFS TFS A0 DGND SDATA DVDD SYNC
Table V. SKT1 Pin Functions
Serial Clock Input / Output. When the device is operating in the External-Clocking Mode, the external serial clock is applied to this terminal and goes via IC3 (74HC125 Quadruple Bus Buffer) to the SCLK pin of the AD7710. When the device is operating in the Self-Clocking Mode, the internal serial clock of the AD7710 is routed to this terminal via IC3. The MODE line controls the direction of buffering on this SCLK line. This output is the DRDY signal from the AD7710 buffered via IC4 (74HC4050 Hex Buffer). This buffered input controls the AD7710 RFS input and in conjunction with TFS controls the direction of the buffering on the SDATA line. This RFS input has a 10 k pull-up resistor to DVDD so that the RFS line will be pulled-up to its inactive high state even if the RFS input terminal is unconnected. This buffered input controls the AD7710 TFS input and in conjunction with RFS controls the direction of the buffering on the SDATA line. This TFS input has a 10 k pull-up resistor to DVDD so that the TFS line will be pulled-up to its inactive high state even if the TFS input terminal is unconnected. This buffered input controls the AD7710 A0 input. This A0 input has a 10 k pull-up resistor to DVDD so that the A0 line will be pulled-up to a logic high state even if the A0 input terminal is unconnected. Digital Ground. This line is connected to the digital ground plane on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. Serial Data Input / Output. When writing to the AD7710 (TFS is low), the external serial data is applied to this terminal and goes via IC3 (74HC125 Quadruple Bus Buffer) to the SDATA pin of the AD7710. When reading from the AD7710 (RFS is low), the internal serial data output of the AD7710 is routed to this terminal via IC3. Digital +5 V Supply. This line is connected to the DVDD supply line on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. This buffered input controls the AD7710 SYNC input. This SYNC input has a 10 k pull-up resistor to DVDD so that the SYNC line will be pulled-up to its inactive high state even if the SYNC input terminal is unconnected.
SOCKETS There are nine sockets on the evaluation board. function of these sockets is outlined in Table VI. Socket SKT1 SKT2-SKT5 SKT6 SKT7 SKT8 SKT9 Function 9 Way D-Type Connector
Sub-Minature BNC Sockets for analog inputs Sub-Minature BNC Socket for external master clock Sub-Minature BNC Socket for external REF IN(+) Sub-Minature BNC Socket for external REF IN(-) Sub-Minature BNC Socket for external VBIAS
DRDY RFS
Table VI. Socket Functions
SET-UP CONDITIONS Care should be taken before applying power and signals to the evaluation board to ensure that all link positions are as per the required operating mode. Figure 4 gives the physical layout of all the links on the board in order to ease set-up. Table VII gives the positions in which the links are set when the evaluation board is sent out. Link LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 LK11 Initial Position Double-Link in Position A, setting board for External Clocking Mode Double Link in Position B, generating AD7710 master clock from Crystal Oscillator Link in place, shorting out R9 Link in Position A, connecting REF IN(+) to REF OUT Link in Position A, connecting REF IN(-) to AGND Link in Position A, connecting VBIAS to REF OUT Link in place, connecting SKT2 to AIN1(+) Link in place, connecting SKT3 to AIN1(-) Link in place, connecting SKT4 to AIN2(+) Link in place, connecting SKT5 to AIN2(-) Link not in place, therefore, D1 is in series with the AVDD line
SDATA
Table VII. Initial Link Positions
DGND 6 DV DD 8 SCLK 1 TFS 4 SDATA 7 RFS 3 DRDY 2 A0 5 SYNC 9 DV DD R7 10k R5 10k 9 11
R8 10k
DV DD C9 0.1µF 14 10
IC3 74HC125
1 3 5 4 6 MODE A0 2 6 1 SCLK 20 RFS 19 TFS SDATA
IC4 74HC4050
24 DGND 18 AGND
LK7 SKT2
R1 C11 7 AIN1(+)
LK8 SKT3
R2 C12 8 AIN1(-)
IC1 AD7710
MCLK OUT 9
XTAL1
LK9 SKT4
R3 C13 AIN2(+) I OUT 17
LK10 SKT5
R4 C14 10 AIN2(-) REF IN(-) 14
V SS LK11 AV
C7 10µF
11 C8 0.1µF
LK3 LK4
R9 200 REF IN(+) 15 A B C
DD D1 HP5082-2810
D2 10µF SD103C
C3 R10 10 10µF
C6 0.1µF
C15 0.1µF REF OUT 16
23 10 C4 0.1µF
IC2 AD680
AV DD C2 0.1µF
Figure 3. AD7710 Evaluation Board Circuit Diagram
COMPONENT LIST
Integrated Circuits IC1 IC2 IC3 IC4 Capacitors C1, C3, C5, C7 C2, C4, C6, C8, C9, C10, C15 Resistors R5, R6, R7, R8 R9 R10 AD7710 AD680 Voltage Reference. 74HC125 Quad Bus Buffers with Three State Outputs. 74HC4050 Hex Buffer. 10µF Capacitors. 0.1µF Capacitors. Crystals XTAL 1 Links LK1, LK2, LK3, LK4, LK5, LK6, LK7, LK8, LK9 LK10, LK11. Sockets SKT1 SKT2 to SKT9 Diodes D1 D2 10 MHz Crystal. Shorting Plugs.
9-Way D Type Connector. Sub-Minature BNC Sockets.
10k Pull Up Resistors. 200 Resistor. 10 Resistor.
HP5082-2810, Schottky Diode. SD103C, Schottky Diode.
Optional Filter Components R1 C11, R2 C12, Can be used on Analog R3 C13, R4 C14 Inputs for filtering. Not included on board.
Figure 4. AD7710 Evaluation Board Silk Screen
Figure 5. PCB Component Side Layout for Figure 3
Figure 6. PCB Solder Side Layout for Figure 3