Evaluation Board AD7710, 24-Bit Sigma Delta Converter Mike Byrne
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TECHNOLOGY P.O.BOX 9106 NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700
Evaluation Board AD7710, 24-Bit Sigma Delta Converter
Mike Byrne Albert O'Grady
INTRODUCTION This Application Note describes evaluation board AD7710 24-Bit Signal Conditioning converter. This converter utilises sigma delta techniques offer 16-bit accuracy (0.0015% FSR) missing codes bits. contains two-channel programmable gain front end, programmable low-pass digital filter bidirectional serial interface. Both analog inputs reference input differential part accept inputs full-scale. features self-calibration mode, which removes internal offset gain errors, system calibration mode, which removes external circuit offset gain errors, background calibration mode which automatically removes internal offset gain errors. addition, flexible serial interface allows AD7710 connect directly Digital Signal Processors (ADSP-2101, TMS320C25, etc.) Microcontrollers (8XC51, 68HC11, etc.). Full data AD7710 available AD7710 data sheet available from
Analog Devices should consulted conjunction with this Application Note when using Evaluation Board. On-board components include AD680, +2.5 reference (the part's +2.5V reference also used), crystal external clock source also used) buffers facilitate AD7710's serial interface modes. basic evaluation board schematic shown Figure while full circuit diagram board shown Figure component silk screen, component side layout solder side layout evaluation board given Figures respectively. LINK OPTIONS AD7710 Evaluation Board several link options available facilitate variety operating conditions these summarised Table position link options should chosen before power applied evaluation board.
DVDD
AD7710
MODE DGND AGND SYNC AIN1(+) SDATA
9-WAY D-TYPE CONNECTOR
SYNC SDATA
AIN1(-)
DRDY SCLK
DRDY SCLK DGND
AIN2(+) MCLK AIN2(-)
10MHz
MCLK IN(-) IN(+)
BIAS
AD680
AVDD
Figure Evaluation Board Basic Schematic Diagram
Link
Function This option selects serial interface mode AD7710. double link (both links must moved together correct operation) which sets AD7710 MODE configures bi-directional buffer serial clock. With both links position MODE input putting device into external clocking mode AD7710 SCLK configured input serial clock buffer (74HC125) configured input. With both links position MODE input high putting device into self-clocking mode AD7710 SCLK configured output serial clock buffer (74HC125) also configured output.
This option selects master clock source AD7710. master clock source comes from on-board crystal from external clock source SKT6. double link (both links must moved together correct operation). With both links position external clock selected. external clock AD7710 must applied SKT6 which routed MCLK AD7710. With both links position on-board crystal (XTAL provides master clock device. With links this position, crystal connected between MCLK MCLK pins AD7710.
This link used short resistor reference decoupling scheme. With this link option place reference decoupling resistor, shorted out. When AD680 reference used reference source device, this link option should place. When using AD7710's internal reference when using external reference which does require decoupling resistor, this link should place. This option used select reference source AD7710's IN(+) pin. With this link position AD7710's on-chip reference used reference source AD7710 connected directly IN(+) input. With this link position AD680 +2.5 reference used reference source AD7710 AD680's VOUT connected, decoupling components, IN(+) input. With this link position external reference, applied SKT7, used reference source AD7710 SKT7 connected, decoupling components (see LK3), IN(+) input.
This option used select voltage source AD7710's IN(-) pin. With this link position IN(-) AD7710 connected directly AGND. AD7710's reference used reference source IN(+), IN(-) should connected AGND. With this link position external voltage, applied SKT8, used reference source AD7710's IN(-) input SKT8 connected directly IN(-) input. external differential voltage required AD7710 should applied between SKT7 SKT8 with appropriately.
This option used select voltage source AD7710's VBIAS pin. With this link position AD7710's on-chip reference used voltage source VBIAS input connected directly VBIAS input. With this link position VBIAS input connected directly AGND. With this link position external voltage, applied SKT9, used voltage source BIAS input SKT9 connected directly VBIAS input.
LK7-LK10
These links series with AIN1(+), AIN1(-), AIN2(+) AIN2(-) analog inputs respectively. With link place, SKT2 connected directly AIN1(+) input. With place, SKT3 connected directly AIN1(-) input. With link place, SKT4 connected directly AIN2(+) input. With LK10 place, SKT5 connected directly AIN2(-) input. These links removed that input signals SKT2 SKT5 connected component grid signal conditioning before being applied analog inputs AD7710.
This link used short schottky diode, AVDD supply when device operated with DVDD driven from same supply. When AVDD DVDD driven from different supplies, shortcircuit current capability DVDD supply large schottky diode, then link option LK11 should removed placing diode series with AVDD line.
Table Link Options
POWER SUPPLIES GROUNDING AD7710 three power supply inputs: AVDD, DVDD VSS. AVDD range from DVDD There additional requirement that AVDD must less than 10.5 evaluation board caters options providing AVDD, DVDD inputs. AVDD DVDD recommended that AVDD DVDD driven from same supply avoid power sequencing issues. applications where separate supply voltages required AVDD DVDD, resistor, R10, SD103C Schottky diode, provide protection AD7710. applications where, shortcircuit current capability DVDD supply large SD103C, link option LK11 should removed placing diode series with AVDD line. supplies decoupled Ground with 10µF tantalum 0.1µF ceramic disc capacitors. AVDD supplies decoupled AGND plane while DVDD supply decoupled DGND plane. Power digital section board DVDD AD7710 routed separately from power analog section AVDD AD7710. systems using single supply AVDD DVDD, AVDD DVDD input terminals should connected together. evaluation board uses extensive ground planing minimise high frequency noise interference from onboard clocks other sources. Once again, ground planing analog section kept separate from that digital section they joined only AD7710 AGND DGND pins. ANALOG INPUT SECTION AD7710 provides differential analog input channels. analog inputs evaluation board applied sub-miniature connectors labelled SKT2, SKT3, SKT4 SKT5. With links through LK10 place these connector inputs routed directly AIN1(+), AIN1(-), AIN2(+) AIN2(-) inputs AD7710. These links removed allow input signals SKT2 SKT5 routed component grid input signal conditioning required. There also option placing antialiasing filters each analog input line. These anti-aliasing components provided with board wire links removed analog input lines insert resistors (these resistor positions labelled through silk screen). There also plated-through holes allow insertion capacitors each line (these capacitor positions labelled through silk screen). REFERENCE INPUT reference input AD7710 differential input with reference voltage, VREF, equal difference between IN(+) IN(-) pin. evaluation board allows reference generated from three sources using link options, LK5. Table summaries reference link options. There additional link, LK3, also used with reference. When place, shorts reference decoupling resistor, This decoupling resistor required when using AD680's VOUT reference source (+). also
required external reference sources. IN(+) input decoupled AGND C15, ceramic disc capacitor. first reference options derive reference voltage from AD7710's internal reference. shorted using when driving IN(+). provides single-ended, +2.5 reference which referred AGND. Therefore, when connected IN(+), IN(-) input should connected AGND LK5. second option AD680's VOUT reference source IN(+). this case, should removed. Once again, AD680 provides single-ended, +2.5 reference which referred AGND. Therefore, when AD680 VOUT connected IN(+), IN(-) input should connected AGND LK5. third option external voltage reference source part. This external reference voltage applied evaluation board SKT7. This external reference voltage single-ended which case IN(-) connected AGND LK5) differential voltage applied between SKT7 SKT8. route voltage SKT8 directly IN(-) input AD7710.
Position
Position
IN(+) Voltage AD680 VOUT SKT7 SKT7
IN(-) Voltage AGND AGND AGND SKT8
Table Reference Link Options
VBIAS INPUT BIAS input AD7710 provides return path most currents flowing analog modulator. provides bias point much analog circuitry modulator. limits BIAS voltage depend reference voltage AVDD voltages. Consult datasheet ensure correct biasing. evaluation board allows VBIAS voltage generated from three sources using link option, LK6. Table summaries VBIAS link options. first options connects VBIAS input directly AD7710. This connection point used either single supply systems dual supply systems with VREF +2.5 second option connects BIAS input directly AGND. This connection point used dual supply systems with +2.5 third option connects VBIAS input SKT9 allow external bias voltage applied AD7710. Note, VBIAS input should driven from impedance point.
Postion
VBIAS Input AGND SKT9
AD7710 acts slave device serial system data clocked part falling edge externally-applied SCLK clocked into device during high time same externallyapplied clock. Table gives link option positions interface modes. Note, inputs SYNC, have pull-up resistors DVDD.
Table VBIAS Link Options
VBIAS voltage does have effect AVDD power supply rejection performance AD7710. VBIAS voltage tracks AVDD supply, improves power supply rejection from supply line from typ. Using external zener diode, connected between line VBIAS input, source VBIAS voltage gives improvement power supply rejection performance. CLOCK GENERATION There clock source options master clock AD7710 selected link, LK2. This double link option device will operate correctly unless both links same position. When both links position on-board crystal oscillator connected between MCLK MCLK pins AD7710 this generates master clock AD7710. With both links position MCLK left open-circuit MCLK connected directly SKT6. external, CMOS-compatible, clock applied SKT6 will provide master clock AD7710. frequency this clock must range from MHz. Note, AVDD voltages excess +5.25 AD7710 only specified operate with master clock frequency MHz. AD7710 INTERFACE MODE SELECTION AD7710 either serial interface modes. These controlled evaluation board link option LK1. This double link option device will operate correctly either modes unless both links same position. modes follows: Self-Clocking Mode used with processors which allow external device clock their serial port including most digital signal processors microcontrollers such 68HC11 68HC05. also allows easy interfacing serial-parallel conversion circuits, allowing interfacing 74XX299 Universal Shift registers without additional decoding. this mode, AD7710 acts master device serial system data clocked part falling edge internally generated SCLK clocked into device during high time same internally-generated clock. External Clocking Mode, designed systems which provide serial clock output which synchronised serial data output including microcontrollers such 8XC51, 68HC11 68HC05 most digital signal processors. this mode,
Postion
Interface Mode External-Clocking Mode Self-Clocking Mode
Table Interface Mode Selection
EVALUATION BOARD INTERFACING Interfacing evaluation board 9-way D-Type connector, SKT1. pinout this connector shown Figure designations given Table port used both Self-Clocking Mode External Clocking Mode. port nine lines which described below.
Figure Configuration SKT1, D-Type Connector
Mnemonic SCLK DRDY DGND SDATA DVDD SYNC
Table SKT1 Functions
SCLK
Serial Clock Input/Output. When device operating External-Clocking Mode, external serial clock applied this terminal goes (74HC125 Quadruple Buffer) SCLK AD7710. When device operating Self-Clocking Mode, internal serial clock AD7710 routed this terminal IC3. MODE line controls direction buffering this SCLK line. This output DRDY signal from AD7710 buffered (74HC4050 Buffer). This buffered input controls AD7710 input conjunction with controls direction buffering SDATA line. This input pull-up resistor DVDD that line will pulled-up inactive high state even input terminal unconnected. This buffered input controls AD7710 input conjunction with controls direction buffering SDATA line. This input pull-up resistor DVDD that line will pulled-up inactive high state even input terminal unconnected. This buffered input controls AD7710 input. This input pull-up resistor DVDD that line will pulled-up logic high state even input terminal unconnected. Digital Ground. This line connected digital ground plane evaluation board. allows user provide digital supply connector along with other digital signals. Serial Data Input/Output. When writing AD7710 (TFS low), external serial data applied this terminal goes (74HC125 Quadruple Buffer) SDATA AD7710. When reading from AD7710 (RFS low), internal serial data output AD7710 routed this terminal IC3. Digital Supply. This line connected DVDD supply line evaluation board. allows user provide digital supply connector along with other digital signals. This buffered input controls AD7710 SYNC input. This SYNC input pull-up resistor DVDD that SYNC line will pulled-up inactive high state even SYNC input terminal unconnected.
SOCKETS There nine sockets evaluation board. function these sockets outlined Table Socket SKT1 SKT2-SKT5 SKT6 SKT7 SKT8 SKT9 Function D-Type Connector
Sub-Minature Sockets analog inputs Sub-Minature Socket external master clock Sub-Minature Socket external IN(+) Sub-Minature Socket external IN(-) Sub-Minature Socket external VBIAS
DRDY
Table Socket Functions
SET-UP CONDITIONS Care should taken before applying power signals evaluation board ensure that link positions required operating mode. Figure gives physical layout links board order ease set-up. Table gives positions which links when evaluation board sent out. Link LK10 LK11 Initial Position Double-Link Position setting board External Clocking Mode Double Link Position generating AD7710 master clock from Crystal Oscillator Link place, shorting Link Position connecting IN(+) Link Position connecting IN(-) AGND Link Position connecting VBIAS Link place, connecting SKT2 AIN1(+) Link place, connecting SKT3 AIN1(-) Link place, connecting SKT4 AIN2(+) Link place, connecting SKT5 AIN2(-) Link place, therefore, series with AVDD line
DGND
SDATA
DVDD
SYNC
Table VII. Initial Link Positions
SKT1
DGND SCLK SDATA DRDY SYNC
0.1µF
0.1µF
74HC125
MODE SCLK SDATA
74HC4050
DRDY
DGND AGND
SYNC
MCLK
SKT2
AIN1(+)
SKT3
AIN1(-)
AD7710
SKT6
MCLK
XTAL1
SKT4
AIN2(+)
LK10 SKT5
AIN2(-) IN(-)
SKT8
LK11
10µF
0.1µF
IN(+)
HP5082-2810
10µF SD103C
10µF
0.1µF
0.1µF
SKT7
0.1µF
BIAS
AD680
10µF
0.1µF
SKT9
Figure AD7710 Evaluation Board Circuit Diagram
COMPONENT LIST
Integrated Circuits Capacitors C1,C3,C5,C7 C2,C4,C6, C8,C9,C10, Resistors R5,R6,R7,R8 AD7710 AD680 Voltage Reference. 74HC125 Quad Buffers with Three State Outputs. 74HC4050 Buffer. 10µF Capacitors. 0.1µF Capacitors. Crystals XTAL Links LK1,LK2,LK3, LK4,LK5,LK6, LK7, LK8,LK9 LK10,LK11. Sockets SKT1 SKT2 SKT9 Diodes Crystal. Shorting Plugs.
9-Way Type Connector. Sub-Minature Sockets.
Pull Resistors. Resistor. Resistor.
HP5082-2810, Schottky Diode. SD103C, Schottky Diode.
Optional Filter Components C11,R2 C12, used Analog C13,R4 Inputs filtering. included board.
Figure AD7710 Evaluation Board Silk Screen
Figure Component Side Layout Figure
Figure Solder Side Layout Figure
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