Section Overview Description .1-1 TSEV8388B Evaluation Board .1-2
|
|
|
Top Searches for this datasheet
8-bit Gsps TSEV8388B Evaluation Board
Section Overview
Description .1-1 TSEV8388B Evaluation Board .1-2 Board Mechanical Characteristics.1-3 Analog Input, Clock Input De-embedding Fixture Accesses .1-4 Digital Outputs Accesses .1-4 Power Supplies Ground Accesses.1-4 Functions Settings Accesses.1-4
Section Layout Information
Board .2-1 Inputs/Digital Outputs.2-1 Functions Settings .2-1 Power Supplies .2-2 TS8388B On-board Implementation .2-2
Section Operating Procedures Characteristics
Introduction .3-1 Operating Procedure.3-1 Electrical Characteristics.3-2 Operating Charcteristics.3-3
Section Application Information
Introduction .4-1 Analog Inputs .4-1 Clock Inputs .4-1 Setting Digital Output Data Format .4-1 Gain Adjust .4-2 Connectors Microstrip Lines De-embedding Fixture .4-2 Temperature Monitoring Data Ready Reset Function.4-3 TS8388B Diode Junction Temperature Measurement Setup .4-3 Data Ready Output Signal Reset .4-4 Test Bench Description .4-5
4.7.1
TSEV8388B Evaluation Board
2162C-BDC-01/04
Table Contents
Section Package Description.
TS8388BGL Pinout .5-1 TS8388BF/TS8388BFS Pinout .5-3 CBGA68 Thermal Characteristics .5-5 Thermal Resistance from Junction Ambient: Rthja .5-5 Thermal Resistance from Junction Case: Rthjc .5-5 CBGA68 Board Assembly with External Heatsink.5-5 Thermal Resistance from Junction Ambient: Rthja .5-6 Thermal Resistance from Junction Case: Rthjc .5-6 CBGA68 Board Assembly with External Heatsink.5-7 Enhanced CQFP68 .5-8 Thermal Resistance from Junction Case: Rthjc .5-8 Heatsink.5-8
5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.4.3 5.5.1 5.5.2 5.5.3
Nominal CQFP68 Thermal Characteristics .5-6
Enhanced CQFP68 Thermal Characteristics .5-8
Ordering Information .5-9
Section Schematics
TSEV8388B Electrical Schematics .6-1 Evaluation Board Schematics .6-4 CBGA68 Option.6-4 CQFP68 Option .6-6
6.2.1 6.2.2
2162C-BDC-01/04
TSEV8388B Evaluation Board
Section Overview
Description
TSEV8388B Evaluation Board (EB) prototype board which been designed order facilitate evaluation characterization TS8388B device full power bandwidth Gsps extended temperature range. high speed TS8388B requires careful attention circuit design layout achieve optimal performance. This four metal layer board with internal ground plane adequate functions order allow quick simple evaluation TS8388B performances over temperature range. TS8388B Evaluation Board (EB) very straightforward only implements TS8388B device, connectors input/output accesses 2.54 pitch connector compatible with high frequency acquisition system probes. board also implements de-embedding fixture order facilitate evaluation high frequency insertion loss inputs microstrip lines, junction temperature measurement setting. board constituted sandwich dielectric layers, featuring insertion loss enhanced thermal characteristics operation high frequency domain extended temperature range. board dimensions board comes fully assembled tested, with TS8388B installed heatsink. 8-bit Gsps evaluation board fully compatible with companion device evaluation board (TSEV81102G0 DMUX).
TSEV8388B Evaluation Board
Rev. 2162C-BDC-01/04
Overview
TSEV8388B Evaluation Board
Figure 1-1. TSEV8388B Block Diagram
Differential Clock inputs CLKB TS8388B DR/DRB D0/D0B Differential Clock inputs VINB VINB D7/D7B OR/ORB
CLKB MC100EL16 Differential Receivers (optional)
Digital Output Data
Gain Adjust GAIN/GND
Gray Binary Output Data Select GORB VPLUSD GORB AVEE DVEE DIOD/DRRB
VPLUSD (ECL) VPLUSD 2.4V (LVDS) VEEA VEED diode diode
(Deembedding fixture)
CAL1 CAL2 CAL3 CAL4
LVIN/VINb LCLK/CLKb
DRRB
V-GND V-GND
VEET
VEEA Short-circuit possibility here
VEED
MC100EL16 SUPPLIES
2162C-BDC-01/04
TSEV8388B Evaluation Board
Overview
Board Mechanical Characteristics
board layer's number, thickness, functions given below, from bottom. Table 1-1. Board Layers Thickness Profile
Layer Layer Copper layer Layer RO4003 dielectric layer (Hydrocarbon/Wovenglass) Characteristics Copper thickness signals traces microstrip lines signals traces (GORB, GAIN, DIODE) Layer thickness Dielectric constant -0.044 dB/inch insertion loss -0.318 dB/inch insertion loss Copper thickness Upper ground plane reference plane microstrip return Layer thickness Copper thickness Lower ground plane (board mechanical rigidity) Layer thickness Copper thickness Power planes VEEA, VEED, VEET, VDD, VCC, VPLUSD ground plane
Layer Copper layer Layer BT/Epoxy dielectric layer Layer Copper layer Layer BT/Epoxy dielectric layer Layer Copper layer
TSEV8388B seven-layer constituted four copper layers three dielectric layers. four metal layers correspond respectively from bottom signals layer (layer ground layers (layers supply layer (layer upper inner ground plane (layer constitutes reference plane impedance signal traces. lower inner ground plane (layer used dielectric substrate rigidity replica upper ground plane. backside metal layer dedicated power supplies planes, surrounded ground plane. three dielectric layers respectively (from bottom) constituted insertion loss dielectric layer (RO4003) (layer parallel BT/Epoxy dielectric layers (layers Considering severe mechanical constraints wide temperature range high frequency domain which board operate, necessary sandwich different dielectric materials, with specific characteristics: insertion loss RO4003 Hydrocarbon/wovenglass dielectric layer thickness, chosen loss (-0.318 dB/inch) enhanced dielectric consistency high frequency domain. RO4003 dielectric layer dedicated routing impedance signal traces (the RO4003 typical dielectric constant GHz). RO4003 dielectric layer characteristics very close PTFE terms insertion loss characteristics. BT/Epoxy dielectric layer total thickness which sandwiched between upper ground plane back-side supply layer.
TSEV8388B Evaluation Board
2162C-BDC-01/04
Overview
BT/Epoxy layer been chosen because enhanced mechanical characteristics elevated temperature operation. typical dielectric constant MHz. More precisely, BT/Epoxy dielectric layer offers enhanced characteristics compared Epoxy, namely: Higher operating temperature value: 170° (125° FR4). Better with standing thermal shocks (-65° 170° total board thickness previously described mechanical frequency characteristics makes board particularly suitable device evaluation characterization high frequency domain military temperature range.
Analog Input, differential active inputs (Analog, Clock, De-embedding fixture) provided connectors. Clock Input De-embedding Reference: VITELEC 142-0701-851. Fixture Accesses
Digital Outputs Accesses
Access differential output data port provided 2.54 pitch connector, compatible with High Speed Digital Acquisition System. enables access converter output data, well proper differential termination.
Power Supplies Ground Accesses
power supplies accesses provided five section banana jacks respectively VEEA, VEED, VEET, VDD, VPLUSD VCC. Ground accesses provided banana jacks.
Functions Settings Accesses
functions settings accesses (GORB, junction temp., gain adjust), smaller section banana jacks provided. potentiometer provided gain adjust.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Section Layout Information
Board
TS8388B requires proper board layout optimum full speed operation. following explains board layout recommendations demonstrates Evaluation Board fulfills these implementation constraints. single impedance ground plane recommended, since allows user signal traces power planes without interrupting ground plane. Therefore multi-layer board structure been retained TSEV8388B. Four copper metal layers used, dedicated respectively (from bottom) signal traces, ground planes power supplies. input/output signal traces occupy metal layer. ground planes occupy second third copper metal layers. bottom metal layer dedicated power supplies.
Inputs/Digital board uses impedance microstrip lines differential analog inputs, clock inputs, differential digital outputs (including Range data ready Outputs
output signal). input signals clock signals must routed layer only, without using through-hole vias. line lengths matched within digital output lines differentially terminated. output data traces lengths matched within 0.25 inch minimize data output delay skew. TSEV8388B propagation delay approximately ps/mm (155 ps/inch). RO4003 typical dielectric constant GHz. more informations about different output termination options, refer specification application notes.
Functions Settings
signals traces impedance. They have been routed with impedance near device because room restriction.
TSEV8388B- Evaluation Board
Rev. 2162C-BDC-01/04
Layout Information
Power Supplies
bottom metal layer dedicated power supply traces (VEEA, VEED, VEET, VCC, VDD, VPLUSD). supply traces approximately wide order present impedance, surrounded ground plane connected inner ground planes. Analog Digital negative power supply traces independent, possibility exists short-circuit both supplies metal layer. difference high speed performance observed when connecting both negative supply planes together. Obviously single negative supply plane could used circuit. Each power supply incoming bypassed Tantalum capacitor parallel with chip capacitor. Each power supply access decoupled very close device surface mount chip capacitors parallel.
Note: decoupling capacitors superposed. this configuration, capacitors must mounted first.
TS8388B Onboard Implementation
Surface-mount resistors chip capacitors allow closest possible connections device pins, microstrip line back termination bypassing. Connecting positive supply pads: positive supply pads denoted VCC: corresponding numbers Each power supply decoupled closely device possible chip capacitor. supply pads connected back side plane CEB. positive digital supply pads denoted VPLUSD 2.4V). corresponding VPLUSD numbers Each VPLUSD power supply decoupled very close device chip capacitor. VPLUSD supply pads connected back side VPLUSD plane evaluation board. Connecting negative supply pads: TS8388BGL separate analog digital supplies: negative analog supply pads denoted VEE. corresponding numbers negative digital supply denoted DVEE. DVEE corresponding number DVEE supply dedicated digital output buffers only. Each DVEE power supply decoupled closely possible near device chip capacitor. DVEE supply pads respectively connected backside layer VEED supply planes. Ground pads connections: analog ground pads denoted GND. corresponding numbers
2162C-BDC-01/04
TSEV8388B- Evaluation Board
Section Operating Procedures Characteristics
Introduction
This section describes typical single-ended configuration analog inputs clock inputs. single-ended configuration preferable, corresponds most straightforward quickest TSEV8388B board setting evaluating TS8388B full speed military temperature range. inverted analog input VINB clock input CLKB common mode level Ground (on-board terminated). this configuration, balun transformer needed convert properly single-ended mixer output balanced differential signals analog inputs. same way, balun necessary feed TS8388B clock inputs with balanced signals. Connect directly sources in-phase analog clock inputs converter. However, dynamic performances somewhat improved entering either analog clock inputs differential mode.
Operating Procedure
Connect power supplies Ground accesses (VCC +5V, VPLUSD VEAE VEED -5V) through dedicated banana jacks. power supplies should turned first. Note: single power supply used supplying digital VEED analog VEEA power planes. board default digital outputs binary format. Connect clock signal. inverted phase clock input CLKB left open on-board terminated). phase noise source. clock input level typically should exceed into termination resistor (maximum ratings clock input power level dBm). Clock frequency range between Gsps.
TSEV8388B Evaluation Board
Rev. 2162C-BDC-01/04
Operating Procedures Characteristics
Connect analog signal VIN. inverted phase clock input VINB left open on-board terminated). phase noise source. Full Scale range 0.5V peak peak around (±250 mV), into Input frequency range from GHz. GHz, attenuates input signal. Connect high speed data acquisition system probes output connector. connector pitch (2.54 compatible with High Speed Digital Acquisition System probes. digital data on-board differentially terminated. However, output data picked either single-ended differentially mode. Board functionality verification proposed product evaluation procedure: first test Msps/250 Nyquist: about Effective Bits (typ) should obtained. Gsps/500 MHz: about Effective Bits (typ) should obtained. Gsps/1 Full Scale analog input, bits SFDR should obtained. same conditions Full Scale input, bits obtained. devices operate respectively from Msps Gsps binary output format Msps Gsps Gray output format. capable sampling analog input waveforms ranging from GHz.
Electrical Characteristics
Table 3-1. Absolute Maximum Ratings
Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VINB Clock input voltage Maximum difference between VCLK VCLKB Static input voltage Digital input voltage Digital output voltage Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Notes: Symbol DVEE(2) VPLUSD VEE(2) DVEE VINB VINB VCLK VCLKB VCLK VCLKB Tstg Tleads GORB DRRB Comments Value -5.7 -0.3 +1.5 -0.3 +0.3 -0.3 +0.9 VPLUSD VPLUSD -0.5 +145 +150 +300 Unit
Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating affect device reliability. thermal heat sink mandatory. case only supply used supplying negative power planes, apply VEED absolute maximum ratings.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Operating Procedures Characteristics
Operating Charcteristics
power supplies denoted VCC, VEEA, VEED VPLUSD dedicated TS8388B ADC. power supplies denoted VEET, dedicated optional MC100EL16 asynchronous differential receivers.
Table 3-2. Electrical Operating Characteristics
Value Parameter Positive supply voltage (dedicated TS8388B only) Symbol VPLUSD LVDS: VEEA VEED Positive supply current IPLUSD IEEA IEED Positive supply voltage used default installed (dedicated MC100EL16 differential Receivers) Positive supply current used default installed (dedicated MC100EL16 differential Receivers) Nominal power dissipation (without receivers) Analog input impedance Full Power Analog Input Bandwidth Full Power Analog Input Bandwidth CBGA68 packaged device CQFP68 packaged device Analog Input Voltage range (differential mode) Clock input impedance Clock inputs voltage compatibility (Single-ended differential) (See Application Notes) Clock input power level into termination resistor VEET IEET -5.25 -5.25 -5.25 -2.15 -125 4.75 ECL: -0.8 LVDS: 5.25 LVDS: -4.75 -4.75 -4.75 -185 125° Unit
levels (typ.) into
TSEV8388B Evaluation Board
2162C-BDC-01/04
Operating Procedures Characteristics
2162C-BDC-01/04
TSEV8388B Evaluation Board
Section Application Information
Introduction
this section, refer also product Specification application notes (TS8388BGL Datasheet). More particularly, refer sections related single-ended differential input configurations.
Analog Inputs
analog inputs entered differential single-ended mode without high speed performance degradation. board digitizes single-ended signals choosing either input leaving other input open, latter on-board terminated. nominal In-phase inputs (See Section
Clock Inputs
clock inputs entered differential single-ended mode without high speed performance degradation. Moreover, clock input common mode -1.3V input format used clock inputs. analog input, either clock input chosen, leaving other input open, both clock inputs on-board terminated. nominal in-phase clock input (See Section
Setting Digital Output Data Format
this section, refer Evaluation Board Electrical schematic components placement document (respectively Figure Figure 6-7). Refer also TS8388B specification pages about digital output coding. TS8388B delivers data natural binary code Gray code. "GORB" input left floating tied data format selected will natural binary, this input tied ground data will follow Gray code. jumper denoted selecting output data port format: left floating tied VCC, data output format true Binary, tied GND, data outputs Gray format.
TSEV8388B Evaluation Board
Rev. 2162C-BDC-01/04
Application Information
VPLUSD positive supply voltage allows adjustment output common mode level from -1.2V (VPLUSD output compatibility) +1.2V (VPLUSD 2.4V LVDS output compatibility). Each output voltage varies between -1.02V -1.35V (respectively +1.38V +1.05V), leading ±0.33V differential, around -1.8V (respectively +1.21V) common mode VPLUSD (respectively 2.4V).
Gain Adjust gain adjustable means (60) (pad input impedance
parallel with pF). jumper denoted been foreseen order have access gain adjust pin. potentiometer dedicated adjusting gain from approximately 0.85 1.15. gain adjust transfer function given below. Figure 4-1. Gain Adjust
1.20 1.15 1.10 Gain 1.05 1.00 0.95 0.90 0.85 0.80 -600 -400 -200
Vgain (command voltage) (mV)
Connectors Microstrip Lines Deembedding Fixture
Attenuation microstrip lines found taking difference magnitudes scattering parameters measured different lengths meandering transmission lines. Such difference measurement also removes common losses such those transitions connectors. scattering parameter corresponds amount power transmitted through two-port network. characteristic impedance microstrip meander lines must close minimize impedance mismatch with network analyzer test ports. Impedance mismatch will cause ripple parameter function both degree mismatch length line.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Application Information
Temperature Monitoring Data Ready Reset Function
TS8388B Diode Junction Temperature Measurement Setup
single used both DRRB input command junction monitoring. denomination DRRB/DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously.
4.7.1
operation extended temperature range, forced convection required, maintain device junction temperature below specified maximum value 125° junction temperature measurement setting been included board, junction temperature monitoring. Four section banana jacks (J9, J10, J11, J12) provided force current measure voltage across dedicated transistor connected between pads measurement method consists forcing current flowing into diode mounted transistor, connected between (pad emitter shorted base-collector).
CAUTION: Respect current source polarity. case, make sure maximum voltage compliance current source limited maximum resistor mounted serial with current source avoid damage occurring transistor device. This occur instance current source reverse connected. measurement setup described Figure 4-2. diode forward voltage versus junction temperature steady state conditions) given Figure 4-3. Figure 4-2. TS8388B Diode Junction Temperature Measurement Setup
banana connectors I-GND
Pads I-DIODE
V-DIODE NP1032C2
V-GND
TSEV8388B Evaluation Board
2162C-BDC-01/04
Application Information
Figure 4-3. Transistor Forward Voltage Versus Junction Temperature
1000 (mV)
Junction temperature (°C)
Data Ready Output Signal Reset
subvis connector provided DRRB command. Data ready signal reset falling edge DRRB input command, logical level (-1.8V). DRRB also tied Data Ready output signal master Reset. long DRRB remains logical level, tied -5V), Data Ready output remains logical zero independent external free running encoding clock. Data ready output signal (DR, DRB) reset logical zero after TRDR typical. TRDR measured between -1.3V point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR, DRB). Data ready Reset command pulse minimum time width. Data ready output signal restarts DRRB command rising edge, logical high levels (-0.8V). DRRB also grounded, allowed float, normal free running Data ready output signal.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Application Information
Test Bench Description
Figure 4-4. Differential Analog Clock Inputs Configuration
Generator 180° Hybrid
Synchro
dBc/Hz offset from
Generator
180° Hybrid
dBc/Hz offset from
CLKB Data Data Acquisition System GPIB Tunable delay line TS8388B VINB
Note:
TS81102G0 DMUX device used output order slow down output data rate factor
Figure 4-5. Single-ended Analog Clock Input Configuration
Generator
Synchro
Generator
(typ)
(open) CLKB Data Data Acquisition System GPIB
dBm) VINB (open)
TS8388B Tunable delay line
Note:
TS81102G0 DMUX device used output order slow down output data rate factor
TSEV8388B Evaluation Board
2162C-BDC-01/04
Application Information
2162C-BDC-01/04
TSEV8388B Evaluation Board
Section Package Description
TS8388BGL Pinout
Figure 5-1. TS8388BGL Pinout CBGA68 Package
VPLUSD
DVEE
VPLUSD
VPLUSD
DVEE
VPLUSD
Gorb
GAIN
VINB
Ball Index other side
CLKB
Diode
BOTTOM VIEW
TSEV8388B Evaluation Board
Rev. 2162C-BDC-01/04
Package Description
Table 5-1. TS8388BGL Description (CBGA68 Packaged Device)
Symbol DVEE
Number B10, E11, G11, K10, F10, A10, D10, H11, J11, C11, G10, H10, L10,
Function Ground pins. connected external ground plane. positive supply. analog negative supply. digital negative supply. phase analog input signal sample Hold differential preamplifier. Inverted phase clock input signal (CLK). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase Digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground (0V). gain adjust pin. gain default grounded, gain transfer function nominally close one. function temperature measurement asynchronous data ready reset active low, single ended input. +2.4V LVDS output levels otherwise GND(1) connected.
VINB(1) CLKB B0B, B1B, B2B, B3B, B4B, B5B, B6B, GORB
GAIN DIOD/DRRB
VPLUSD Note:
B11, C10, J10, A11,
common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Package Description
TS8388BF/TS8388BFS Pinout
Figure 5-2. TS8388BF/TS8388BFS Pinout CQFP68 Package
VIEW VPLUSD VPLUSD DVEE DVEE DVEE VPLUSD VPLUSD
index
VPLUSD GORB TS8388BF/TS8388BFS
VPLUSD Gain VINb VINb
Diode
CLKb
TSEV8388B Evaluation Board
CLKb
2162C-BDC-01/04
Package Description
Table 5-2. TS8388BF/TS8388BFS Description (CQFP68 Packaged Device)
Symbol VPLUSD DVEE VINB CLKB D0B, D1B, D2B, D3B, D4B, D5B, D6B, GORB Number 57(1) 40(1)
Function Ground pins. connected external ground plane. Digital positive supply compatibility, 2.4V LVDS compatibility).(2) positive supply. analog negative supply. digital negative supply. phase analog input signal Sample Hold differential preamplifier. Inverted phase analog input signal (VIN). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground (0V). gain adjust pin. This double function (can left open grounded used): DIOD: junction temperature monitoring pin. DRRB: asynchronous data ready reset function.
GAIN DIOD/DRRB
Notes:
Following numbers (CLK), (CLKB), (VIN) (VINB) have connected through resistor close possible package termination preferred option). common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Package Description
CBGA68 Thermal Characteristics
Thermal Resistance from Junction Ambient: Rthja following table lists converter thermal performance parameters device itself, with external heatsink added.
5.3.1
Table 5-3. Thermal Resistance
Flow (m/s) Estimated Thermal Resistance C/W) 35.8 30.8
Rthja (°C/W)
Figure 5-3. Thermal Resistance from Junction Ambient: Rthja
27.4 24.9 21.5 19.3 17.7
flow (m/s)
5.3.2
Thermal Resistance from Junction Case: Rthjc
Typical value Rthjc given 1.56° C/W. This value does include thermal contact resistance between package external component (heatsink PCBoard). example, 2.0° taken thermal grease.
5.3.3
CBGA68 Board Assembly with External Heatsink
recommended external heatsink PCBoard special design. Cooling system efficiency monitored using Temperature Sensing Diode, integrated device. Figure 5-4. CBGA68 Board Assembly
50.5
24.2
20.2 32.5
0.65 Note: Dimensions given Board
TSEV8388B Evaluation Board
2162C-BDC-01/04
Package Description
Nominal CQFP68 Although power dissipation this performance, heat sink mandatory. Thermal Characteristics user will find some advice this topics below.
Thermal Resistance from Junction Ambient: Rthja following table lists converter thermal performance parameters, with without heatsink. following measurements, heatsink been used (see Figure page Table 5-4. Thermal Resitance
Thermal Resistance C/W) CQFP68 Board Flow (m/s) Note: Estimated Without Heatsink 23.5 Targeted With Heatsink(1)
5.4.1
Heatsink glued backside package screwed pressed with thermal grease.
Figure 5-5. Thermal Resistance from Junction Ambient: Rthja
Rthja (°C/W) flow (m/s) With heatsink
Without heatsink
5.4.2
Thermal Resistance from Junction Case: Rthjc
Typical value Rthjc given 4.75° C/W.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Package Description
5.4.3
CBGA68 Board Assembly with External Heatsink
Figure 5-6. CQFP68 Board Assembly with External Heatsink
28.96 24.13 Printed circuit Aluminum heatsink 15.0 Interface: Af-filled epoxy thermal conductive grease max.
16.0
50.0
TSEV8388B Evaluation Board
2162C-BDC-01/04
Package Description
Enhanced CQFP68 Thermal Characteristics
Enhanced CQFP68 CQFP68 been modified, order improve thermal characteristics: heatspreader been added bottom package. been electrically isolated with substrate.
5.5.1
5.5.2
Thermal Resistance from Junction Case: Rthjc
Typical value Rthjc given 1.56° C/W. This value does include thermal contact resistance between package external component (heatsink PCBoard). example, 2.0° taken thermal grease.
5.5.3
Heatsink
recommended external heatsink, PCBoard special design. stand been calculated permit simultaneous soldering leads heatspreader with solder paste. Figure 5-7. Enhanced CQFP68 Suggested Assembly
28.78 24.13 Printed circuit board
heatspreader
Thermal
Solid ground plane
Cooling system efficiency monitored using Temperature Sensing Diode, integrated device.
2162C-BDC-01/04
TSEV8388B Evaluation Board
Package Description
Ordering Information
Part Number Package CQFP CQFP CQFP CQFP CQFP CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader CQFP with heatspreader Temperature Range Ambient Ambient High temperature 125° grade: grade: -40° 110° grade: -55° 125° grade: -55° 125° grade: -55° 125° grade: grade: -40° 110° grade: -55° 125° grade: -55° 125° grade: -55° 125° grade: -55° 125° Screening Level Visual inspection Visual inspection Standard Standard Standard Mil-PRF-38535, level Standard temperatures test (min, ambient, max) Standard Standard Standard Mil-PRF-38535, level Standard temperatures test (min, ambient, max) ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test ESA/SCC9000 Screening ESA/SCC qualified Level selection Acceptance Test Standard Standard DSCC 5962-0050401QXC DSCC 5962-0050401QYC Comments REQUEST ONLY (Please contact Marketing) REQUEST ONLY (Please contact Marketing)
Table 5-5. Ordering Information
JTS8388B-1V1B JTS8388B-1V2B TS8388BCF TS8388BVF TS8388BMF TS8388BMF TS8388BMF TS8388BCFS TS8388BVFS TS8388BMFS TS8388BMFS TS8388BMFS TS8388BMFS9NB2
TS8388BMFS9NB3
CQFP with heatspreader
grade: -55° 125°
TS8388BMFS9NC2
CQFP with heatspreader
grade: -55° 125°
TS8388BMFS9NC3
CQFP with heatspreader
grade: -55° 125°
TS8388BCGL TS8388BVGL
CBGA CBGA
grade: grade: -40° 110°
TSEV8388B Evaluation Board
2162C-BDC-01/04
Package Description
Table 5-5. Ordering Information (Continued)
Part Number TSEV8388BF TSEV8388BFZA2 Package CQFP CQFP Temperature Range Ambient Ambient Screening Level Prototype Prototype Comments Evaluation Board (delivered with heatsink) Evaluation Board with digital receiver (delivered with heatsink) Evaluation Board (delivered with heatsink) Evaluation Board with digital receiver (delivered with heatsink)
TSEV8388BGL TSEV8388BGLZA2
CBGA CBGA
Ambient Ambient
Prototype Prototype
5-10
2162C-BDC-01/04
TSEV8388B Evaluation Board
Section Schematics
TSEV8388B Electrical Schematics
Please, following figures.
TSEV8388B Evaluation Board
Rev. 2162C-BDC-01/04
Schematics
Figure 6-1. TSEV8388B Electrical Schematic
2162C-BDC-01/04
TSEV8388B Evaluation Board
Schematics
Figure 6-2. Board Digital Outputs Default Option
OUTb Digital data differential termination output connector
D7B, ORB,
Figure 6-3. Board Digital Outputs Option Using MC100EL16 Differential Receivers
D7B, ORB,
MC100EL
output connector OUTb
VEET
TSEV8388B Evaluation Board
2162C-BDC-01/04
Schematics
Evaluation Board Schematics
CBGA68 Option Figure 6-4. Component Side Description
6.2.1
Figure 6-5. Ground Plane
2162C-BDC-01/04
TSEV8388B Evaluation Board
Schematics
Figure 6-6. Power Supplies Planes
Figure 6-7. TSEV8388B Evaluation Board: Component Placement
TSEV8388B Evaluation Board
2162C-BDC-01/04
Schematics
6.2.2
CQFP68 Option
Figure 6-8. Component Side Description
Figure 6-9. Ground Plane
2162C-BDC-01/04
TSEV8388B Evaluation Board
Schematics
Figure 6-10. Power Supplies Planes
Figure 6-11. TSEV8388B Evaluation Board: Component Placement
TSEV8388B Evaluation Board
2162C-BDC-01/04
Schematics
2162C-BDC-01/04
TSEV8388B Evaluation Board
Atmel Corporation
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Chantrerie 70602 44306 Nantes Cedex France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue Rochepleine 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems.
ATMEL registered trademark Atmel Corporation. Other terms product names trademarks others. Printed recycled paper.
2162C-BDC-01/04
Other recent searches
STTA212S - STTA212S STTA212S Datasheet
SRP1205 - SRP1205 SRP1205 Datasheet
PCA2002 - PCA2002 PCA2002 Datasheet
NC7SZ27 - NC7SZ27 NC7SZ27 Datasheet
MMBTA14 - MMBTA14 MMBTA14 Datasheet
LTC3219 - LTC3219 LTC3219 Datasheet
EZC70DCWN - EZC70DCWN EZC70DCWN Datasheet
CHR2244 - CHR2244 CHR2244 Datasheet
2SC6065 - 2SC6065 2SC6065 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
