TECHNICAL NOTE TN-16 ADN2819 EVALUATION BOARD APPLICATION NOTE

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TECHNICAL NOTE TN-16 ADN2819 EVALUATION BOARD APPLICATION NOTE

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Introduction:
TECHNICAL NOTE TN-16
ADN2819 EVALUATION BOARD APPLICATION NOTE
This application note describes ADN2819 Evaluation board. ADN2819 multi-rate clock-recovery, data-retiming device based multi-loop architecture. ADN2819 recover clock data SONET OC3, OC-12, OC-48 Gigabit Ethernet data rates well 15/14 Forward Error Correction (FEC) these rates using single reference clock external crystal oscillator. ADN2819 evaluation board fabricated using standard FR-4 materials. high speed signal traces matched within length maintain characteristic impedance preserve signal integrity. ADN2819 Evaluation Board also used ADN2809 ADN2811.
Figure ADN2819 Evaluation Board (actual size)
Quick Start Guide: OC-48, Normal Operating Mode
Apply 3.3V supply vector pins "AVCC" "GND" Connect PIN/NIN pattern generator that supply differential input ADN2819 greater than 10mV. cables matching length. Connect CLKOUTP/N, DATAOUTP/N measurement equipment using cables matching length. switches S1-S9 should position*. This sets part OC-48, normal operating mode using onboard 19.44 crystal reference clock. Apply single-ended differential 2.48 Gb/s data stream ADN2819 inputs. recovered 2.48 clock re-timed data will present CLKOUTP/N DATAOUTP/N outputs respectively. *For "0", switch should right-most position shown picture Figure ADN2819 that populated with three-pin jumpers instead slide switches, jumper should placed left-most pins "0". board shipped after April 2002 will populated with jumpers instead switches.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703
REV. 0.2, Apr. 2002
TECHNICAL NOTE -HSN TN-16
ADN2819 EVALUATION BOARD APPLICATION NOTE
Power Supply
ADN2819 Evaluation board requires single 3.3Volt nominal supply basic operation. This supply brought board through vector pins, AVCC GND, center board. evaluation board shipped configured single supply through jumpers JP1-JP4, which populated with ferrite beads. these ferrite beads removed, seperate 3.3V supplies must applied vector pins labelled DVCC DRVCC. This allows user seperate analog supply, digital supply output driver supply from each other, though required. 100ohm differential source impedance. this termination required, (e.g. refclk being driven single-ended clock oscillator), should removed. external reference clock frequency selected REFSEL0, REFSEL1 switches S5-S6 (see table
Data Rate Selection
input data rate ADN2819 selected SEL0, SEL1, SEL2 switches S2-S4 (see Table ADN2819 programmed acquire OC-3 (155.52Mbps), (166.6Mbps), OC-12 (622.08Mbps), OC-12 (666.5Mbps) OC-48 (2.488Gbps), OC-48 (2.665Gbps), Gigabit Ethernet (1.25Gbps) Gigabit Ethernet (1.339 Gbps)
TABLE Reference Freq Selection REFSEL1 REFSEL0 Applied Ref. Freq. 19.44 38.88 77.76 155.52
Loop Filter Capacitor
loop filter capacitor, connected between pins recommended capacitor parameters shown Table ADN2819 eval board uses leakage 4.7uF capacitor.
TABLE Data Rate Selection SEL2 SEL1 SEL0 Rate Freq OC48 2.48832 1.25 OC12 155.5 OC48*15/14 2.666 GbE*15/14 1.339 OC12*15/14 666.5 OC3*15/14 166.6
TABLE Recommended Spec Parameter Value Capacitance (-40C 85C) 4.7uF Leakage (-40C 85C) 80nA Rating 6.3V
PIN/NIN Inputs
PIN/NIN inputs brought onto ADN2819 evaluation board through connectors Capacitors provide coupling on-chip termination resistors. When coupling inputs outputs ADN2819, care must taken when choosing your coupling capacitor values. time constant formed with resistors signal path must considered. Also, when large number Consecutive Identical Digits (CID's) applied, capacitor voltage droop, causing pattern dependent jitter. designers ADN2819 have done thorough investigation OC48 datarates came following conclusion. Assuming that 1000 CID's must tolerated, minimum capacitor 1.6uF PIN/ NIN, 0.1uF DATAOUTP/DATAOUTN should used. ADN2819 evaluation board shipped with 1.8uF capacitors positions optimize performance OC-3 datarate.
Reference Clock
ADN2819 on-chip crystal oscillator which used with 19.44MHz external crystal resonator series resonant mode. When REFSEL "0", crystal oscillator used supply reference frequency. external clock oscillator other external reference clock used, REFSEL external reference clock brought either differentially single-ended REFCLKP/N pins.When configured external reference clock ADN2819 XTAL oscillator disabled populating with 1kOhm pull-up resistors. ADN2819 accept following reference clock frequencies: 19.44MHz, 38.88 77.76 LVTTL/LVCMOS/LVPECL/LVDS levels 155.52MHz LVPECL/LVDS levels REFCLKN/P inputs. reference clock frequency selected independent data rate. Only single reference clock rate needs selected ADN2819 operate over data rates. Setting REFSEL switch disconnects onboard 19.444MHz crystal oscillator selects external reference clock inputs, REFCLKN/P connectors REFCLKN/P accepts differential signal with peak peak differential voltage level greater than 200mV (e.g. LVPECL LVDS), single-ended LVTTL LVCMOS input. REFCLK inputs high impedance, however, eval board there 100ohm resistor, placed across REFCLKP REFCLKN provide differential 100ohm termination case REFCLK inputs being driven REV. 0.2, 2002
Clock/Data Outputs
CLKOUTP CLKOUTN brought through 0.1uF coupling caps connectors respectively. DATAOUTP DATAOUTN brought through 0.1uF coupling caps connectors J10, respectively.
SLICEP/SLICEN
SLICE allows ADN2819's input quantizer decision level adjusted accommodate (amplified spontaneous emission) fiber amplifier applications. slicing level adjusted 100mV applying differential input voltage 800mV SLICEP/SLICEN. SLICEP SLICEN inputs brought onto ADN2819 evaluation board through connectors respectively. When being used, SLICEN/ SLICEP inputs should tied using jumpers.
TECHNICAL NOTE -HSN TN-16
ADN2819 EVALUATION BOARD APPLICATION NOTE
(Loss Lock)
ADN2819 lock detector monitors frequency difference between reference clock. "Loss Lock" (LOL) signal de-asserted when within 500ppm center frequency. frequency error between input data rate selected data rate then drifts more than 0.1% (1000 PPM), output will asserted. provides visual indication status, will turn when part lost lock. output LVTTL compatible shows lock status frequency detector loop. Loss lock output brought test point labelled "LOL".
TEST MODES Test Data Inputs, TDINN/TDINP
Test Data inputs, TDINP TDINN, facilitate external quantizer/limiting amplifier bypassing ADN2819's input quantizer provide direct input clock recovery circuit. Test Data inputs TDINP TDINN brought onto ADN2819 evaluation board through connectors respectively. Test modes enabled using LOOPEN BYPASS These LVTTL/CMOS compatible logic inputs. Switches used BYPASS LOOPEN respectively. Table complete list Test Modes.
SDOUT (Signal Detect Output)
SDOUT/LOS uses peak detection circuitry determine input data quantizer above threshold THRADJ resistor R30. SDOUT output LVTTL compatible. provides visual indication SDOUT status, turns when "loss signal" condition detected. SDOUT also brought test point labelled "SDOUT".
BYPASS Mode
Asserting BYPASS input through BYPASS switch connects output quantizer directly data output buffers, bypassing clock recovery circuit. This affects only data output circuitry. clock output remains connected clock recovery circuit continues output valid clock input data rate valid.
Squelch
When "Squlech" input, driven high, both clock data outputs zero state. Switch provided drive Squelch high low. Squelch function required, Squelch should driven low.
LOOPEN Mode
Asserting Loop Enable input through LOOPEN switch connects test data inputs TDINP, TDINN through input multiplexer clock recovery circuit. This function used testing clock recovery functionality well configuring ADN2819 with external limiting amplifier/quantizer.
TABLE ADN2809 Operation Modes LOOPEN BYPASS FUNCTION Normal Operation BYPASS Mode LOOPEN Mode
REV. 0.2, 2002
TECHNICAL NOTE -HSN TN-16
ADN2819 EVALUATION BOARD APPLICATION NOTE
Figure Silkscreen Layer
Figure Layer
Figure Ground Plane
Figure Bottom Layer
Figure Power Plane
REV. 0.2, 2002
TECHNICAL NOTE -HSN TN-16
ADN2819 EVALUATION BOARD APPLICATION NOTE
REV. 0.2, 2002
TECHNICAL NOTE -HSN TN-16

TECHNICAL NOTE TN-16 ADN2819 EVALUATION BOARD APPLICATION NOTE

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