Detailed Description Projected Impact: Freescale Semiconductor, I

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Detailed Description Projected Impact: Freescale Semiconductor, I

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MPC185HWRM Timing Explanation 4/2004
Detailed Description Projected Impact:
Freescale Semiconductor, Inc.
Previous revisions PPC185 internal noise sensitivity which caused internal lose synchronization, immediately lock This lock generally leads host generating Machine Check Error, board which operating lock well. address this errata, both package silicon PPC185 were redesigned eliminate noise sensitivity. first silicon incorporate these changes PPC185VFB. Initial testing determined that PPC185VFB longer exhibited Lock errata, device made available customer orders. Recent testing determined that PPC185VFB's still affected worst case switching noise, with noise manifesting itself jitter. This jitter reduced running MPC185's 1.8v (the Vdd, APLL), however voltage must tightly controlled (+/-2.5%) minimize noise sensitivity while meeting long term reliability requirements. With higher voltage, jitter reduced, eliminated, because this jitter have positive negative effect timing each clock edge, worst case jitter cause timing failures boards designed account worst case jitter 3.3V systems 1.9ns 2.5V systems 0.85ns. consequence 185's jitter, Motorola issuing following revised timings. These timings indicate maximum operating frequency 66MHz PowerQUICC systems. also recommended that PowerQUICC systems, `PLL Range' F15, should connected Ovdd, indicating that operating 33-66MHz range. MPC185 users requested contact their Motorola sales/FAE organization schedule calls with Product Team discuss impact this errata their programs.
Timing Characteristics
Table shows timing specifications with PowerQUICC timings assume 40-pF load.
More Information This Product, www.freescale.com
Table Electrical Characteristics PowerQUICC
Condition Power supply voltage-Core Power supply voltage-I/O Power supply voltage-PLL Clock frequency Clock cycle time Clock-to-signal valid delay Clock-to-signal hold Name VDDQ VPLL Fclock tKHKH tKHQV tKHQX tDVKH tKHDX 1.45 1.75 15.15 1.65 1.85 Unit
Freescale Semiconductor, Inc.
Input setup time clock-bused signals Input hold time clock
Table shows timing specifications with MPC107 other bridge/memory controller. timings assume 15-pF load.
Table Electrical Characteristics Bridge/Memory Controller
Condition Power supply voltage-Core Power supply voltage-I/O Power supply voltage-PLL Clock frequency Clock cycle time Clock-to-signal valid delay Clock-to-signal hold Input setup time clock-bused signals Input hold time clock Name VDDQ VPLL Fclock tKHKH tKHQV tKHQX tDVKH tKHDX 1.45 1.75 0.95 1.65 1.85 Unit
MOTOROLA
More Information This Product, www.freescale.com

Detailed Description Projected Impact: Freescale Semiconductor, I

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