PIC18F6310/6410/8310/8410 Rev. Silicon Errata PIC18F6310/6410/831

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PIC18F6310/6410/8310/8410 Rev. Silicon Errata PIC18F6310/6410/831

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PIC18F6310/6410/8310/8410
PIC18F6310/6410/8310/8410 Rev. Silicon Errata
PIC18F6310/6410/8310/8410 Rev. parts have received conform functionally Device Data Sheet (DS39635A), except anomalies described below. issues listed here will addressed future revisions PIC18F6310/6410/8310/8410 silicon. following silicon errata apply only PIC18F6310/6410/8310/8410 devices with these Device/Revision IDs: Part Number PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410 Device 1011 0110 1101 0110 Revision 00011 00011 00011 00011
Module: MSSP
current implementation, I2CMaster mode operates follows: Baud Rate Generator Master mode slower than rates specified Table 16-3 Device Data Sheet. this revision silicon, values shown Table place those shown Table 16-3 Device Data Sheet. differences shown bold text. following formula place shown Register 16-4 (SSPCON1) Device Data Sheet description SSPM3:SSPM0 1000. SSPADD INT((FCY/FSCL) (FCY1.111 MHz))
Device (DEVID1 DEVID2) located addresses 3FFFFEh:3FFFFFh device's configuration space. They shown hexadecimal format "DEVID2 DEVID1".
TABLE
FOSC Note
I2CCLOCK RATE w/BRG
FCY*2 Value FSCL Rollovers BRG) kHz(1) 312.5 kHz(1) kHz(1) MHz(1)
I2Cinterface does conform specification (which applies rates greater than kHz) details, used with care where higher rates required application.
2004 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410
Module: MSSP
When MSSP configured SPIMaster mode, cannot disabled setting TRISC<5> bit. always outputs content SSPBUF regardless state TRIS bit. Slave mode with Slave Select enabled, SSPM3:SSPM0 0010 (SSPCON1<3:0>), disabled placing logic high level (RF7). Work around None.
Module:
10-bit Addressing mode, when Repeated Start issued followed high address byte write command, issued. Work around There workarounds available: Single-Master Environment: single-master environment, user must issue Stop, then Start, followed write address high, then address followed data. Multi-Master Environment: multi-master environment, user must issue Repeated Start, send dummy write command different address, issue another Repeated Start then send write original address. This procedure will prevent loss bus.
Module: MSSP
After transfer initiated, SSPBUF register written before additional writes blocked. data transfer corrupted SSPBUF written during this time. WCOL time SSPBUF write occurs during transfer. Work around Avoid writing SSPBUF until data transfer complete, indicated setting SSPIF (PIR1<3>). Verify WCOL (SSPCON1<7>) clear after writing SSPBUF ensure potential transfer progress corrupted.
Module:
CCP1 CCP2, configured mode with Timer2 prescaler duty cycle period minus result output(s) remaining logic level. Clearing register select fastest period also result output(s) remaining logic output level. Work around ensure reliable waveform, verify that selected duty cycle does equal 10-bit period minus prior writing these locations, 1:16 Timer2 prescale. Also, verify register written 00h. other duty cycle period settings will function described Device Data Sheet. modules remain capable 10-bit accuracy.
Module: MSSP
RCEN becomes when system Idle. normal operation, setting RCEN should ignored module while system Idle. Work around Wait system become Idle. This requires check following bits reset: ACKEN, RCEN, PEN, RSEN SEN.
DS80206A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Module:
offset greater than specified limit Table 26-25 Device Data Sheet. additional Parameter A06A updated conditions limits shown bold text Table Work around Three workarounds exist. Configure VREF+ VREFpins voltage references. This done setting VCFG<1:0> bits (ADCON1<5:4>). Perform conversion known voltage reference voltage adjust result software. Increase system clock speed adjust settings accordingly. Higher system clock frequencies decrease offset error.
TABLE
CONVERTER CHARACTERISTICS: PIC18F6310/6410/8310/8410 (INDUSTRIAL) PIC18LF6310/6410/8310/8410 (INDUSTRIAL)
Characteristic Offset Error Offset Error <±1.5 <±-3.5 Units Conditions VREF VREF+ VREFVREF
Param Symbol A06A EOFF EOFF
Module: AUSART
Back-to-back reception AUSART does work reliably framing error that occurs when bytes sent consecutively. Transmission from AUSART affected; therefore, application microcontroller that sends serial stream data AUSART should work expected. Work around When possible, delay between byte transmissions microcontroller. Using Stop bits alleviates issue.
Module: Timer1/Timer3
When Timer1 Timer3 configured external clock source CCPxCON register configured with 0x0B (Compare mode, trigger special event), timer reset Special Event Trigger. Work around Modify firmware reset Timer registers upon detection compare match condition TMRxL TMRxH.
Module: Timer1
When Timer1 External Clock Synchronized mode external clock period between TCY, interrupts will occasionally skipped. Work around Avoid using external clock with period frequency) between TCY.
Module: External Memory
should when ~EBDIS while external memory accessed. Work around None.
2004 Microchip Technology Inc.
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Clarifications/Corrections Data Sheet:
Device Data Sheet (DS39635A), following clarifications corrections should noted. None.
DS80206A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
REVISION HISTORY
Document (8/2004) First revision this document which includes silicon issues (MSSP), (PWM), (CCP), (A/D), (AUSART), (External Memory Bus), (Timer1/ Timer3) (Timer1).
2004 Microchip Technology Inc.
DS80206A-page
PIC18F6310/6410/8310/8410
NOTES:
DS80206A-page
2004 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2004 Microchip Technology Inc.
DS80206A-page
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08/24/04
DS80206A-page
2004 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 Rev. Silicon Errata PIC18F6310/6410/831

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