Vast resources have been expended semiconductor industry trying build

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Application Note Using Nonvolatile Static RAMs
Vast resources have been expended semiconductor industry trying build nonvolatile random access read/write memory. effort been undertaken because nonvolatile offers several advantages over other memory devices DRAM, Static RAM, Shadow RAM, EEPROM, EPROM which were developed meet specific applications needs. Characteristics ideal nonvolatile are: power consumption, high performance, high reliability,
high density, cost, ability used semiconductor memory application. While various memory components designed date meet ideal memory scenario, each excels meeting more sought after attributes (Figure
MEMORY ATTRIBUTES Figure
EASE INTERFACE NONVOLATILE PERFOR- MANCE READ/ WRITE DATA RETENTION
COST DRAM STATIC SRAM PARTITIONABLE SRAM PSEUDO STATIC FLASH EEPROM EPROM EPROM
DENSITY
Degree excellence
TYPES MEMORY
Many types memories have been devised meet varying application needs. However, nonvolatile read/ write random access memories substituted memory types independent application, cost primary consideration.
DRAM: Dynamic Random Access Memory. DRAM, similar SRAM, stores information SRAM, this information stored four transistor flip-flop which easy address, requires relatively large memory cell. DRAM, comparison, stores charge small capacitor, requir-
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much more current then SRAM maintain stored data. memory cell size smaller DRAM than SRAM, total cost memory less. DRAM's capacitors must constantly refreshed that they retain their charge. DRAMs require more sophisticated interface circuitry. SRAM: Static Random Access Memory. SRAM essentially stable flip-flop requiring clock timing refreshing. contents SRAM memory retained long power supplied. SRAMs support extremely fast access times. SRAMs also have relatively strict timing requirements parallel address structure, making them particularly suited cache other low-density, frequent-access applications. SRAM: Nonvolatile Static Random Access Memory. SRAM single package which contains low-power SRAM, nonvolatile memory controller, lithium type battery. When power supply this single modular package falls below minimum requirement maintain contents SRAM, memory controller module switches power supply from external source internal lithium battery write protects SRAM. These transitions from external power source transparent SRAM, making true nonvolatile memory. This unique construction combines strategic advantages SRAM-addressing structure, high- speed access, timing requirements-with nonvolatility advantages EEPROM technologies. Battery-backed SRAM modules from Dallas Semiconductor pin-compatible with non-battery-backed SRAMs, making them ideal application where traditional SRAM would suitable. PSEUDO STATIC RAM: Pseudo Static Random Access Memory. advantages using Static simplicity interface circuitry required, fact that device nature "static," requiring periodic refreshing retain data. DRAM, however, provides lower cost-per-bit advantages higher memory density. Pseudo-static combines advantages SRAM DRAM using dynamic storage cells retain memory, placing required refresh logic on-chip that device functions similarly SRAM. FLASH: flash memory combines electrical erase capability EEPROM with cell that similar EPROM. result that modified cell
block erased electrically instead with light. This feature allows Flash memory accept code updates information while functioning system. EEPROM: Electrically Erasable/Programmable Read Only Memory. significant disadvantage EPROM memory fact that cannot reprogrammed while system. EPROM requires external programming device receive code data. EEPROM eliminates this problem providing write function which used while EEPROM still circuit. tradeoff obtaining write function while EEPROM still circuit having provide high voltage (12.5V above) source EEPROM when writing data, buying more expensive EEPROM which charge pump package that allows used with standard input. Although nonvolatile, EEPROM memory cells exhibit slow read/write access rates, making them most suitable systems where performance issue. other read/write capable memories listed Figure provide ability frequently read write data continuously over their entire lifetimes, excess years, while EEPROM memory cells rarely rewritten more than 10,000 times. EEPROM placed system accessed standard RAM. EPROM: Electrically Programmable Read Only Memory. EPROM nonvolatile memory which offers ability both program erase contents memory multiple times. EPROM must programmed using 12.5 volt higher) PROM programmer, then transferred into system which intended function. EPROMs erased shining ultraviolet light into window package. process writing data into EPROM then erasing repeated almost indefinitely. EPROMs usually used product development, later replaced with less expensive one-time programmable EPROMs. EPROM: One-Time Programmable EPROM. EPROM which only written with code/data once instead multiple times. Generally, EPROMs less expensive then erasable EPROMs. ROM: Mask Programmable Read Only Memory. Mask programmable ROMs most durable form memory storage. They are, however, "read only" offer fairly slow performance. design code/data that very stable will need changed, custom mask made which will sig-
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nificantly reduce cost ROM. drawback using mask significant cost penalty that must incurred error code/data being stored forces mask change. EPROM fills between applications changes) EPROMs (frequent changes).
Finally, because complexity programming circuits, cell structure special process technology required, density EEPROMs kept with industry demands. systems requiring store-and-forward data, memory must provide desired fast write cycle well protection data event power loss. Despite promise such memory device effort invested industry, ideal memory remains elusive. more nearly emulate ideal memory, Dallas Semiconductor combines intelligent CMOS control circuitry (DS1210), lithium energy source, very power SRAM offer high density, nonvolatile memory. Five devices, including DS1220 DS1225 DS1230 (32K DS1245 (128K DS1250 (512K this fusion technologies provide nonvolatile random access memory solution densities 4096K bits. CMOS SRAMs currently available have read write cycle times which exceeds most system requirements. They much more robust than EEPROM, because there wear-out mechanism write cycle limitation. SRAMs also easiest interface because pinout configurations standard throughout industry. fact, bytewide SRAMs interfaced directly microprocessors (Figure addition, CMOS SRAMs offer power both active standby modes, characteristic sought many designers. most designs, memories remain standby much time, keeping power consumption negligible. standby mode, current drain consists only leakage currents tens nanoamperes.
MEETING APPLICATIONS NEEDS
NMOS DRAM memory provides performance density, but, down side, must constantly refreshed retain data. opposite extreme ROMs, offering nonvolatility density, lacking ability updated with data because information programmed only once. Between these wide range devices that fulfill some characteristics ideal memory. popular devices, EEPROMs Shadow RAMs, designed emulate static also have ability retain data after power loss. despite their capability retain data, both EEPROMs Shadow RAMs fall short meeting industry's needs several reasons. Most notably, EEPROM requires special slow write cycle. EEPROM's inability support standard write cycle rates hinders performance applications where memory updated immediately data available. Another problem with EEPROMs their wear-out mechanisms. These raise longevity concerns limited number write cycles allowed sometimes 10,000. static with cycle time this limitation, would wear mere application that requires constant updating, such buffer memory cashier's checkout terminal printer, EEPROM's wear mechanism acceptable.
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BYTEWIDE MICROPROCESSOR INTERFACE Figure
WRITE READ MEMORY CYCLE MICRO- PROCESSOR DECODER ADDRESS DATA CMOS
BYTEWIDE MEMORIES PROVIDE EASY INTERFACE MICROPROCESSORS BECAUSE ORGANIZATION CONTROL SIGNAL DEFINITION.
PUTTING LITHIUM TOGETHER
minute leakage currents modem CMOS SRAMs sustained with backup energy source yield most attractive nonvolatile memory. However, actual solution involves more than just CMOS memory back energy source (see Figure Battery backup design schemes many varied. increase density availability low-power CMOS memories recent years made this approach even more attractive. problems still exist with battery backup design battery packaging lack appropriate standard components implement support circuitry. problem providing isolation between battery power supply (see Figure Diodes provide isolation produce voltage drop which requires nonstandard power supplies also subtracts from battery voltage. second problem that circuitry must powered from battery. Unless these devices draw extremely modest amount current, battery selection changes drastically. fact, current drain even couple
microamperes dictates either rechargeable batteries replaceable battery scheme. rechargeable batteries selected, recharging circuit costly complex, best rechargeable battery cannot compare with electrochemical stability lithium primary cell. Even worse, replaceable batteries maintenance cost in-service system. Battery packaging also been serious limitation, taking valuable space requiring special handling consideration prevent discharge. Dallas Semiconductor overcomes these obstacles using high-capacity, non-rechargeable lithium batteries battery backed SRAMs.
ENERGY SOURCE
energy source used retain data memory must capable outlasting usefulness product. Dallas Semiconductor SRAM products extremely stable electrochemical system with enough energy guarantee shelf life greater than years.
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BATTERY BACKUP CIRCUIT Figure
CMOS STATIC
CMOS STATIC REQUIRES MORE THAN JUST BACKUP POWER SUPPLY. DATA MUST ALSO PROTECTED DURING POWER TRANSIENTS AVOID GARBLED DATA.
POWER SUPPLY BATTERY ISOLATION CIRCUITRY Figure
REGULATOR
CMOS STATIC
SUPPORT CIRCUITRY REQUIRED PRODUCE POWER FAIL DETECTION WRITE PROTECTION FORCES NEED MULTICELL RECHARGEABLE BATTERY LITHIUM BATTERY.
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LITHIUM BATTERY BACKUP MORE RELIABLE
lithium energy cell raised concern about reliability been object much study. Data taken energy cell used Dallas Semiconductor SRAMs indicates cell failure rate less than 0.5% 55°C over year period. Additional life studies taken same lithium energy source encapsulated Dallas Semiconductor's SRAMs have produced failures over million device hours 85°C. lithium energy cell, then, ideal commercial industrial semiconductor applications.
memory substituting Dallas Semiconductor SRAM Static memory.
IN-CIRCUIT PROGRAMMABILITY
advantages SRAM related capability software. Modern systems seek customization cost standard product. this aspect, software adapted system perform specialized functions. even possible totally modify system personality over telephone. In-circuit programming also reduces maintenance cost eliminating service calls update software. Software stored SRAM updated often necessary, depending configuration application system.
RETROFITTING EXISTING DESIGNS
pinout Dallas Semiconductor SRAMs established industry standard (Figure Joint Electronic Devices Engineering Council's Bytewide Version Standard defines upgrades from density 128K This standard accommodates RAM, ROM, EPROMs, EEPROMs. Because flexibility upgradeability bytewide memories, number existing sockets hundreds millions. Therefore, many system designs accommodate direct replacement RAMs, EPROMs, ROMs, EEPROMs with Dallas Semiconductor SRAMs. These solutions real-time programmability and/or density upgrades existing systems without redesign. Real-time programmability gives system ability personalized user. other words, SRAMs retrofitted into existing designs without making changes existing hardware. This retrofitting offers cost-effective, practical solution companies have invested other memory devices that less than ideal their needs. example, design using conventional static upgraded nonvolatile
PORTABLE APPLICATIONS
advancement high density, low-power portable computers continuing drive development requirements. Difficult interface circuitry refresh requirements DRAM memories make them unsuitable such applications. SRAMs only easier address consume less power when operating, also require very little power maintain contents their memory. Even better, SRAM provide high performance DRAM SRAM also guarantee that memory truly nonvolatile. When portable needs standby mode, memory powered down altogether.
MBYTE MEMORY SUBSYSTEM USING SRAMs
Figure shows system block diagram with Intel 386SL microprocessor with megabyte main memory 128K SRAMs (DS1245). Figure Portable Applications: Intel 386SL CPU/NV SRAM Timing, shows requisite timing memory subsystem. Intel 386SL many microprocessors specially designed power, portable applications, addressing SRAM memory.
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PORTABLE APPLICATIONS: INTEL 386SL CPU/NV SRAM TIMING Figure
MA[10:0] ADDRESS COLUMN ADDRESS COLUMN ADDRESS
MD[15:0]
DATA
DATA
PAGE MISS
PAGE
MBYTE MEMORY SUBSYSTEM USING SRAMS Figure
CE[3:0] A[17:11] CE3# CE2# CE1# CE0#
MA[10:0] A[10:1] A[17:1]
128K
128K
128K
128K
DS1245
DS1245
DS1245
DS1245
WLE#
OLE#
128K
128K
128K
128K
DS1245
DS1245
DS1245
DS1245
WHE#
OHE#
MD[15:0]
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Figure eight DS1245 SRAMs used create four-bank 1Mbyte SRAM memory subsystem. following signals from Intel 386SL required address SRAM module based system. (The 386SL memory controller must configured SRAM addressing mode this application.) Latch Enable. This signal active high serves indicate that address address bus. address must latched this signal's falling edge. connected latch enable input address latch. MA[10:0]: Multiplexed Memory Address Bus. This provides address information Memory Controller Unit. provides address multiplexed row/column sequence. CE[3:0]: Chip Enable outputs. These signals provide chip enable control each SRAM bank.
WLE: Write Enable. Indicates write access lower byte 386SL memory bus. lower byte data memory falling edge WLE. WHE: Write High Enable. Indicates write access high byte 386SL memory bus. high byte data memory falling edge WHE. OLE: Output Enable. Enables lower byte output from SRAM modules. OHE: Output High Enable. Enables high byte output from SRAM modules. MD[15:0]: Memory Data Bus. This provides data information Memory Controller Unit. Accesses from Memory Controller Unit SRAM memory modules take place through this bus.
16-BIT SINGLE-BANK SRAM BIOS CIRCUIT Figure
128K DS1245 ROMCS0# MEMR# FROM mprocessor MEMW# SA[16:0] ADDR
DATA
XD[15:8]
128K DS1245
DATA ADDR
XD[7:0]
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16-BIT SINGLE-BANK SRAM BIOS CIRCUIT
Figure shows Dallas SRAMs providing BIOS memory storage Intel 386SL CPU. Using DS1645 SRAMs provides several advantages over using either EPROM FLASH memories. Flash memories require more operating current than SRAMs. Flash memories also require high voltage source, 12V+, writes updates that must made BIOS. SRAMs, other hand, require only their standard input both read write access. Like Flash memories, DS1645 SRAM maintains contents memory absence VCC. DS1645 additional feature that easily programmed write protect user-selected blocks memory. effect, individual memory blocks SRAM module configured appear memory, without detracting from DS1645's ability receive BIOS updates non-write-protected blocks memory. Traditional EPROMs, while nonvolatile very low-power like DS1245 SRAMs, lacking that they only programmed once, usually require special fixture programmed. DS1245 SRAMs provide capability update BIOS repeat-
edly without removing them from system. DS1245 SRAMs also provide fast access times, negating need insert additional wait states into BIOS access timing requirements. signals shown Figure taken directly from Intel 386SL CPU: ROMCSO#: This signal dedicated control signal provided 386SL CPU. active used enable system BIOS. MEMR#: Memory Read. This signal indicates when memory read access occurring active low. MEMW#: Memory Write. This signal indicates when memory write access occurring active low. XD[15:0]: X-bus Data. Buffered data lines from system data bus. These signals produced using external transceiver (see Intel 386SL Superset System Design Guide). SA[16:0]: System Address Bus. This driven 386SL system accesses.
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DATA LOGGING Figure
INTEL 8088 8086
DT/R
AD15
LATCH
ADDRESS
TRANSCEIVER DATA
SRAM (DATA LOG)
SRAM (BIOS)
CONVERTER
DS1225
DS1225
ANALOG INPUT
DATA LOGGING
Figure shows Dallas Semiconductor's SRAMs provide special advantage environments where power supply entirely reliable, when power must periodically shut down. Dallas Semiconductor SRAMs contain memory control circuitry which only maintains data SRAM absence power, also write protects device tolerance. This feature ensures that unstable power supply does corrupt data which been collected. this application, Intel 8086 shown minimal mode, connected address latch transceiv-
demultiplex 8086's (see Figure resulting address data busses then connected directly memory banks, BIOS memory consisting DS1225 SRAMs, other memory bank consisting DS1225's acting data log. data collecting device, such converter, addressed read-only peripheral device sample value write DS1225 acting data log. DS1225s acting data transmit their data data another peripheral, removed from system taken another location have extracted.
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DALLAS SEMICONDUCTOR BATTERY BACKUP SRAM MODULES Figure
DS1220 DS1225 DS1230
DS1245 128K
DS1250 512K
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