DUAL PORT PORT PORT 030698 Memory devices systems diversifyi

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DUAL PORT PORT PORT 030698 Memory devices systems diversifyi

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Application Note Dual Port
DUAL PORT PORT PORT
030698
Memory devices systems diversifying becoming more complex necessity support information processing needs. need centralize data storage multiprocessor applications challenges both hardware software designers. ways must found that consolidate system information that controllable more than bus. addition, systems becoming more power conscious, particularly portable systems they typically rely some kind rechargeable battery power. systems where shared access requirements infrequent, require many megabytes memory transferred, shared mass storage device such floppy disk drive networked hard disk drive suffice. However, frequent, density access, media such hard drives floppy diskettes impractical would greatly slow rate which data could stored retrieved. DS1609 Dual Port been specifically designed able meet high frequency, volume data storage retrieval between asynchronous systems. With ability operate voltages volts, DS1609 also fits easily into portable application where power availability limited.
DESCRIPTION
AD0-AD7 VOLT SUPPLY GROUND PORT ADDRESS/DATA PORT ENABLE OUTPUT ENABLE WRITE ENABLE
type which connected either port DS1609 limited system level. multiplexed microprocessor address data connected directly either both ports DS1609. device controlled from either port separately only three signals, obvious disadvantage multiplexed slightly reduced system performance because address data information being transmitted serially. equally obvious advantage reduced count achievable multiplexing addressing data buses. Read/Write access either port transferred bits address, followed bits data. read cycle port, inactive, cycle initiated when goes active, which with address latched, data retrieved under control rising edge either terminates read cycle. write cycle, inactive, becoming active latches address accessed, with becoming active. DS1609 dual port special cell design that allows simultaneous accesses from ports. Because this cell design, arbitration required read cycles occurring same instant. However, argument arbitration made reading writing cell exact same instant write from both ports same instant. write cycle occurs while read cycle progress, read cycle will likely recover either data data some combination both. However, write cycle will update memory with correct data. Simultaneous write cycles same memory location pose additional concern that cell contention causing metastable state. Depending timing write cycles port port memory location could left containing data written from port data from port some combination thereof. However, both concerns expressed above eliminated disciplined system software design. simple assure that read/write contention does occur perform redundant read cycles. Write/write contention needs avoided assigning groups addresses
ASSIGNMENT
PORT AD7A AD6A AD5A AD4A AD3A AD2A AD1A AD0A PORT AD0B AD1B AD2B AD3B AD4B AD5B AD6B AD7B
DS1609 (600 mil)
PORT AD7A AD6A AD5A AD4A AD3A AD2A AD1A AD0A
PORT AD0B AD1B AD2B AD3B AD4B AD5B AD6B AD7B
DS1609S SOIC (300 mil) 030698
write operations port only. Groups data assigned check bytes which would guarantee correct transmission. software arbitration system using "mail box" pass status information also employed. Each port could assigned unique byte
writing status information which other port would read. status information could tell reading port activity progress indicate when activity going occur.
DS1609 DUAL PORT INTERFACE INTEL 8086 MICROPROCESSOR Figure
AD0-7
SYSTEM DECODER
8086
PORT AD7A AD6A AD5A AD4A AD3A AD2A LOCK/(WR) AD1A AD0A DS1609
PORT AD0B AD1B AD2B AD3B AD4B AD5B AD6B AD7B ADDRESS/DATA 030698
DS1609 ideally suited small microprocessor based systems which frequently utilize dedicated multiplexed address/data busses following examples deal with interfacing with Intel 8086/8088 series Motorola HC11 series microprocessors. implementation with Intel 8086/8088 microprocessor family, address/data pins either port tied directly lower address data lines Intel 8086 8088 microprocessor (Figure from microprocessor provides input port DS1609, while provides
port. port's input conditioned system decoder, which would require 8086's output input provide address latching. Several unused address/data lines from 8086 would also required inputs indicate where DS1609 resides system memory map. applications where multiple DS1609 ports required, multiple outputs could provided from system decoder using signal from Intel 8086/8088 with user specified address lines generate multiple chip selects (Figure
MOTOROLA HC11 EXPANDED MODE Figure
HC11
PORT AD7A AD6A AD5A AD4A AD3A AD2A AD1A AD0A SYSTEM DECODER DS1609
PORT AD0B AD1B AD2B AD3B AD4B AD5B AD6B AD7B ADDRESS/DATA
implementation with Motorola HC11 microprocessor family, address/data pins either port DS1609 directly ties port HC11 operating expanded mode (Figure Address pins from port HC11 A15) used provide DS1609's location system memory map. signal, which also input HC11, provides clock system decoder indicating whether HC11 address data cycle. input decoder indicates whether HC11 writing reading data data cycle. From these inputs, sys-
decoder provide outputs DS1609. applications where more density required, DS1609's used. same inputs, including user selected combination address lines used provide multiple signals individual DS1609 devices (Figure DS1609 used with other microprocessors without multiplexed busses, which have separate address data bus.
030698
MULTIPLEXED INTERFACE Figure
INTEL 8086/8088 AD15 AD14 AD13 AD12 AD11 AD10 PORT DS1609 DS1609 PORT ADDRESS/DATA
PORT
PORT
MOTOROLA HC11 EXPANDED MODE MULTIPLE DS1609'S Figure
HC11
PORT
DS1609 DS1609
PORT
SYSTEM DECODER
030698
ADDRESS/DATA
ADDRESS/DATA
ADDRESS/DATA
DS1609 used between with non- multiplexed microprocessors such Intel Motorola 68030. Processor cycles from
DS1609 must then multiplexed specifically DS1609's address/data/bus. example implementation shown below (Figure
SAMPLE IMPLEMENTATION; NON-MULTIPLEXED Figure
ADDRESS/DATA
NON-MULTIPLEXED EXTERNAL MICROPROCESSOR
PORT DS1609 PORT
this implementation, lower bits microprocessor's address data connected multiplexed address data inputs using 74F157 quad input multiplexers. Each 74F157 devices takes address data inputs originating from microprocessor external master. 74F157s produce four outputs multiplexed address/data information which then used DS1609 port. inputs each 74F157 tied ground. inputs 74F157's become control logic, direct switching back forth between passing address lines data lines. Read write enabling signals must provided microprocessor external master.
DS1609's unique asynchronous dual port access allows system design provide bytewide registers which shared independent microprocessors. Multiple DS1609's tied together system provide microprocessors having access byte memories. Because multiplexed address/data bus, count cost kept minimum while providing unique asynchronous access. systems which have multiplexed address/data bus, minimal logic convert separate address data lines into multiplexed address/data usable DS1609. Intel, 8086, 8088, trademarks Intel Corporation. Motorola, HC11, 68030, trademarks Motorola, Inc.
SUMMARY
DS1609 Dual Port tailored with multiplexed address/data microprocessors.
030698

DUAL PORT PORT PORT 030698 Memory devices systems diversifyi

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