Megabit (524,288 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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Megabit (524,288 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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Am29F040
Megabit (524,288 8-Bit) CMOS Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
read write operations Minimizes system level power requirements Compatible with JEDEC-standards Pinout software compatible with singlepower-supply Flash Superior inadvertent write protection Package options 32-pin PLCC 32-pin TSOP 32-pin PDIP Minimum 100,000 write/erase cycles guaranteed High performance maximum access time Sector erase architecture Uniform sectors Kbytes each combination sectors erased. Also supports full chip erase. Sector protection Hardware method that disables combination sectors from write erase operations Embedded Erase Algorithms Automatically preprograms erases chip combination sectors Embedded Program Algorithms Automatically programs verifies data specified address Data Polling Toggle feature detection program erase cycle completion Erase suspend/resume Supports reading data from sector being erased power consumption typical active read current typical program/erase current Enhanced power management standby mode typical standby current Standard access time from standby mode
GENERAL DESCRIPTION
Am29F040 Mbit, Volt-only Flash memory organized Kbytes bits each. Am29F040 offered 32-pin package. This device designed programmed in-system with standard system supply. 12.0 required write erase operations. device also reprogrammed standard EPROM programmers. standard Am29F040 offers access times between allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable (CE), write enable (WE) output enable (OE) controls. Am29F040 entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Volt Flash EPROM devices. Am29F040 programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified less than second. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin.
Publication# 17113 Rev: Amendment/0 Issue Date: November 1996
individual sector typically erased verified seconds already completely preprogrammed). This device also features sector erase architecture. sector mode allows byte blocks memory erased reprogrammed without affecting other blocks. Am29F040 erased when shipped from factory. device features single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling Toggle feature DQ6. Once program erase cycle been completed, device internally resets read mode. AMD's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability cost effectiveness. Am29F040 memory electrically erases entire chip bits within sector simultaneously FowlerNordheim tunneling. bytes programmed byte time using EPROM programming mechanism electron injection.
Flexible Sector-Erase Architecture
Eight Kbyte sectors Individual-sector, multiple-sector, bulk-erase capability Individual multiple-sector protection user definable
7FFFFh 6FFFFh 5FFFFh Kbytes Sector 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh 00000h
17113E-1
Am29F040
PRODUCT SELECTOR GUIDE
Family Part Ordering Part Access Time (ns) Access (ns) Access (ns) -120 -150 Am29F040
BLOCK DIAGRAM
DQ0-DQ7
Erase Voltage Generator
Input/Output Buffers
State Control Command Register Voltage Generator Chip Enable Output Enable Logic Data Latch
Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A18
17113E-2
Am29F040
CONNECTION DIAGRAMS
PDIP
17113E-3 17113E-4
PLCC
17113E-5
TSOP 29F040 Standard Pinout 29F040 Reverse Pinout
Am29F040
CONFIGURATION
A0-A18 Address Inputs DQ0-DQ7 Data Input/Output Chip Enable Output Enable Write Enable Device Ground Device Power Supply (5.0 ±10% ±5%)
LOGIC SYMBOL
A0-A18 DQ0-DQ7
17113E-6
Am29F040
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination AM29F040 OPTIONAL PROCESSING Blank Standard Processing Burn-In TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 32-Pin Plastic 032) 32-Pin Rectangular Plastic Leaded Chip Carrier 032) 32-Pin Thin Small Outline Package (TSOP) Standard Pinout 032) 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F040 Megabit (524,288 8-Bit) CMOS Volt-only, Sector Erase Flash Memory
Valid Combinations AM29F040-55 AM29F040-70 AM29F040-90 AM29F040-120 AM29F040-150 PCB, PIB, PEB, JCB, JIB, JEB, ECB, EIB, EEB, FCB, FIB,
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am29F040
Table
Operation Autoselect Manufacturer Code (Note Autoselect Device Code (Note Read (Note Standby Output Disable Write Verify Sector Protect (Note Autoselect Device Unprotect Code
Am29F040 User Operations
Code Code HIGH HIGH (Note Code Code
Legend: Logic Logic Don't Care. Characteristics voltage levels. Notes: Manufacturer device codes also accessed command register write sequence. Refer Tables Refer Table valid (Program Data) during write operation. Refer section Sector Protection. VIL, initiates write operations.
Read Mode
Am29F040 control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins (assuming addresses have been stable least tACC-tOE time).
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from device outputs toggling address from VIH. addresses don't cares except manufacturer device codes also read command register, instances when Am29F040 erased programmed system without access high voltage pin. command sequence illustrated Table (refer Autoselect Command section). Byte VIL) represents manufacturer's code (AMD 01H) byte VIH) device identifier code (Am29F040 A4H). identifiers manufacturer device exhibit parity with (DQ7) defined parity bit. Table
Standby Mode
Am29F040 standby modes, CMOS standby mode input held when current consumed less than standby mode held VIH) when current required reduced approximately standby mode outputs high impedance state, independent input. device deselected during erasure programming, device will draw active current until operation completed.
Am29F040
Table Am29F040 Autoselect Codes
Type Manufacturer Am29F040 Device Sector Protection Code (HEX) 01H*
Sector Addresses
*Outputs protected sector addresses
Table
Sector Addresses
Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
Sector Protection
Am29F040 features hardware sector protection. This feature will disable both program erase operations number sectors through sector protect feature enabled using programming equipment user's site. device shipped with sectors unprotected. Alternatively, program protect sectors factory prior shipping device (AMD's ExpressFlashService). also possible determine sector protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses (A16, A17, A18) used select desired sector. device produces logical protected sector logical unprotected sector. Table Autoselect codes.
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/ Programming Waveforms specific timing parameters.
Sector Unprotect
Am29F040 also features sector unprotect mode that protected sector unprotected incorporate changes code. sector unprotect enabled using programming equipment user's site.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0) Erase Resume (30) commands valid only while Sector Erase operation progress. Either reset commands will reset device (when applicable).
Am29F040
Table
Write Cycles Req'd First Write Cycle Addr XXXXH 5555H 5555H 5555H 5555H 5555H Data
Am29F040 Command Definitions
Second Write Cycle Addr Data Third Write Cycle Addr Data Fourth Read/Write Cycle Addr Data Fifth Write Cycle Addr Data Sixth Write Cycle Addr Data
Command Sequence Read/Reset Read/Reset Read/Reset Autoselect Byte Program Chip Erase Sector Erase
2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
5555H 5555H 5555H 5555H 5555H
2AAAH 2AAAH 5555H
5555H 5555H
Sector Erase Suspend Sector Erase Resume
Erase suspended during sector erase with Addr (don't care), Data (B0H) Erase resumed after suspend with Addr (don't care), Data (30H)
Notes: Address bits A15, A16, A17, Don't Care address commands except Program Address (PA), Sector Address (SA), Read Address (RA), autoselect sector protect verify. operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge pulse. Address sector erased. combination A18, A17, will uniquely select sector (see Table Data read from location during read operation. Data programmed location Data latched rising edge Read from non-erasing sectors allowed Erase Suspend mode.
Read/Reset Command
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up read/ reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
device contains command autoselect operation supplement traditional PROM programming methodology. operation initiated writing autoselect command sequence into command register. Following command write, read cycle from address XX00H retrieves manufacture code 01H. read cycle from address XX01H returns device code (see Table manufacturer device codes will exhibit parity with (DQ7) defined parity bit. Scanning sector addresses (A16, A17, A18) while (A6, will produce logical device output protected sector. terminate operation, necessary write read/reset command sequence into register.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice.
Byte Programming
device programmed byte-by-byte basis. Programming four cycle operation. There "unlock" write cycles. These followed program setup command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first.
Am29F040
rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. automatic programming operation completed when data equivalent data written this (see Write Operation Status section) which time device returns read mode addresses longer latched. Therefore, device requires that valid address device supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting cause device exceed programming time limits (DQ5 result apparent success, according data polling algorithm, read from reset/read mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded Programming Algorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "setup" command. more "unlock" write cycles then followed sector erase command. sector address (any address location within desired sector) latched falling edge while command (data) latched rising edge time-out from rising edge last sector erase command will initiate sector erase command(s). Multiple sectors erased concurrently writing cycle operations described above. This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. (Monitor determine sector erase window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this period resets device read mode, ignoring previous command string. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase. When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data (see Write Operation Status section) which time device returns read mode. During execution Sector Erase command, only Erase Suspend Erase Resume commands allowed. other commands will ignored. Data polling must performed address within sectors being erased. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "setup" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device automatically will program verify entire memory zero data pattern prior electrical erase. chip erase performed sequentially sector time. system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (see Write Operation Status section) which time device returns read mode. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Am29F040
Erase Suspend
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writing Erase Suspend command during Sector Erase time-out results immediate termination time-out period suspension erase operation. other command written during Erase Suspend mode will ignored except Erase Resume command. Writing Erase Resume command resumes erase operation. addresses "don't-cares" when writing Erase Suspend Erase Resume command.
When Erase Suspend command written during Sector Erase operation, device will take maximum suspend erase operation. When device entered erase-suspended mode, will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, device defaults erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. resume operation Sector Erase, Resume command (30H) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
Write Operation Status
Table
Status Byte Programming Embedded Algorithm Embedded Erase Algorithm Progress Erase Erase Suspended Sector Suspended Non-Erase Suspended Sector Mode Byte-Programming Embedded Algorithm Embedded Erase Algorithm
Write Operation Status
Data Toggle Toggle Toggle Data Toggle Toggle Data Data
Exceeded Time Limits
Data Polling Am29F040 device features Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read device produces compliment data last written DQ7. Upon completion Embedded Program Algorithm, reading device produces true data last written DQ7. During Embedded Erase Algorithm, reading device produces output. Upon completion Embedded Erase Algorithm, reading device produces output. flowchart Data Polling (DQ7) shown Figure chip erase, Data Polling valid after rising edge sixth pulse write pulse sequence. sector erase, Data Polling valid after last rising edge sector erase pulse. Data
Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. Once Embedded Algorithm operation close being completed, Am29F040 data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs DQ0-DQ6 still invalid. valid data DQ0-DQ7 will read successive read attempts. Data Polling feature active during Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, sector erase time-out (see Table
Am29F040
Figure Data Polling timing specifications diagrams.
Toggle Am29F040 also features "Toggle Bit" method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase, Toggle valid after rising edge sixth pulse write pulse sequence. Sector erase, Toggle valid after last rising edge sector erase pulse. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. Figure Toggle timing specifications diagrams.
this failure condition occurs during chip erase operation, specifies that entire chip combination sectors bad. this failure condition occurs during byte programming operation, specifies that entire sector containing that byte this sector reused, (other sectors still functional reused). failure condition also appear user tries program location previously programmed "0". this case device locks never completes Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate "1". Please note that this device failure condition since device incorrectly used.
Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle Bit. ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, command have been accepted. Refer Table Write Operation Status.
Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Table this failure condition occurs during sector erase operation, specifies that particular sector reused, however, other sectors still functional used program erase operation. device must reset other sectors. Write Reset command sequence device, then execute program erase command sequence. This allows system continue other active sectors device.
Data Protection
Am29F040 designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transitions system noise.
Am29F040
Write Inhibit
avoid initiation write cycle during power-up power-down, Am29F040 locks write cycles VLKO (see Characteristics section voltages). When VLKO, command register disabled, internal program/erase circuits disabled, device resets read mode. Am29F040 ignores writes until VLKO. user must ensure that control pins correct logic state when VLKO prevent unintentional writes.
Logical Inhibit
Writing inhibited holding VIL, VIH. initiate write cycle must logical zero while logical one.
Power-Up Write Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Sector Protect
Sectors Am29F040 hardware protected using programming equipment users factory. protection circuitry will disable both program erase functions protected sector(s). Requests program erase protected sector will ignored device.
Am29F040
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (see below)
Data Poll Device
Increment Address
Last Address
Programming Completed
Program Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
17113E-7
Figure
Embedded Programming Algorithm
Am29F040
EMBEDDED ALGORITHMS
Start Write Erase Command Sequence (see below) Data Polling Toggle Successfully Completed
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H Additional sector erase commands optional Sector Address/30H
17113E-8
Figure Embedded Erase Algorithm
Am29F040
Start
Read Byte (DQ0-DQ7) Addr
Byte address programming sector addresses within sector being erased during sector erase operation XXXXH during chip erase
Data Read Byte (DQ0-DQ7) Addr
Data Fail
Pass
17113E-9
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
Am29F040
Start
Read Byte (DQ0-DQ7) Addr
Byte address programming sector addresses within sector being erased during sector erase operation XXXXH during chip erase
Data Read Byte (DQ0-DQ7) Addr
Data Fail
Pass
17113E-10
Note: rechecked even because stop toggling same time changing "1".
Figure
Toggle Algorithm
+0.8 -0.5 -2.0
17113E-11
Figure
Maximum Negative Overshoot Waveform
17113E-12
Figure
Maximum Positive Overshoot Waveform
Am29F040
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Ceramic Packages -65°C +150°C Plastic Packages -65°C +125°C Ambient Temperature with Power Applied. -55°C +125°C Voltage with Respect Ground pins except (Note -2.0 +7.0 (Note -2.0 +7.0 (Note -2.0 +13.0 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs undershoot -2.0 periods Maximum voltage input pins During voltage transitions, input pins overshoot periods 20ns. Minimum input voltage -0.5 During voltage transitions, undershoot -2.0 periods Maximum input voltage +12.5 which overshoot 14.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA). +70°C Industrial Devices Ambient Temperature (TA). .-40°C +85°C Extended Devices Ambient Temperature (TA). .-55°C +125°C Supply Voltages Am29F040-55. +4.75 +5.25 Am29F040 -70, -90, -120, -150 +4.50 +5.50
Operating ranges define those limits between which functionality device guaranteed.
Am29F040
CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Active Read Current (Note Active Program/Erase Current (Notes Standby Current Input Level Input High Level Voltage Autoselect Sector Protect 5.25 Output Voltage Output High Level Lock-Out Voltage -2.5 Test Description VCC, Max, 12.5 VOUT VCC, VIL, VIL, Max, -0.5 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress. 100% tested.
Am29F040
CHARACTERISTICS (continued) CMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 VOH2 VLKO Lock-out Voltage Parameter Description Input Load Current Input Load Current Output Leakage Current Active Read Current (Note Active Program/Erase Current (Notes Standby Current (Note Input Level Input High Level Voltage Autoselect Sector Protect Output Voltage Output High Voltage 5.25 12.0 -2.5 -100 0.85 -0.4 Test Description VCC, Max, 12.5 VOUT VCC, VIL, VIL, Max, -0.5 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress. 100% tested. ICC3 extended temperatures +85°C).
Am29F040
CHARACTERISTICS Read Only Operations Characteristics
Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Standard tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Notes Output Enable Output High (Notes Output Hold Time from Addresses, Whichever Occurs First Test Setup Speed Options (Note -120 -150 Unit
tAXQX
Notes: Test Conditions (for -55):
Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level, input output: Output Load: gate Input rise fall times: Input pulse levels: 0.45 Timing measurement reference level, input output:
(for others):
Output driver disable time. 100% tested.
IN3064 Equivalent
Device Under Test
Diodes IN3064 Equivalent
17113E-13
Notes: -55: including capacitance others: including capacitance
Figure
Test Conditions
Am29F040
CHARACTERISTICS Write/Erase/Program Operations
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Standard tOES Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read (Note Enable Toggle Data Polling Hold (Note Time Read Recover Time Before Write Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Sector Erase Operation (Note tWHWH3 tWHWH3 tVCS Chip Erase Operation (Note Setup Time (Note tWHWH2 tWHWH2 Speed Options -120 -150 Unit
tOEH
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1
tGHWL tWPH tWHWH1
Notes: This does include preprogramming time. 100% tested.
Am29F040
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING WAVEFORMS
Addresses tACC Addresses Stable
(tDF)
(tCE) (tOH) High High
Outputs
Output Valid
17113E-14
Figure
Waveforms Read Operations
Am29F040
SWITCHING WAVEFORMS
Data Polling Addresses 5555H tGHWL tWPH Data
17113E-15
tWHWH1
DOUT
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure Program Operation Timings
Addresses 5555H 2AAAH tGHWL tWPH Data tVCS 10H/30H 5555H 5555H 2AAAH
17113E-16
Note: sector address Sector Erase. Addresses don't care Chip Erase.
Figure
Waveforms Chip/Sector Erase Operations
Am29F040
SWITCHING WAVEFORMS
tOEH
Valid Data High
tWHWH Invalid
Valid Data
17113E-17
*DQ7 Valid Data (The device completed Embedded operation.)
Figure
Waveforms Data Polling During Embedded Algorithm Operations
tOEH tOES Data (DQ0-DQ7) Toggle
17113E-18
Toggle
Stop Toggling
DQ0-DQ7 Valid
*DQ6 stops toggling (The device completed Embedded operation.)
Figure
Waveforms Toggle During Embedded Algorithm Operations
Am29F040
CHARACTERISTICS Write/Erase/Program Operations
Alternate Controlled Writes
Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Standard tOES Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read (Note Enable Toggle Data Polling Hold (Note Time Read Recover Time Before Write Setup Time Hold Time Pulse Width Pulse Width High Byte Programming Operation Sector Erase Operation (Note tWHWH3 tWHWH3 tVCS Chip Erase Operation (Note Setup Time (Note tWHWH2 tWHWH2 Speed Options -120 -150 Unit
tOEH
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1
tGHEL tCPH tWHWH1
Notes: This does include preprogramming time. 100% tested.
Am29F040
SWITCHING WAVEFORMS
Data Polling Addresses 5555H tGHEL tCPH Data
17113E-19
tWHWH1
DOUT
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Alternate Controlled Program Operation Timings
Am29F040
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note (Note (Note (Note (Note 10.8 (Notes Unit Comments Excludes programming prior erasure Excludes programming prior erasure Excludes system-level overhead (Note Excludes system-level overhead (Note
Notes: 25°C, VCC, 100,000 cycles. Under worst case condition 90°C, VCC, 100,000 cycles. System-level overhead defined time required execute four cycle command necessary program each byte. preprogramming step Embedded Erase algorithm, bytes programmed before erasure. Embedded Algorithms allow byte program time. only after byte takes theoretical maximum time program. minimal number bytes require significantly more programming pulses than typical byte. majority bytes will program within pulses µs). This demonstrated Typical Maximum Programming Times listed above.
LATCHUP CHARACTERISTICS
Input Voltage with respect pins Current -1.0 -100 +100
Includes pins except VCC. Test conditions: time.
CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
Am29F040
PLCC CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
PDIP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
Am29F040
PHYSICAL DIMENSIONS 32-Pin Plastic (measured inches)
1.640 1.680 .530 .580 .045 .065 .140 .225 .005 .630 .700 .008 .015
.600 .625
I.D.
SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060
16-038-SB_AG DG75 2-28-95
32-Pin Plastic Leaded Chip Carrier (measured inches)
.485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 VIEW .050 REF. .490 .530 .042 .056
.447 .453
.585 .595 .547 .553
I.D.
SIDE VIEW
16-038FPO-5 DA79 6-28-94
Am29F040
PHYSICAL DIMENSIONS (continued) 32-Pin Standard Thin Small Outline Package (measured millimeters)
0.95 1.05 I.D.
0.17 0.27 7.90 8.10
0.50
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 0.50 0.70
16-038-TSOP-2 DA95 8-14-96
Am29F040
PHYSICAL DIMENSIONS (continued) TSR032 32-Pin Reversed Thin Small Outline Package (measured millimeters)
0.95 1.05 I.D.
0.17 0.27 7.90 8.10
0.50
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 0.50 0.70
16-038-TSOP-2 TSR032 DA95 8-15-96
Am29F040
DATA SHEET REVISION SUMMARY AM29F040
Distinctive Characteristics Changed power consumption specifications typical values. Added "enhanced power management" bullet. General Description Fifth paragraph, changed sector erase time sec. Product Selector Guide Removed ±5%) speed option. Ordering Information Added speed option example part number. Removed speed option from valid combinations. Added industrial extended temperature ranges valid combinations. Added extended temperature valid combinations. Table 1-User Operations Changed write entry "PD" read entry "RD"; matches Table Corrected reference tables Note Standby Mode Changed maximum CMOS standby mode current Autoselect Deleted fourth paragraph. Table 2-Autoselect Codes Changed table title. Table 3-Sector Addresses Changed table title. Sector Protection Reworded second paragraph, second sentence. Sector Unprotection Deleted after second sentence. Table 4-Command Definitions Added first cycle first Read/Reset command. Changed fourth cycle Byte Program from "data" "PD". Deleted Note Rewrote Notes
Sector Erase Changed time-out Deleted note. second paragraph, deleted third sentence from end. fourth paragraph, changed third sentence from end. User Note Chip Erase Sector Erase Commands Deleted section. Erase Suspend Deleted last sentence fourth paragraph. Deleted fifth paragraph. Table 5-Write Operation Status Added overbars DQ7. DQ7-Data Polling Fourth paragraph, added "Erase Suspend." DQ5-Exceeded Timing Limits Clarified first sentence fifth paragraph. Absolute Maximum Ratings Corrected second sentence Operating Ranges-VCC Supply Voltages Added speed options. Deleted speed option. Characteristics
TTL/NMOS Compatible: Changed ICC1, ICC2, specifications. CMOS Compatible: Changed ICC1, ICC2, ICC3 specifications, added typical values. Added Note
Characteristics
Read Only Operations Characteristics: Removed speed option. Changed tGLQV column Combined Notes
Figure 7-Test Conditions Changed first note -55. Characteristics
Write/Erase/Program Operations (also same table Alternate Controlled Writes): Removed speed option. Changed specifications tWHWH1, tWHWH2, tWHWH3.
Erase Programming Performance Changed maximum specifications. Clarified note Deleted Note
Trademarks Copyright 1996 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am29F040

Megabit (524,288 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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