P.O. 9106 NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700 Interfac

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AN-399 APPLICATION NOTE
P.O. 9106 NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700
Interfacing AD1890/AD1891 AES/EBU Receivers Digital Filters
Hank Zumbahlen, Senior Field Applications Engineer
ABSTRACT AES/EBU AES3-199X IEC-958 have become standard interfacing digital audio components digital domain. AD1890/AD1891 Asynchronous Sample Rate Converter (ASRC) device that provides solution sample rate interfacing compatibility issues. practice using oversampling digital signal before goes digital-to-analog converter become standard well. This paper examines issues with interfacing these components. AES/EBU INPUT Even though resolution commercial digital audio sources, Compact Disc (CD) Digital Audio Tape (DAT), bits, AES/EBU interface space bits data, total frame size bits. format subframe shown Figure This allows higher resolution professional applications. Therefore, since data will fill entire width word, data must padded. This padding either before after data word. placed before data, (Least Significant Bit) 32nd clock position. This referred right-justified data. padding placed after data, (Most Significant Bit) first clock position. This referred left-justified data.
problem arises when mate component that right justifies data with that expects leftjustified data. This case when trying mate AD1890/AD1891 with Yamaha YM3623B receiver chip. Crystal CS8412 allows user select which data format used. These chips most popular solutions this point time. standard digital audio signal consists data, which alternated between left right channels, signal indicate whether left right channel (L/R), clock word clock which indicates valid data. moving clock that change justification data. Assume that have bits right-justified data, which case with Yamaha part. That would mean that would have leading zeros. delaying clock, outputted receiver chip, word clock, also output from receiver chip, delay clock quarter cycle. signal will change state beginning valid output data, which effect changes data left justification. This delaying clock done simply with type flip-flop (see Figure timing signals given Figure
PREAMBLE
PREAMBLE
DATA
AUDIO DATA
DATA
DATA
DATA FRAME
DATA FRAME
PREAMBLE INDENTIFIES RIGHT LEFT CHANNEL START BLOCK DATA AUDIO DATA DATA WORD GREATER THAN BITS OPEN OTHER APPLICATIONS DATA WORD LESS THAN BITS VALIDITY VALID DATA USER DATA UNDEFINED CHANNEL STATUS PARITY GENERATES EVEN PARITY
FRAME STATUS BLOCK
FRAME START STATUS BLOCK
PREAMBLE INDICATES DATA INDICATES DATA INDICATES DATA START STATUS BLOCK
Figure Audio Subframe Format
Figure Audio Block Format
YM3623B
DOUT XOUT KMODE/ HLDR HLDL
AD1891
DATA_I BCLK_I WCLK_I BKPOL_I TRGLR_O TRGLR_I DATA_O BCLK_O WCLK_O BKPOL_O
DATA_I BCLK_I L/R_I WCLK_I BKPOL_I TRGLR_I MSBDLY_I
DATA_O BCLK_O L/R_O WCLK_O BKPOL_O TRGLR_O MSBDLY_O MUTE_O
FSCO
NPC5813
BCLK /RST /OW18 /CKDV /CKSL /SYN /COB WCKO BCKO /OW20
SEETLSLW
MSBDLY_O MSBDLY_I MUTE_O MUTE_I SEETLSLW GPDLYS
AD1890
GPDLYS FLAG_I
MUTE_I RESET
MCLK
74HC74
SSYNC
SYNC/
SCLK
CLOCK
FLAG_I
RESET
MCLK
ADDITIONAL CIRCUITRY SHOWN CLARITY
WORD CLOCK
Figure Justification Change
YM3623B
DATA CLKOUT CLOCKS CLOCKS
74HC393
74HC74
74HC393
ADDITIONAL CIRCUITRY SHOWN CLARITY
12.288
WORD CLOCK
Figure Digital Filter Interface
CLOCKS
AD1890/91
AD1890/91
CLOCKS CLOCKS
CLOCKS
Figure Receiver ASRC Timing
INTERPOLATION FILTER Just inverse process required interfacing SM5813 similar digital filters. These filters used raise apparent sample rate digital audio string factor typically, increasing apparent data rate images moved frequency that much simpler (lower order) filter designed. advantages simpler filter many. First most important that smaller filter easier design manufacture. They less components they less expensive. Also, order filter will have high sections which tend ring when with transient. filter expecting right hand justified data. AD1890/AD1891 outputs left-hand justified data. Therefore must same trick used before (see Figure clock delayed word clock effectively change justification data from left-justified right-justified. There slight difference though. AD1890/AD1891 will bits data. digital filter expecting only bits. Luckily data format first that first bits will latched when clock transitions, which latches contents digital filters shift register. remaining bits will affect input filter, since shift register only sixteen bits wide last bits previous channel will have shifted through register before valid bits present channel latched. Figure shows timing ASRC-filter interface.
DATA
WORD CLOCK
NPC5813
Figure ASRC-Digital Filter Timing
CONCLUSION interface between components which expect different justification data been examined. proposal modifying justification been presented. should noted that second generation ASRCs, AD1893, have internal provisions selection either left justification right justification. BIBLIOGRAPHY AUDIO ENGINEERING SOCIETY, "AES Recommended Practice Digital Audio Engineering Serial Transmission Format Linearly Represented Digital Audio Data," AES3-1985 (ANSI S4.40-1985). INTERNATIONAL ELECTROTECHNICAL COMMISSION "International Standard Digital Audio Interface," 1989. Zumbahlen, Hank, Outboard Digital-to-Analog Converter Digital Audio Sources," Analog Devices AN-394, 1995. Sanchez, Clifton Taylor, Robert, "Overview Digital Audio Interface Structures," Crystal Semiconductor AN-22.
PRINTED U.S.A.
E2037-15-6/95

P.O. 9106 NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700 Interfac

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