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Technical Notes using Analog Devices' components development tools
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Analog Devices JTAG Emulation Technical Reference
Contributed David Doyle July 2003
Introduction
Every processor developer needs emulator test debug hardware software systems. Analog Devices Inc. (ADI) offers family in-circuit emulators (ICE). According IEEE 1149.1 standard defined Joint Test Access Group (JTAG), Test Access Port (TAP) designed SHARC© DSPs, TigerSHARC® processors, ADSP-219x DSPs Blackfin® processors. Analog Devices JTAG emulators JTAG interface access internals processors. This permits load code, breakpoints, observe variables, observe memory, examine registers, processor must halted send data commands, once emulator completed operation, processor system running full speed with impact system timing.
Note: avoid unpredictable processor operations power very important follow target interface requirements ~TRST signal. This signal must pulsed power ensure boots correctly. Previous revisions this document have directed treat ~TRST signal differently. experiencing problems with target designed with earlier revision this document, encouraged update your target reflect this revision.
last thing want when testing hardware design debug target board's emulation port. Often, emulation port only vehicle through which test target board; must work flawlessly. This engineering note describes design interface between emulation header custom target board JTAG DSP. guidelines this engineering note will help eliminate JTAG emulation-port problems. This document describes correct JTAG interface requirements targets using Analog Devices processors with embedded JTAG emulation support. Analog Devices manufactures sells different JTAG emulator product types. product types supported this document include Analog Devices older Legacy products Analog Devices newer High Performance products. Legacy products include Analog Devices Mountain-ICETM, Summit-ICETM, Trek-ICETM, Apex-ICETM. Legacy products support targets with 3.3V voltage, fixed operating speed 10MHz. should connect Legacy product targets designed products unless 3.3V voltage target. Connecting Legacy product target with voltage lower than 3.3V could result damage target 3.3V pod. Targets designed products will only fixed 10MHz rate when using Legacy product.
Copyright 2003, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices' Engineer-to-Engineer Notes.
products include Analog Devices HPPCI ICE, High Performance ICE. products will automatically detect target voltages 5V/3.3V/2.5V/1.8V, without need setting switches user. Depending your target type delay your target JTAG path, products will support four different selectable speeds. They include 10MHz., 25MHz, 33MHz, 50MHz, with 10MHz being default operating speed. safely connect product targets designed Legacy products. products will support higher frequencies targets designed Legacy products. frequencies include 25MHz, 33MHz, 50MHz, default frequency 10MHz. higher frequencies supported Legacy products dependent target type delays target JTAG path. will support automatic target voltage detection targets designed Legacy products. will only support 5V/3.3V voltages with Legacy product targets. targets should designed support product family. future JTAG emulator product development Analog Devices will part product family.
Note: guarantee your target will function properly, should only product information sections this document that support your JTAG emulator product.
Legacy Target JTAG Header
emulation header JTAG target pins, shown Figure must supply this header target board order communicate with emulator. interface standard dual-row 0.025" squarepost header, 0.1" 0.1" spacing, with minimum post length 0.235". keyed prevent from accidentally inserting backwards. Clip this target board. recommends following clearance considerations length, width, height around header. Provide clearance least 0.30" 0.10" around length width header, respectively. Reserve room above header attach detach header. Figure Figure drawing connector.
pin)
BTMS
BTCK
BTRST
TRST
BTDI
Figure Legacy Emulation Header Interface
Legacy
This section document specifically describes technical information Analog Devices Mountain-ICE, Summit-ICE, Trek-ICE, Apex-ICE products. your product these products, should section that supports your product.
Note: Older target designs connect clock signal target referred CLKIN. emulator longer uses this signal. This signal cause noise problems connected JTAG header. your target already connects header target CLKIN signal, clip this 14-pin JTAG header.
Analog Devices JTAG Emulation Technical Reference (EE-68)
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Legacy JTAG Header Boundary Scan Signals
shown Figure signals odd-numbered side connector used targets, which have board-level boundary-scan logic. These signals include board-level boundary-scan controller JTAG signals (BTMS, BTCK, BTDI, ~BTRST). Each these signals described Table
Legacy Targets with Boundary Scan Logic
Note: your target performs boundary scan, your target does control ~BTRST signal during boundary scan, will need guarantee ~BTRST signal only pulsed during power reset, driven high other times when performing boundary scan. Keeping ~BTRST signal continuously during boundary scan will keep reset, allowing target successfully execute boundary scan. Legacy Targets without Boundary Scan Logic
Targets with on-board boundary-scan logic should connect board-level boundary-scan signal pins on-board JTAG boundary-scan logic target shown Figure These pins connect inside emulator pod, simply provide method inserting removing target from boundary-scan controller logic board using jumpers. Make these connections installing removing jumpers between boundary-scan JTAG signals (BTMS, BTCK, BTDI, ~BTRST) emulation JTAG signals (TMS, TCK, TDI, ~TRST). Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target. ~TRST must pulsed power when using onboard boundary scan logic, should kept when using onboard boundary scan controller logic. Jumpers substituted with zero resistors production boards. Figure shows ~TRST should controlled when target uses boundary scan controller, while Figure shows ~TRST should controlled when target does it's boundary scan controller.
Targets that board-level boundary scan include boundaryscan chain target) should boundary-scan JTAG signals ground shown Figure Jumpers should connected between boundary-scan JTAG signals (BTMS, BTCK, BTDI, ~BTRST) emulation JTAG signals {TMS, TCK, TDI, ~TRST}. jumper substituted with zero resistor production boards. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Legacy JTAG Header Emulation Signals
shown Figure emulator uses signals even-numbered side header. These signals include standard JTAG signals (TMS, TCK, TDI, TDO, ~TRST). Also included ~EMU signal, special event signal defined IEEE JTAG standard, which used emulators. These signals described Table
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
JTAG Supply
pin)
BTMS
Connect Signals Target Board-Level Boundary Scan Controller Note Below
BTCK
Target JTAG Signals
BTRST
TRST
BTDI
Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here. Note: Zero resistors substituted jumpers production boards.
JTAG Supply
PowerUpReset
SN7408
BTRST
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
BoundaryScanReset
Figure Legacy Emulation Header with Boundary Scan
JTAG Supply
pin)
Connect Signals Target Digital Gound.
BTMS
BTCK
Target JTAG Signals
BTRST
TRST
BTDI
Note: Zero resistors substituted jumpers production boards. Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure Legacy Emulation Header without Boundary Scan
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
Signal
~EMU BTMS BTCK ~BTRST ~TRST BTDI
Description
Emulator/Target Digital Ground Signals Emulator, Operation Completed location removed from Target JTAG Header Previously CLKIN. Used Local Boundary Scan Test Mode Select Emulator Test Mode Select Local Boundary Scan Test Clock Emulator Test Clock Local Boundary Scan Test Reset {active low} Emulator Test Reset {active low} Local Boundary Scan Test Data Emulator Test Data Emulator/Target Digital Ground Emulator Test Data
Emulator
Passive Input Connect Input Connect Output Connect Output Connect Output Connect Output Passive Input
Target
Passive Output {Open Drain} Connect Passive Output Input Output Input Output Input Output Input Passive Output
Table Legacy JTAG Header Signal Description
Legacy Connections
Single-DSP Target
Note: route between header exceeds eight inches and/or target multiple JTAG devices emulator scan chain, buffer shown Figure Figure This length restriction also applies targets with single other JTAG devices emulation scan path.
Targets with single whose routes between header shorter than eight inches require buffer shown Figure Figure Figure Figure show connections between emulation header target targets without board-level boundary-scan with board-level boundary scan respectively.
Also shown Figure Figure optional (recommended, required) series terminations (RT) ~EMU signals going emulator. value generally equal ZLine(PCB) minus ZDriver(DSP), where impedance represented ohms. Initially these resistors zero ohms. Change them value range signal integrity problems observed with emulator. Tuning value required, depending condition signals. Place termination resistors close possible. traces between emulation header single-DSP designs without JTAG signal buffers must shorter than inches. Route traces between emulation header group, using equal lengths possible). Provide good cross-talk isolation from other signal nets especially clocks.
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
JTAG Supply
pin)
BTMS
Connect Signals Target Digital Ground
BTCK
BTRST
TRST
TRST
BTDI
Note: Zero resistors substituted jumpers production boards. Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure Legacy Single Target without Boundary Scan
Legacy Single Target without Boundary Scan
Legacy Single-DSP Targets with Boundary Scan
Figure shows connections between emulation header target consisting single with board-level boundary scan header routes that exceed eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Figure shows connections between emulation header target system consisting single with board-level boundary scan header routes exceeding eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Analog Devices JTAG Emulation Technical Reference (EE-68)
TARGET
Page
JTAG Supply
pin)
BTMS
Connect Signals Target Board-Level Boundary Scan Controller Note Below
BTCK
BTRST
TRST
TRST
BTDI
Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here. Note: Zero resistors substituted jumpers production boards.
JTAG Supply
PowerUpReset
SN7408
BTRST
BoundaryScanReset
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure Legacy Single Target with Boundary Scan
Legacy Multiple Target Connections
Legacy JTAG Header Connection Multiple DSPs
scan path more than other JTAG devices) chain, JTAG header farther than eight inches from DSP, buffered connection scheme shown Figure Figure minimize signal skew, ensure that buffers TMS, TDI, ~TRST, TDO, ~EMU signals come from single package. signals, driver with high out. drivers should come from single dedicated package that used other TMS, TDI,
~TRST, TDO, ~EMU signals. Limit number loads (DSPs) TDI, ~TRST, TDO, ~EMU buffered signals eight (8). Additional loads (DSPs) should another buffer support eight more devices. Using more than sixteen (16) physical devices scan chain recommended, highly discouraged. physical device, such multichip module may, however, contain many JTAG devices). This recommended limit transmission line effects that appear long signal traces (and excessive capacitive loading), which lead unreliable emulator performance.
Analog Devices JTAG Emulation Technical Reference (EE-68)
TARGET
Page
best approach large numbers (>16) physical devices break chain into smaller independent chains, each with JTAG header buffers. this possible, jumpers reduce number devices chain debug purposes. special attention routing minimize transmission line effects. jumper substituted with zero resistor production boards. Referring Figure Figure because ~EMU signal open drain, requires 4.7K pull-up resistor (RPEMU) target JTAG voltage input buffer. Targets without buffers require pull-up resistor ~EMU (RPEMU). RPEMU already provided emulator pod's ~EMU signal. When using more than ~EMU buffer, provide 4.7K pull-up resistor (RPEMU) each buffer input. Provide logical function these buffer outputs before sending signal JTAG header. Include extra delay logic calculations perform ~EMU signal your target. low-voltage 3.3V targets, buffer TMS, TDI, ~TRST, TDO, ~EMU signals with type 74AC11244 buffer equivalent). This buffer support both 3.3V target JTAG voltages. buffer small propagation delay (typically less than 6ns) ample drive current (+/- 24mA). targets, buffer signal with clock driver that skew, high out, minimal input-to-output delay. IDT49FCT3805E equivalent) dual 1-to-5 clock driver provides with very (<700ps) skew, (<6ns) propagation delay, ample drive current (IOH: -24mA IOL: mA). low-voltage 3.3V targets, buffer signal with clock driver that skew, high out, minimum input-to-output delay. IDT49FCT805 equivalent) dual 1-to-5 clock driver provides with very (<200ps) skew, (<2.5ns) propagation delay, ample drive current (+/- 12mA).
Note: type clock drivers signal. signal discontinuous logic lock time will result missed critical JTAG clock cycles causing scan errors.
Also shown Figure Figure optional (recommended, required) series terminations (RT) ~EMU signals going emulator. value generally equal ZLine(PCB) minus ZDriver(DSP), where impedance represented ohms Initially these resistors zero ohms. Change them value range signal integrity problems observed with emulator. have tune value, depending condition signals. Place termination resistors close possible. Route traces between emulation header group with equal lengths, possible. Provide good cross-talk isolation from other signal nets.
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
JTAG Supply
TRST TRST
JTAG Supply
Buffer Type: 74AC11244 (5V/3.3V) Equivalent
RPEMU
4.7K
pin)
BTMS
Clock DriverType: IDT49FCT805 (5V) IDT49FCT3805E (3.3V) Equivalent
Connect Signals Target Digital Ground
BTCK
BTRST
TRST
BTDI
Note: Zero resistors substituted jumpers production boards.
Maximum Devices Recommended Buffer Output. Additional loads should driven another buffer output groups loads buffer output maximum. Maximum number loads JTAG chain should limited devices (two buffer loads).
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure Legacy Multi-DSP Target without Boundary Scan
Connect Signals Target Board-Level Boundary Scan Controller Note Below
JTAG Supply
JTAG Supply
Buffer Type: 74AC11244 (5V/3.3V) Equivalent
TRST
pin)
BTMS
Clock DriverType: IDT49FCT805 (5V) IDT49FCT3805E (3.3V) Equivalent
BTCK
BTRST
TRST
BTDI
JTAG Supply Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here.
PowerUpReset
SN7408
BTRST
BoundaryScanReset
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target. Maximum Devices Recommended Buffer Output. Additional loads should driven another buffer output groups loads buffer output maximum. Maximum number loads JTAG chain should limited devices (two buffer loads). Note: Zero resistors substituted jumpers production boards.
Figure Legacy Multi-DSP Target with Boundary Scan
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
RPEMU
TRST
4.7K
Legacy Multiple-DSP Boundary Scan Target without
Figure shows connections between emulation header target which does board-level boundary-scan multiple DSPs routes between header exceed eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Legacy Multiple-DSP Target with Boundary Scan
Note: emulator interface relies state line clock signal. Unreliable emulator operation result when these signals have glitches (due ground bounce, cross-talk, etc.). experience emulator problems, check these signals with high-speed digital oscilloscope.
These lines must clean. buffering JTAG header, provide signal terminations appropriate your target board using series terminations (RT) discussed previously.
Legacy Power Sequence
avoid possible damage electronics target electronics, perform following poweron sequence your target emulator. Connect your emulator host with power applied emulator before performing these steps.
Note: This sequence only operation with ICE, does pertain production targets which choose zero resistors instead jumpers. target assumed have jumpers between
Figure shows connections between emulation header target which uses board-level boundary scan multiple DSPs routes between header that exceed eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Legacy Layout Requirements
Treat emulator signals (TCK, TMS, TDI, TDO, ~EMU, ~TRST) critical route signals. special attention when routing these signals. Specify controlled impedance requirement each route. This value, which depends your circuit board logic, typically range 50-75. Minimize cross-talk inductance these signal lines using good ground plane routing emulator signal away from high-noise signals such clock lines. Keep these routes short clean possible, keep bused signals (TMS, TCK, ~TRST, ~EMU) similar length possible.
boundary scan signals (~BTRST, BTMS, BTDI, BTCK) JTAG signals (~TRST, TMS, TDI, TCK) JTAG emulation header when connecting ICE. Turn target power. Remove jumpers mentioned above from JTAG emulation header. Connect emulator probe target. Activate VisualDSP++emulator session. This sequence ensures JTAG signals correct state free power Target. Once emulator poweredon, will drive ~TRST signal low, keeping test-logic-reset state until
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
emulation software takes control. Remove power reverse order, follows: Close VisualDSP++ emulator session. Remove emulator probe from target. Install jumpers mentioned above JTAG emulation header. Remove power from target.
Note: Analog Devices Legacy emulator electronics supply sufficient voltage your target plane while target powered interfere with power-up reset logic target. This caused current sourced through pull-up resistors pod, which connected through target input-protection diodes pins.
0.10"
0.30"
Figure JTAG Connector Keep-Out
Legacy 3.3V Logic
Legacy 3.3V JTAG
This section explains electrical mechanical specifications JTAG Pod.
Legacy JTAG Connector
Figure Legacy JTAG Connector Dimensions
Figure details dimensions JTAG header 14-pin target end. Figure displays keep-out area target board header. keep-out area forces connector properly seat with target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.025" square-post pin.
3.3V logic 3.3V-compliant drive 3.3V logic levels, meeting voltage level requirements DSPs with 3.3V voltage. 3.3V logic 5V-tolerant tolerate inputs from DSPs with voltage. portion 3.3V emulator interface shown Figure This figure describes driver circuitry emulator pod. seen, TMS, TCK, driven with series resistor. ~TRST driven with series resistor. necessary, terminate signal 3.3V emulator pod. This done installing jumper which will terminate signal with 91/120 parallel terminator. ~EMU signal pulled with resistor because opendrain characteristics this signal. needed, parallel terminating TMS, TCK, ~TRST, lines locally your target board. Because series termination resistor already installed these signals 3.3V emulator pod, addition parallel termination these lines discouraged except very noisy lines. Table includes characteristics 3.3V pod.
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
Note: optional parallel terminator placing jumper Make sure there sufficient drive terminator. this terminator have already series terminator (RT) your board discussed previously. longer used probe. Keep optional 91/120 parallel terminator this disabled leaving jumper removed.
Figure Legacy 3.3V JTAG Driver Logic
Signal ~TRST ~EMU
Cpin
Cload 50pF 50pF 50pF 50pF
2.4VDC 2.4VDC 2.4VDC 2.4VDC
0.55VDC 0.55VDC 0.55VDC 0.55VDC
-32mA -32mA -32mA -32mA
64mA 64mA 64mA 64mA
2.0VDC 2.0VDC
0.8VDC 0.8VDC
5.5VDC 5.5VDC
Table Legacy 3.3V Characteristics
Legacy 3.3V Timing
This section details important timing information relating JTAG signals JTAG header 3.3V emulator target. Figure Table define switching parameters timing requirements JTAG header interface.
this information when determining maximum routing lengths, loading, number buffers that tolerated target JTAG signal paths, while still meeting timing requirements 3.3V emulator electronics.
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
Figure Legacy 3.3V Timing Waveform
Parameter
Unit
Description TDO, ~EMU Setup Time margin before Header TDO, ~EMU Hold Time margin after Header
Timing Requirements: tsuTDO, tsuEMU/ thTDO, thEMU/ 8.45 2.45
Switching Characteristics: tcTCK twTCKH twTCKL tdTMS, tdTDI, tdTRST/ 99.990 49.995 49.995 100.010 50.005 50.005 19.20 Cycle time, Pulse duration, high Pulse duration, Delay TMS, TDI, ~TRST after Header
Table Legacy 3.3V Timing Information
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
have complex JTAG emulation path with relatively long propagation delay, want perform timing analysis determine your design will operate MHz. This analysis will determine JTAG emulation path sufficient timing margin allow operation MHz. cases, timing margin should positive number. general rule, margin should least full clock period 10ns (10% 100ns). calculate negative margin, should make changes your target reduce JTAG signal path delay. should aware when doing your analysis, delay numbers given here based worst case delay. Typically, logic will tend somewhere middle between minimum maximum delay, although this cannot guaranteed. your margin negative, very close, want typical numbers still negative. Again guarantees made when using typical numbers. should read Conclusion section this document.
Figure HPPCI Emulation Header Interface
recommends following clearance considerations length, width, height around header. Provide clearance least 0.30" 0.10" around length width header, respectively. Reserve room above header attach detach header. Figure Figure drawing connector.
Note: Older target designs connect clock signal target referred CLKIN. emulator longer uses this signal. This signal cause noise problems connected JTAG header. your target already connects header target CLKIN signal, clip this 14-pin JTAG header. HPPCI JTAG Header Boundary Scan Signals
HPPCI
This section document specifically describes technical information Analog Devices HPPCI-ICE. your product HPPCI ICE, should section that supports your product.
HPPCI Target JTAG Header
emulation header JTAG target pins, shown Figure must supply this header target board order communicate with emulator. interface standard dual-row 0.025" squarepost header, 0.1" 0.1" spacing, with minimum post length 0.235". keyed prevent from accidentally inserting backwards. Clip this target board.
shown Figure signals odd-numbered side connector used targets that have board-level boundary-scan logic. These signals include board-level boundary-scan controller JTAG signals (BTMS/VDDIO, BTCK, BTDI, ~BTRST). Each these signals described Table (BTMS/VDDIO) dual purpose pin. First, allows route board level
Page
Analog Devices JTAG Emulation Technical Reference (EE-68)
boundary scan controller BTMS signal Analog Devices when emulator connected. second, used HPPCI when connected target auto sense target board voltage. HPPCI automatically sense target voltage 5VDC. HPPCI uses voltage senses JTAG emulator interface input signal thresholds output signal drive level. must pull (BTMS/VDDIO) your target voltage with resistor.
HPPCI Targets with Boundary Scan Logic
boundary scan controller logic. Jumpers substituted with zero resistors production boards. Figure shows ~TRST should controlled when target uses boundary scan controller, while Figure shows ~TRST should controlled when target does it's boundary scan controller.
Note: your target performs boundary scan, your target does control ~BTRST signal during boundary scan, will need guarantee ~BTRST signal only pulsed during power reset, driven high other times when performing boundary scan. Keeping ~BTRST signal continuously during boundary scan will keep reset, allowing target successfully execute boundary scan.
Targets with on-board boundary-scan logic should connect board-level boundary-scan signal pins target JTAG emulation header shown Figure shown Figure board-level boundary scan controller BTMS signal should isolated from BTMS/VDDIO JTAG emulation header jumper tri-stateable buffer. must provide method isolate BTMS signal your board from BTMS/VDDIO JTAG emulation header when HPPCI connected. isolation must guaranteed before HPPCI software invoked. This will prevent board-level boundary scan controller BTMS signal from confusing automatic voltage sensing logic HPPCI BTMS/VDDIO pin. Make these connections installing removing jumpers between boundary-scan JTAG signals (BTMS/VDDIO, BTCK, BTDI, ~BTRST) emulation JTAG signals {TMS, TCK, TDI, ~TRST}. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target. ~TRST must pulsed power when using onboard boundary scan logic, should kept when using onboard
Except (BTMS/VDDIO), board level boundary scan pins connect inside emulator pod. They simply provide method inserting removing target from on-board boundary-scan controller logic using jumpers.
HPPCI Targets without Boundary Scan Logic
shown Figure designs that board-level boundary scan their targets include boundary-scan chain target) should boundary-scan JTAG signals ground with exception BTMS/VDDIO signal. BTMS /VDDIO required HPPCI automatically sense target voltage. Jumpers should connected between boundary-scan JTAG signals (BTMS/VDDIO, BTCK, BTDI, ~BTRST) emulation JTAG signals {TMS, TCK, TDI, ~TRST}. jumper substituted with zero resistor production boards. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals.
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
However, they required should they create power budget issue with your target.
HPPCI JTAG Header Emulation Signals
shown Figure emulator uses signals even-numbered side header. These signals include standard JTAG signals
Signal ~EMU BTMS/VDDIO Description
(TMS, TCK, TDI, TDO, ~TRST). Also included ~EMU signal, special event signal defined IEEE JTAG standard, which used emulators. These signals described Table
Emulator Passive Input Connect Input Input
Target Passive Output {Open Drain} Connect Passive Output
Emulator/Target Digital Ground Signals Emulator, Operation Completed {active low} location removed from Target JTAG Header Previously CLKIN. Used Dual Function: (BTMS)-Local Boundary Scan Test Mode Select Signal (VDDIO)-HPPCI Automatic Voltage Sense Emulator Test Mode Select Local Boundary Scan Test Clock Emulator Test Clock Local Boundary Scan Test Reset {active low} Emulator Test Reset {active low} Local Boundary Scan Test Data Emulator Test Data Emulator/Target Digital Ground Emulator Test Data
BTCK ~BTRST ~TRST BTDI
Output Connect Output Connect Output Connect Output Passive Input
Input Output Input Output Input Output Input Passive Output
Table HPPCI JTAG Header Signal Description
Analog Devices JTAG Emulation Technical Reference (EE-68)
Page
JTAG Supply
RPVS
JTAG Supply
4.7K
BTMSOE
pin)
BTMS
BTMS/VDDIO
Connect Signals Target Board-Level Boundary Scan Controller Note Below
BTCK
Target JTAG Signals
BTRST
TRST
BTDI
JTAG Supply
Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here. Note: Zero resistors substituted jumpers production boards.
PowerUpReset
SN7408
BTRST
Note:Connect on-board BTMS signal header BTMS/VDDIO using tri-state buffer jumper. When using buffer, buffers output must disabled when HPPCI attached JTAG emulation header Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
BoundaryScanReset
Figure HPPCI Emulation Header with Boundary Scan
JTAG Supply
JTAG Supply
RPVS
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure HPPCI Emulation Header without Boundary Scan
Analog Devices JTAG Emulation Technical Reference (EE-68)
4.7K
pin)
BTMS/VDDIO
BTCK
Target JTAG Signals
BTRST
TRST
BTDI
Note: Zero resistors substituted jumpers production boards.
Page
HPPCI Connections Single-DSP Target
generally equal ZLine(PCB) minus ZDriver(DSP), where impedance represented ohms. Initially these resistors zero ohms. Change them value range signal integrity problems observed with emulator. Tuning value required, depending condition signals. Place termination resistors close possible. Figure Figure also show pull-down resistor (RPD) installed ~TRST emulation header. This pull-down resistor keeps JTAG reset when emulator connected. emulator overdrive this resistor. traces between emulation header single-DSP designs without JTAG signal buffers must shorter than inches. Route traces between emulation header group, using equal lengths possible). Provide good cross-talk isolation from other signal nets especially clocks.
Note: route between header exceeds eight inches and/or target multiple JTAG devices emulator scan chain, buffer shown Figure Figure This length restriction also applies targets with single other JTAG devices emulation scan path.
Targets with single whose routes between header shorter than eight inches require buffer shown Figure Figure Figure Figure show connections between emulation header target targets without board-level boundary-scan with board-level boundary scan respectively. Also shown Figure Figure optional (recommended, required) series terminations (RT) ~EMU signals going emulator. value
JTAG Supply
JTAG Supply
RPVS
BTCK
BTRST
TRST
TRST
BTDI
Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target. Note: Zero resistors substituted jumpers production boards.
Figure HPPCI Single Target without Boundary Scan
Analog Devices JTAG Emulation Technical Reference (EE-68)
TARGET
4.7K
pin)
BTMS/VDDIO
Page
HPPCI Single Target without Boundary Scan HPPCI Single-DSP Targets with Boundary Scan
Figure shows connections between emulation header target consisting single with board-level boundary scan header routes that exceed eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
Figure shows connections between emulation header target system consisting single with board-level boundary scan header routes exceeding eight inches. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
JTAG Supply
JTAG Supply
RPVS
4.7K
BTMSOE
pin)
BTMS
BTMS/VDDIO
Connect Signals Target Board-Level Boundary Scan Controller Note Below
BTCK
BTRST
TRST
TRST
BTDI
JTAG Supply
Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here. Note: Zero resistors substituted jumpers production boards.
PowerUpReset
SN7408
BTRST
BoundaryScanReset
Note:Connect on-board BTMS signal header BTMS/VDDIO using tri-state buffer jumper. When using buffer, buffers output must disabled when HPPCI attached JTAG emulation header Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure HPPCI Single Target with Boundary Scan
HPPCI Multiple Target Connections
HPPCI JTAG Header Connection Multiple DSPs
connection scheme shown Figure Figure minimize signal skew, ensure that buffers TMS, TDI, ~TRST, TDO, ~EMU signals come from single package. signals, driver with high out. drivers should come from single dedicated package that used other TMS, TDI,
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scan path more than other JTAG devices) chain, buffered
Analog Devices JTAG Emulation Technical Reference (EE-68)
TARGET
~TRST, TDO, ~EMU signals. Limit number loads (DSPs) TDI, ~TRST, TDO, ~EMU buffered signals eight (8). Additional loads (DSPs) should another buffer support eight more devices. Using more than sixteen (16) physical devices scan chain recommended, highly discouraged. physical device, such multichip module may, however, contain many JTAG devices). This recommended limit transmission line effects that appear long signal traces (and excessive capacitive loading), which lead unreliable emulator performance. best approach large numbers (>16) physical devices break chain into
JTAG Supply Buffer Type: 74AC11244 (5V) 74AVC16244 (3.3V/2.5V/1.8V) Equivalent JTAG Supply
smaller independent chains, each with JTAG header buffers. this possible, jumpers reduce number devices chain debug purposes. special attention routing minimize transmission line effects. jumper substituted with zero resistor production boards. Referring Figure Figure because ~EMU signal open drain, requires 4.7K pull-up resistor (RPEMU) target JTAG voltage input buffer. Targets without buffers require pull-up resistor ~EMU (RPEMU). RPEMU already provided emulator pod's ~EMU signal.
TRST
TRST
JTAG Supply
pin)
4.7K
RPVS
BTMS/VDDIO
Clock DriverType: Equivalent IDT49FCT805 (5V) IDT49FCT3805E (3.3V) IDT5T9050 (2.5V/1.8V)
BTCK
BTRST
TRST
BTDI
Maximum Devices Recommended Buffer Output. Additional loads should driven another buffer output groups loads buffer output maximum. Maximum number loads JTAG chain should limited devices (two buffer loads).
Note: Zero resistors substituted jumpers production boards.
Note: resistors TMS, TCK, recommended, improve noise imunity these signal. However they required they create power budget issue with your target.
Figure HPPCI Multi-DSP Target without Boundary Scan
When using more than ~EMU buffer, provide 4.7K pull-up resistor (RPEMU)
each buffer input. Provide logical function these buffer outputs before sending
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Analog Devices JTAG Emulation Technical Reference (EE-68)
RPEMU
4.7K
signal JTAG header. Include extra delay logic calculations perform ~EMU signal your target.
Note: Users wish take advantage JTAG operation need minimize propagation delay their JTAG path much possible. Using skew, small propagation delay buffers suggested below will long minimizing delay JTAG path your target.
target with JTAG voltage. buffer small propagation delay (typically less than 6ns) ample drive current (+/24mA). 3.3V/2.5V/1.8V low-voltage targets, buffer TMS, TDI, ~TRST, TDO, ~EMU signals with type 74AVC16244 buffer equivalent). This buffer will support targets with 3.3V 2.5V 1.8V JTAG voltages. buffer very small propagation delay (typically less than 2ns) ample drive current (+/- 24mA). should buffers like these equivalent with very small propagation delays.
targets, buffer TMS, TDI, ~TRST, TDO, ~EMU signals with type 74AC11244 buffer equivalent). This buffer will support
JTAG Supply Buffer Type: 74AC11244 (5V) 74AVC16244 (3.3V/2.5V/1.8V) Equivalent JTAG Supply
TRST
TRST
JTAG Supply
RPVS
BTMSOE
pin)
BTMS
BTMS/VDDIO
Clock DriverType: Equivalent IDT49FCT805 (5V) IDT49FCT3805E (3.3V) IDT5T9050 (2.5V/1.8V)
Connect Signals Target Board-Level Boundary Scan Controller Note Below
BTCK
BTRST
TRST
BTDI
JTAG Supply
Note: When using boundary scan, must control ~BTRST signal such that pulsed when first applying power your target. This could done using method shown here. Note: Zero resistors substituted jumpers production boards.
PowerUpReset
SN7408
BTRST
BoundaryScanReset
Note:Connect on-board BTMS signal header BTMS/VDDIO using tri-state buffer jumper. When using buffer, buffers output must disabled when HPPCI attached JTAG emulation header Note: resistors TMS, TCK, recommended, improve noise imunity these signals. However, they required they create power budget issue with your target.
Figure HPPCI Multi-DSP Target with Boundary Scan
targets, buffer signal with clock driver that skew, high out, minimal input-to-output delay.
IDT49FCT3805E equivalent) dual 1-to-5 clock driver provides with very (<700ps) skew, (<6ns) propagation
Analog Devices JTAG Emulation Technical Reference (EE-68)
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RPEMU
4.7K
4.7K
delay, ample drive current (IOH: -24mA IOL: mA). low-voltage 3.3V targets, buffer signal with clock driver that skew, high out, minimum input-to-output delay. IDT49FCT805 equivalent) dual 1-to-5 clock driver provides with very (<200ps) skew, (<2.5ns) propagation delay, ample drive current (+/- 12mA). very low-voltage 2.5V/1.8V targets, buffer signal with clock driver that skew, high out, minimum input-to-output delay. IDT5T9050 equivalent) single 1to-5 clock driver provides with very (<25ps) skew, (<1.8ns) propagation delay, ample drive current (+/- 12mA).
Note: type clock drivers signal. signal discontinuous logic lock time will result missed critical JTAG clock cycles causing scan errors
Route traces between emulation header group with equal lengths, possible. Provide good cross-talk isolation from other signal nets.
HPPCI Multiple-DSP Boundary Scan Target without
Figure shows connections between emulation header target with multiple DSPs and/or routes between header exceed eight inches target does board-level boundary scan. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
HPPCI Multiple-DSP Target with Boundary Scan
Figure Figure show 4.7K pulldown resistor (RPD) installed ~TRST emulation header. This pull-down resistor keeps JTAG reset when emulator connected. emulator overdrive this resistor. Figure Figure show optional (recommended, required) series terminations (RT) ~EMU signals going emulator. value generally equal ZLine(PCB) minus ZDriver(DSP), where impedance represented ohms Initially these resistors zero ohms. Change them value range signal integrity problems observed with emulator. have tune value, depending condition signals. Place termination resistors close possible.
Figure shows connections between emulation header target which uses board-level boundary scan multiple DSPs. Pull-up resistors TMS, TDI, TCK) optional improve noise immunity these signals. However, they required should they create power budget issue with your target.
HPPCI Layout Requirements
Note: take advantage operation, users need minimize propagation delay their JTAG path Using routing suggestions below will long minimizing delay JTAG path your target.
Treat emulator signals (TCK, TMS, TDI, TDO, ~EMU, ~TRST) critical route signals. special attention when routing these signals. Specify controlled impedance requirement each route. This value, which
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Analog Devices JTAG Emulation Technical Reference (EE-68)
depends your circuit board logic, typically range 50-75. Minimize cross-talk inductance these signal lines using good ground plane routing emulator signal away from high-noise signals such clock lines. Keep these routes short clean possible, keep bused signals (TMS, TCK, ~TRST, ~EMU) similar length possible.
Note: emulator interface relies state line clock signal. Unreliable emulator operation result when these signals have glitches (due ground bounce, cross-talk, etc.). experience emulator problems, check these signals with high-speed digital oscilloscope.
This sequence ensures JTAG signals correct state free power Target. Once emulator poweredon, will drive ~TRST signal low, keeping test-logic-reset state until emulation software takes control. Remove power reverse order, follows: Close VisualDSP++ emulator session. Remove emulator probe from target. Install jumpers mentioned above JTAG emulation header. Remove power from target.
HPPCI JTAG
This section explains electrical mechanical specifications JTAG Pod.
HPPCI Logic
These lines must clean. buffering JTAG header, provide signal terminations appropriate your target board using series terminations (RT) discussed previously.
HPPCI Power Sequence
avoid possible damage electronics target electronics, perform following poweron sequence your target emulator. Connect your emulator host with power applied emulator before performing these steps.
Note: This sequence only operation with ICE, does pertain production targets which choose zero resistors instead jumpers. target assumed have jumpers between
HPPCI uses auto voltage sensing (BTMS/VDDIO) JTAG emulation header. auto sensing logic will automatically determine what voltage levels will drive JTAG signals target header. HPPCI logic with then adjust threshold values buffers accordingly. HPPCI will also voltage detected determine what levels will drive signals target header.
Note: Your target voltage (VDDIO) same voltage used core. Your target core voltage (VDD) could 2.5V, while your voltage (VDDIO) 3.3V. Make sure pull BTMS/VDDIO signal correct voltage plane with 4.7K resistor.
boundary scan signals (~BTRST, BTMS, BTDI, BTCK) JTAG signals (~TRST, TMS, TDI, TCK) JTAG emulation header when connecting ICE. Turn target power. Remove jumpers mentioned above from JTAG emulation header. Connect emulator probe target. Activate VisualDSP++ emulator session.
HPPCI tolerant 5VDC. will work with Analog Devices JTAG family DSPs with JTAG voltages 3.3V, 2.5V, 1.8V. will drive targets 3.3V levels. Figure details dimensions JTAG header 14-pin target end. Figure displays keep-out area target board
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Analog Devices JTAG Emulation Technical Reference (EE-68)
header. keep-out area forces connector properly seat with target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.025" square-post pin. Table includes characteristics HPPCI Pod.
Signal
~TRST ~EMU ~TRST ~EMU ~TRST ~EMU ~TRST ~EMU
5VDC
Cpin
Cload
33pF
2.3VDC
0.70
-12mA
12mA
5VDC
2.0VDC
0.8VDC
5VDC
3.3VDC
33pF
2.3VDC
0.70
-12mA
12mA
3.3VDC
2.0VDC
0.8VDC
5VDC
2.5VDC
33pF
1.90VDC
0.60
-8mA
2.5VDC
1.7VDC
0.7VDC
5VDC
1.8VDC
33pF
1.36VDC
0.43
-4mA
1.8VDC
1.2VDC
0.6VDC
5VDC
Table HPPCI Characteristics
Analog Devices JTAG Emulation Technical Reference (EE-68)
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HPPCI JTAG Connector
define switching parameters timing requirements JTAG header interface. this information when determining maximum routing lengths, loading, number buffers that tolerated target JTAG signal paths, while still meeting timing requirements HPPCI electronics.
Note: families operate frequencies supported HPPCI ICE. HPPCI software will only display frequencies supported HPPCI target session started. basis which JTAG frequencies supported HPPCI individual family JTAG timing delay numbers published Analog Devices data sheets.
0.20"
0.28"
ANALOG DEVICES
0.43"
0.29" 0.20" 0.70" 1.19"
Figure HPPCI JTAG Connector Dimensions
HPPCI Timing
This section details important timing information relating JTAG signals JTAG header HPPCI target. Figure Table
Parameter Unit
Table defines required timing parameters guaranteed operation with rates 10MHz, 25MHz, 33MHz, 50MHz.
Description TDO, ~EMU Setup Time required before Header TDO, ~EMU Hold Time required after Header Cycle time, Pulse duration, high Pulse duration, TMS, TDI, ~TRST Delay after Header TDO, ~EMU Setup Time required before Header TDO, ~EMU Hold Time required after Header Cycle time, Pulse duration, high Pulse duration, TMS, TDI, ~TRST Delay after Header TDO, ~EMU Setup Time required before Header TDO, ~EMU Hold Time required after Header
Timing Requirements: tsuTDO, tsuEMU/ 14.08 thTDO, tsEMU/ Switching Characteristics: tcTCK 99.990 100.010 twTCKH 49.995 50.005 twTCKL 49.995 50.005 tdTMS, tdTDI, tdTRST/ (1.0) Timing Requirements: tsuTDO, tsuEMU/ thTDO, tsEMU/ Switching Characteristics: tcTCK 39.996 40.004 twTCKH 19.998 20.002 twTCKL 19.998 20.002 tdTMS, tdTDI, tdTRST/ (1.0) Timing Requirements: tsuTDO, tsuEMU/ 8.42 thTDO, tsEMU/ Switching Characteristics:
Analog Devices JTAG Emulation Technical Reference (EE-68)
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tcTCK 29.997 30.003 twTCKH 14.998 15.002 twTCKL 14.998 15.002 tdTMS, tdTDI, tdTRST/ (1.0) Timing Requirements: tsuTDO, tsuEMU/ 9.92 thTDO, tsEMU/ Switching Characteristics: tcTCK 19.998 20.002 twTCKH 9.999 10.001 twTCKL 9.999 10.001 tdTMS, tdTDI, tdTRST/ (1.0) Table HPPCI Timing Information Cycle time, Pulse duration, high Pulse duration, TMS, TDI, ~TRST Delay after Header TDO, ~EMU Setup Time required before Header TDO, ~EMU Hold Time required after Header Cycle time, Pulse duration, high Pulse duration, TMS, TDI, ~TRST Delay after Header
Figure HPPCI Timing Waveform
These current available rates supported HPPCI ICE. setup hold values ~EMU signals table take into account HPPCI hardware delays only. When determining overall timing margin, must include JTAG path delays your target including DSP.
setup hold requirement values based worst case maximum delay HPPCI hardware. Typically, setup hold time requirements will considerably smaller than values table. have complex JTAG emulation path with relatively long propagation delay, want perform timing analysis determine your
Analog Devices JTAG Emulation Technical Reference (EE-68)
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design will operate JTAG frequency plan use. This analysis will determine JTAG emulation path sufficient timing margin allow operation JTAG frequency will operating cases, timing margin should positive number. general rule, margin should least full clock period. calculate negative margin, should make changes your target reduce JTAG signal path delay slowing down frequency increase your margin. This assumes slowest frequency 10MHz. should aware when doing your analysis, delay numbers given based worst case delay. Typically, logic will tend somewhere middle between minimum maximum delay, although this cannot guaranteed. your margin negative, very close, want typical numbers still negative. Again guarantees made when using typical numbers. Development test application custom hardware thus begin without debugging emulation port. Check site periodically updates this document that will contain emulator design details. find this document
Reference
IEEE 1149.1 JTAG standard sponsored Test Technology Standards Committee IEEE Computer Society, published IEEE. latest versions time this publication IEEE 1149.1-1990 IEEE 149.1a1993. order copy, call IEEE 1-800-678-4333 Canada, 1-908-981-1393 outside Canada. also visit IEEE standards site http://standards.ieee.org/. 1999 2003 Analog Devices, Inc.
Conclusion
Assuming recommendations described here followed, designing JTAG emulation interface Analog Devices target board straight forward, emulation interface should work with minimal effort.
Analog Devices JTAG Emulation Technical Reference (EE-68)
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Document History
Version Release Date July 2003 Description Updated document discussions ~TRST signal JTAG Emulation header jumper requirements. Most sections document were effected. Change keep clearance requirements larger HPPCI pod. Divided document into discussion Legacy products HPPCI product. Added HPPCI information. December 2002 August 2001 March 2001 August 2000 February 2000 December 1999 Updated sections added timing information Update power sections Update target connections Update logic General update Initial Release
March 2003
Analog Devices JTAG Emulation Technical Reference (EE-68)
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