EE-79 Copyright 1999, Analog Devices, Inc. rights reserved. Analo

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EE-79 Copyright 1999, Analog Devices, Inc. rights reserved. Analo

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Engineer-To-Engineer's Note
EE-79
Copyright 1999, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Technical Notes using Analog Devices' components development tools
EPROM Booting Host Mode With 218x Processors
Written Last Modified: Greg 9/23/98
sheet, available website following URL; http://www.analog.com
Full Memory Mode
Full Memory Mode gives complete external address data busses found ADSP-2181. Full Memory Mode, ADSP-2185/2186 behaves like ADSP-2181 with IDMA port removed. There external data bus, address memory select signals. Byte memory accessed using middle eight bits data data. upper eight bits data together with address pins provide address byte memory space. these features behave exactly same ADSP2181. Hold cases (autobuffer cycle stealing, external memory accesses with wait states, etc.) simplified because IDMA transfer will never occur. this mode IDMA port disabled deselected pulled high ADSP-2181.
This Note will explain boot Analog Device's adsp218x processor (2184/85/86/87/89) Byte Memory interface (BDMA) while configured host memory mode. Host memory mode allows host processor boot access DSP's internal memory Internal Direct Memory Addressing port (IDMA). Normally, these processors configured boot only methods; from eprom (full memory mode), from host processor IDMA port (host memory mode).
Overview
previously mentioned processors feature 100pin package which uses multiplexed external that following functionality: Full Memory Mode Provides complete external address data busses found ADSP-2181. Allows BDMA operation with full external overlay memory capability. IDMA functionality disabled Host Mode: Allows complete IDMA port operation with limited external addressing capabilities.
Host Mode
Host Mode gives full IDMA port found ADSP-2181, there limitations external memory bus. Host Mode lower eight bits data bus, D[7:0] become IDMA control pins pins. upper bits address A[13:1] become lower bits IDMA address/data bus, IAD[12:0]. Pinout Diagram tables Memory Interface Pins ADSP2185/6/7L Data Sheets show alternate functions each either major mode. IDMA transfers occur exactly ADSP-2181.
functionality external dependent upon setting external mode processor. logic state this acknowledged processor during reset; mode configures full memory mode, mode configures processor host memory mode. Note: state mode must changed once begins execution. more information operation configurations Mode pin, please refer appropriate ADSP-2185/6/7L data
Accessing Peripherals
external Host Mode still remains available limited form. DSP's address pins A[13:1] changed IAD[12:0] when Mode high. result, chip cannot drive address externally. However, internally chip will behave external accesses occurring.
external will behave ADSP-2181 system where address bits A[13:1] data bits D[7:0] ignored. upper bits data still used external data transfers, only address available, Writes Data Memory Space will activate appropriate memory select(s), /WR, place data D[23:8], drive single address Program memory reads writes behave similarly have added consideration register. program memory reads writes only upper bits will available externally. When data written external program memory upper bits will driven data pins [23:16]. register will still latch lower eight bits program memory word, they will driven externally. read external memory occurs, external pins will control value register, register will written with ones. missing address bits restrict using external with conventional memory device which separated address data buses. These external transfers might usable with shared address/data memory chips used communication with ASIC. memory selects will still active, each memory space effectively collapsed into external addresses, address
What Does This Mean?
Since configured host mode, external address limited pin, What this means that need address generators drive external address pins EPROM facilitate booting DSP. (Please refer included data sheet more information operation address generators, Philips part number 74HC4040.) caveat building this hardware configuration that address generators output sequential address values, while prom splitter 218x family does not. executable file must massaged allow prom splitter output sequential data eprom. Normally, prom splitter (when used conjunction with -2181 -loader switches), prepends boot loader kernel beginning eprom file. This done because development tools 218x family different boot paging scheme than rest 21xx family processors initialize program memory segments, program data segments, data memory segments.
Real Solution
Here following steps that needed complete design: Create system file (*.sys) 2101 processor that declares chip memory space 218x system, also includes boot page segments. Declare boot page segment your source code's .module directive. Replace symbol your *.exe file with symbol. (The symbol located second line *.exe file; edit this file with text editor, since file written ASCII file format.)
Byte Memory Accesses
BDMA accesses still allowed Host Mode. However, because address pins A[13:1], operate bus, construction complete byte address impossible, without external circuitry. Byte memory addresses ADSP-2181 were 22-bit addresses formed from external data pins D[23:16] address pins A[13:0]. Host Mode D[23:16] only address bits available externally. values external data pins D[23:16], will values contained BMPAGE field BDMA Control Register, located internal address 0x3fe3 processor. will byte addresses even byte addresses. BDMA IDMA timing cycle stealing same ADSP-2181. BDMA with limited address bits available still provides flexible interface DSP. Without full address bits addressing memory will more difficult host microcontroller communication possible because order byte sequence known. information byte sequencing, refer Byte Memory Word Formats ADSP-2100 Family User's Manual.
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Technical Notes using Analog Devices' components development tools Phone: (800) ANALOG-D, FAX: (781) 461-3010, FTP: ftp.analog.com, EMAIL: dsp.support@analog.com
following example system file (Boothost.sys) used build this project:
.system BootHost; .adsp2101; .mmap0; .seg/pm/ram/code/data/abs=0 .seg/dm/ram/data/abs=0 .seg/rom/boot=0 boot0[2048]; .endsys; int_pm[0x4000]; int_dm[0x3c00];
dm(0x3fe3) ay0; 0x1; dm(0x3fe4) ay0; nop; nop; nop; nop;
{set BDMA Control}
{set BWCOUNT, start BDMA}
lshift (LO); {shift holding data} dm(0x3fdf); dm(0x3fe5) ay1; rti;
RESETPF: 0x40;
From this example system file, you'll notice that we've declared adsp2101 system with roughly words respectively!! This step required "trick" tools into using boot segments, (".seg/rom/boot=0 boot0[2048];"), with 2181 memory model.
rts;
START: 0x0400; dm(0x3fff) ax0;
here code example. Here you'll notice again that boot segment used this source file (located line which normally illegal 218x system. But, since we've tricked tools into using modified 2101 system file, everything will work accordingly.
0x0000;
{set IOWAIT
dm(0x3ffe) ax0; imask 0x200; 0x1f7f; dm(0x3fe6) ax0; {make output PF7} {enable IRQ2}
Filename Boothost.DSP .module/ram/boot=0 #include "vectab.h" #define IRQ2ON booty;
0x80; dm(0x3fe5) ax0; 0x40; {make {set data first
reset fl0; cntr 0x6;
IRQ2INT: toggle fl0; none pass sr0; call resetpf; 0x80; dm(0x3fde) 0x7fdf; dm(0x3fe0) ax0; 0x0; dm(0x3fe2) ay0; 0x3fde; dm(0x3fe1) ay0; 0x7; {set BIAD} {set BEAD} {set IDMAA DATA reg} {set data BDMA {reset data}
FLASHER until cntr 0x1000; FLASHER1 until cntr 0x2000; FLASHER2 until FLASHER2: nop; {wait IRQ2}
FLASHER1: nop; FLASHER: toggle fl0; NOWHERE: idle; jump NOWHERE;
#include trailer.h"
EN-79
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Technical Notes using Analog Devices' components development tools Phone: (800) ANALOG-D, FAX: (781) 461-3010, FTP: ftp.analog.com, EMAIL: dsp.support@analog.com
.endmod;
boothost.dsp program
References Appendices
Please refer chapters five 2100 Family Assembler Tools Simulator Manual, (System Builder PROM Splitter, respectively), well latest version development tools release notes more information usage functionality these tools. (All these documents downloaded from website following URL; sp_prdoc.html.) Also included this application note schematic that shows interface used this design. more information please contact Analog Devices 1-800-ANALOGD, http://www.analog.com/dsp.
From this point, we're able build executable file. We'll following command line(s) prompt:
bld21 boothost asm21 boothost.dsp boothost ld21 boothost boothost.ach boothost
first line creates architecture file from file boothost.sys. second line assembles file boothost.dsp creates object file boothost.obj. third line creates executable file boothost.exe using boothost.obj boothost.ach files.
this step build need perform more task; need manually edit executable file generate program memory executable file, executable file. This done performing following steps;
Edit file boothost.exe. Change first line file from @PA. (This changes file from bootable file program memory executable file.) Save file boothost.exe.
this point, able perform final step build, typing following command line prompt; spl21 boothost boothost -loader -2181. This will create file boothost.bnm, that burn into EPROM system.
EN-79
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Technical Notes using Analog Devices' components development tools Phone: (800) ANALOG-D, FAX: (781) 461-3010, FTP: ftp.analog.com, EMAIL: dsp.support@analog.com
D7/IWR D6/IRD D5/IAL D4/IS D3/IACK D2/IAD15 D1/IAD14 D0/IAD13
IAD15 IAD14 IAD13
RESET EINT ELIN ELOUT ECLK RESET ERESET SCLK1 RFS1 TFS1 SCLK0 RFS0 TFS0 IRQ2/PF7 IRQL1/PF6 IRQL0/PF5 IRQE/PF4
IAD0 IAD1 IAD2
PF2/MODEC PF1/MODEB PF0/MODEA PWDACK A1/IAD0 A2/IAD1 A3/IAD2
RESET
OE/VPP 27C080
218X_100L
74HC04
CLOCK
74HC4040
IRQ2
A4/IAD3 A5/IAD4 A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 CLKIN XTAL CLKOUT IOMS
RESET
CLOCK
IAD4 IAD3 IAD12 IAD11 IAD10 IAD9 IAD8 IAD7 IAD6 IAD5 74HC4040
OSCILLATOR
74HC32
74HC244 74HC244 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 ANALOG DEVICES TECHNOLOGY NORWOOD, 02062 Title IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 IAD6 IAD7
218X 100L BDMA BOOT ONLY CIRCUIT Document Number Sheet
Size Date:
Monday, September 1998
Figure Example schematic Host Mode EPROM booting system
EN-79
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Technical Notes using Analog Devices' components development tools Phone: (800) ANALOG-D, FAX: (781) 461-3010, FTP: ftp.analog.com, EMAIL: dsp.support@analog.com

EE-79 Copyright 1999, Analog Devices, Inc. rights reserved. Analo

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