Notes using Analog Devices' components development tools Phone: (800)

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Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Booting ADSP-2191 using Atmel AT25020N EZ-KIT LITE Evaluation Board
Introduction: Analog Devices ADSP-2191 first that provides booting SPI. This note shows interface ATMEL EEPROM (AT25020) order boot ADSP-2191 interface. With help little project, this note will describe create loader file which stored EEPROM used boot DSP. loader file format well Hardware will covered order build whole project.
W2.0:
latest version VisualDSP++2.0 creates loader files suitable booting (Serial Peripheral Interface) automatically. Open Analog Devices VisualDSP++2.0 make project. linker description file (LDF) ADSP-2191 project first. This file defines entire address range identifiers individual sections memory with labels.
Figure create project with VisualDSP++
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Finally, existing assembly file your choice create file add) header file "def2191.h" which defines ADSP-2191's memory-mapped registers. ADSP-2191 processor selected project build. This VisualDSP++2.0 will build executable file "filename.dxe" which required debugging your program simulator loading debugging emulator. Note: Ensure have most recent loader "elfloader.exe". Find file. prepare VisualDSP++ booting please open "Project Options" dialog from "Project" menu. shown figure project option change option "type" "target" frame from "DSP executable file" "Loader file". This causes VisualDSP++ create loader file which stored non-volatile memory your choice. ADSP-2191 able boot from different memory types. select appropriate booting device, select "Loader" control "Project Options" Boot Type" "SPI". Select binary format "Format" frame create binary file that suitable most common programmers shown figure ASCII format lets VisualDSP++ loader "elfloader.exe" build loader file ASCII format. This file accessed text editor easily. binary file accessed using binary editor only. Finally, press "OK" button dialog "Project Options" again rebuild whole project again. file with same name project extension .ldr will generated. This .ldr file loaded programmer written booting device this case AT25020 EEPROM) straight forward.
Figure "Project" options dedicated your project
Figure "Loader" options dedicated your project
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
ADSP-2191 Startup basics:
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
ADSP-2191 booting scheme that different from former DSPs. boot kernel located on-chip stored 24-bit wide, ROM. After hardware reset processor starts running address FF0000h. Automatically boot kernel will processed. There three input pins ADSP-2191 whose input state upon hard /RESET determines booting mode. state three pins (OPMODE, BMODE0 BMODE1) sampled rising edge /RESET captured into corresponding bits (0,1 System Configuration Register software (boot kernel). case booting kernel branches booting subroutine. initializes port using SPISS0 sends first commands EEPOM. Referring AT25020 data sheet first byte sent EEPROM order receive data value "0x3" (Read Timing). Followed this command starting address sent this case). more information see, section titled Hardware investigations. Received data coming from serial EEPROM will then unpacked stored appropriate memory locations following section will explain.
Figure Memory ADSP2191
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Serial Peripheral Interface (SPI):
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
ADSP-2191 serial peripheral interface industry standard synchronous serial link that helps communicate with multiple SPI-compatible devices. peripheral synchronous, 4-wire inter-face consisting data pins, MOSI (Master Slave MISO (Master Slave Out); device select pin, SPISS (SPI Slave Select); gated clock pin, (Serial Clock). With data pins, allows full-duplex operation other SPIcompatible devices. also includes programmable baud rates, clock phase, clock polarity. operate multi-master environment interfacing with several other devices, acting either master device slave device. multi-master environment, interface uses open drain data driver outputs avoid data contention. Figure provides block diagram ADSP-2191 Interface. interface essentially shift register that serially transmits receives data bits, time rate, to/from other devices. data transmitted received same time through shift register. When transfer occurs, data simultaneously transmitted, shifted serially shift register, data received, shifted serially other same shift register. synchronizes shifting sampling data serial data pins, MOSI MISO.
Figure ADSP-2191 Block Diagram
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Boot stream format: During booting kernel follows protocol decode loader file shown below. data received from EEPROM eight bits wide. Each byte received will checked, shifted together than stored memory. processor stores Header (Control Word, Flag known TAG) Start Address, Page Word Count) data memory first. With help these contents processor knows where store instructions data.
Control Word will stored memory beginning boot sequence, only. these values ignored completely during booting. just booted mode well with having wait states required. Each instruction data block starts with flag. This flag includes whether store instr./data well zero filling final block detection. start address indicates location first word memory. address will incremented following words automatically. Control Word bits): (SPI Width bits) (Wait State Information's bits)
Flag bits): (Indicates memory locations bits bits)
Start Address bits): (Indicates start address corresponding memory location)
page extents address order access more memory.
Page bits): (Extents address range access higher memory)
Instructions placed one, consecutively. Word Count indicates number instructions following this header.
Word Count bits): (Holds number words (instructions data) that must loaded starting start address
Finally instructions, just many instr. countered Word Count many bits Data Words expected. Beginning after Word Count placed memory dedicated Flag Word starting address held Start Address. Flag 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Function Final Final Zero-init Zero-init Zero-init Final Zero-init Final Reserved
Data Words bits bits): (Instructions data self)
following Flag indicates next instr./data words storing different areas.
Flag bits): (Indicates memory locations
Start Address bits): (Indicates start address corresponding memory location)
Figure Boot stream format
Table Boot Flags (Tags)
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Format loader file "Filename.ldr":
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
This section will describe loader file that been build VisualDSP++ 2.0. whole file will analyzed will explain processor does unpacks contents order place code data right location DSPs memory. Figure shows file ASCII format. programmer place data starting address EEPROM. Each line (address) contains byte (byte wise organized). next unpack data boot kernel shown table
Address 0x0:
Figure Loader file created VisualDSP++
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Wait State Width
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Table figure figure show booted data will shifted together placed memory correctly. first byte received from EEPROM 0x02F (Wait State) using loader file above. This byte will stored memory space. following zero (Width) next address. first word header (Flag) will loaded seen table bytes must shifted together order form first sixteen value. LSByte received first placed into shifter MSByte next shifted LSB. result stored into place data memory. whole header unpacked same way. After header completely transferred first instruction following header unpacked placed memory. works follows. Decode: Flag: data bits wide must placed Address: start address Page: Internal memory space Word Count: only instruction same procedure starts next flag again.
Received Bytes Wait States Data Width Flag Flag Address Address Page Page Word Count Word Count Instr./data 8-15 Instr./data Instr./data Table Unpacking
Flag data Address Page Word count Instruction //Jump Start Flag Address Page Word count Flag data Address Page Word count Instruction //i0 0x300; Instruction //m0 0x0001; Instruction //l0 0x000; Instruction //ax0 0x0000; Instruction //reg(b0) ax0; Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //ax0 pm(i0+=m0); Instruction //NOP; Instruction //Jump Loop1; Flag Zero init final Address Page Word count //272 locations Zero init
Figure Loader file decoded (DSP format)
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
next block implemented fill defined area with zeros. order save EEPROM memory space zero filling will done automatically. shown Table flags will force boot kernel fill certain memory area zeros. data must added header. header includes start address word count specify area filled. After this done next header processed. convention, final block always type "zero fill DM". This contents flag (0x07) lets jump zero internal space start executing loaded code. Hardware investigations: AT25020 connected easily shown figure This EE-Note dedicated ADDS-2191M-EZLITE connect EEPROM. Bread Board Connector offers signals required connection. Note: ceramic capacitor (100nF) connected power supply placed very close device (AT25020) decouple. Four pull resistors (10k) connected pins ensure defined state pins.
Figure Schematic circuit placed Bread Board Area
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Clock
diagrams illustrates EEPROM accessed. After reset initializes Port asserts chip select line (SPISS0) starts transfer. seen clock line configured transfer data eight bits wide. rate 122.0 kHz.
SPISS
Diagram Timing Clock Chip select line(SPISS) Clock
Diagram shows Transfer line EEPROM (MOSI) "Master Slave In". first sent byte puts EEPROM read mode (referring AT25020 Data Sheet). next sets start address which zero this case. Starting from this point EEPROM sends data continuously long port requesting (Clock runs). MOSI line will held ever after start address been sent.
MOSI
Diagram Timing Clock Transfer line (MOSI)
Once read instruction start address received EEPROM first data will sent immediately next clock cycles. Diagram shows first byte coming from address zero EEPROM. EEPROM increments address pointer automatically sends second data next clock cycles. This whole program code will transferred DSP. After transfer boot kernel disables port again starts executing code placed program memory jumping address
Clock
MISO
Diagram Timing Clock Receiver line (MISO)
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Notes using Analog Devices' components development tools Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
Finally diagram shows part data transfer DSP.
Diagram Timing Clock Receiver line (MISO)
Conclusion: This note should have given idea booted interface. Furthermore been described hole project from beginning booting hard- software. Attached this document please find software project used create this file latest loader patch. (elfldr2191.dll).
References: VisualDSP++ Getting Started Guide ADSP-21xx DSPs VisualDSP++ Linker Utilities Manual ADSP-21xx DSPs ADSP-2191 -KIT LITE Manual ADSP-2191 Hardware Reference Manual documents: ATMEL AT25020 data sheet http://www.atmel.com
Copyright 2001, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.

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