Frank Zeller Digital Signal Processoring Solutions Typically, int

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Setting TMS320C2xx Interrupts Assembler
Frank Zeller Digital Signal Processoring Solutions
Typically, interrupts generated devices that need give take data from Texas Instruments TMS320C2xx, example, analog-to-digital (A/D) digital-toanalog (D/A) converters other processors. When C2xx recognizes interrupt signal, suspends execution code specific particular interrupt event (Interrupt Subroutine). C2xx family supports three four different sorts interrupts:
Maskable external interrupts (INT1-3) Non-maskable external interrupts (NMI, Maskable internal interrupts (TINT, RINT, XINT, TXRXINT) Software interrupts (INT8-16, INT20-31)
This document shows simply possible general these interrupts. TMS320C2xx handles interrupts three phases: Reception interrupt request Acknowledgement interrupt Execution corresponding Interrupt Subroutine (ISR)
Contents
Setting TMS320C2xx Interrupts Assembler Setting TMS320C2xx Interrupts Hardware.11
Figures
Figure Circuit Diagram.11
Tables
Table Register Setting Table Memory Allocation.9
Digital Signal Processing Solutions
December 1998
Setting TMS320C2xx Interrupts Assembler
Introduction
Typically, interrupts generated devices that need give take data from Texas Instruments TMS320C2xx, example, analog-to-digital (A/D) digital-toanalog (D/A) converters other processors. When C2xx recognizes interrupt signal, suspends execution code specific particular interrupt event (Interrupt Routine). C2xx family supports three four different sorts interrupts:
Maskable external interrupts (INT1-3) Non-maskable external interrupts (NMI, Maskable internal interrupts (TINT, RINT, XINT, TXRXINT) Software interrupts (INT8-16, INT20-31)
This document shows simply possible general these interrupts. TMS320C2xx handles interrupts three phases: Reception interrupt request Acknowledgement interrupt Execution corresponding Interrupt Routine (ISR)
Interrupt Management
Flags
When valid signal generated interrupt pin, corresponding flag (Interrupt Flag Register). Because INT2/INT3 share same IFR, additional flags (FINT2 FINT3) located (Interrupt Control Registers) allow distinguish between both.
Masks
user select which interrupts TMS320C2xx should respond given time. written mask (Interrupt Masked Register) enables corresponding interrupt. This includes "combo-flags":
INT1/HOLD INT2/INT3
Hence, separate combined masks, additional bits (MINT2 MINT3 ICR) allow distinguish those interrupts.
Setting TMS320C2xx Interrupts Assembler
HOLD INT1 signals share same external pin. Although INT1/HOLD combined IFR, they mutually exclusive. MODE (bit ICR) separates both types inquiries:
MODE HOLD selected MODE INT1 chosen
Even through HOLD shown IMR, HOLD function cannot masked.
Controls
(Interrupt Controls Register) provides capability
Individually mask INT2 INT3 (MINT2 MINT3 bits) Clearly identify which interrupt INT2 INT3 been requested (FINT2 FINT3 bits) Differentiate HOLD (MODE bit)
Global Enabling
IN(Interrupt Mode bit, ST0) globally enables disables maskable interrupts.
enables masked interrupts inhibits masked interrupts
Interrupt Initialization
Registers Definition
Some registers mapped data space (from 0000h 0060h). .mmregs directive defines global symbols memory-mapped registers (listed page 5-35 TMS320C2xx User's Guide, literature number SPRU127B). facilitate access mapped registers, define address on-chip registers mapped space. This table depends target DSP. on-chip registers mapped space TMS320C203 are: .set 0FFE8h ;CLK Register .set 0FFECh ;Interrupt Control Register SDTR .set 0FFF0h ;Synch. Serial Port Transmit/Receive Register SSPCR .set 0FFF1h ;Synch. Serial Port Control Register ADTR .set 0FFF4h ;Async. Serial Port Receive/Transmit Register ASPCR .set 0FFF5h ;Async. Serial Port Control Register IOSR .set 0FFF6h ;Input/Output Status Register. .set 0FFF7h ;Baud Rate Divisor Register .set 0FFF8h ;Timer Control Register .set 0FFF9h ;Timer Period Register .set 0FFFAh ;Timer Counter Register WSGR .set 0FFFCh ;Wait State Generator Control Register
Setting TMS320C2xx Interrupts Assembler
Steps Initialization
During initialization processor, user define working environment enable/disable interrupts according application. distinguish three steps initialization process.
Global Disable Interrupts
prevent interruption processor initialization, interrupts disabled setting INbit using following command: SETC disable interrupts
Mask Interrupts
setting. this memory-mapped register assuming that value contained IMR_Value: SPLK IMR,#IMR_Value mask interrupts
setting. this I/O-mapped register assuming that value contained ICR_Value: SPLK #IC_Value,TEMP TEMP,IC ;load ICR_Value temporary variable ;write ICR_Value
Flag Clear
avoid servicing interrupt, flag bits have cleaned cleared writing each whereas flag cleared meanwhile mask (see previous point). IFR_CLR .set SPLK 0FFFFh #IFR_CLR,IFR
Global Reenable Unmasked Interrupts.
Before starting main function, INbit reset. Thus, unmasked interrupts enabled. CLRC IN;enable unmasked interrupts
Table Register Setting
Interrupt
INT1 HOLD INT2
Condition
Condition involved
Observations mutually exclusive with
HOLD
mutually exclusive with INT1
TINT
INT3
Setting TMS320C2xx Interrupts Assembler
Vector Table Allocation
Once interrupt received, C2xx branches corresponding subroutine called (Interrupt Service Routine). C2xx follows branch instruction place predetermined address (the vector location) executes have written. vector location table shown page 5-16 TMS320C2xx User's Guide, literature number SPRU127B). user must address 0000h program space command file (interr.cmd). Typically, .sect directive used. each interrupt, words reserved: code branch instruction other address branched. those interrupts unused, replace branch instruction directive, .space 2*16. reserves 2*16 bits. following example interrupt table .sect "vectors" INIT IT1HOLD INT2_3 TINT ;reset ;INT1/HOLD ;INT2 INT3 ;TINT
Interrupt Service Routine
Before returning from interrupt, generally need reenable unmasked interrupts. Thus, ends with: CLRC IN;reenable unmasked interrupts ;return from interrupt
HOLD INT1
Both signals connected same pin. Thus, they share same mask same flag. MODE ICR) distinguishes them. know which subroutine branched, test MODE. MODE `0', HOLD state ;otherwise, interrupt INT1 served. function this selected user depend part running program. example, *Registers values FLAGIT1 .set ICRHOLD .set ICRINT1 .set SPLK 0010h 0000h 0010h ;identify HOLD mode ;Hold mode ;INT1 mode
#ICRINT1,TEMP ;set-up INT1 (use ICRHOLD HOLD) TEMP,IC ;INT1 enabled
code below possible test.
Setting TMS320C2xx Interrupts Assembler
IT1HOLD:
LACL BCND SETC CLRC CLRC LACL SPLK
TEMP,IC TEMP FLAGIT1 HOLD,EQ
;capture ;test MODE HOLD mode, branch HOLD ;interrupt1 service routine ;XF=1, shows that INT1 operating ;repeat 32768 times ;INT1 ended ;enable interrupts before return ;return from interrupt ;save current ;mask interrupts ;only positive edge INT1/HOLD ;may issue HOLD mode
INT1:
TEMP2 IN
HOLD:
#1,IMR
IDLE SPLK SACL CLRC
;power down mode ;(HOLD mode-HOLDA asserted) #HOLD_CLR,IFR ;clear HOLD prevent service ;restore mask IN;enable unmasked interrupts before return ;return from HOLD mode
There three methods exiting HOLD mode while de-asserting HOLDA:
Rising edge INT1/HOLd Reset
Even other unmasked interrupt exit idle state, HOLD would properly left (the HOLDA will de-asserted). That current saved beginning Hold subroutine changed 0001h (only INT1/HOLD enabled) before idle. rising edge INT1/HOLd pin, idle state exited restored.
INT2 INT3
flag both INT2 INT3. This cleared automatically when either interrupt serviced. determine which received, must read FINT2 FINT3 then branch required proper place ISR.
Setting TMS320C2xx Interrupts Assembler
FLAGIT2 IMR_VAL ICR_VAL
.set .set .set
0004h 0002h 0003h
;mask differentiate INT2 from INT3 ;IMR mask enable INT2 INT3 ;ICR value unmask INT2 mask INT3 0001h ;ICR value mask INT2 unmask INT3 0002h ;ICR value unmask both INT2 INT3: 0003h ;capture ;test FINT2 ;branch INT3 subroutine FINT2=0 ;here corresponding INT2 ;here corresponding INT3
INT2_3:
INT2: INT3:
LACL BCND
TEMP,IC TEMP #FLAGIT2 INT3,EQ
FINT2 FINT3 cleared automatically CPU. Consequently, clearing done interrupt subroutine. TEMP,IC TEMP,IC ;capture ;clear flag
TINT
timer consists three I/O-mapped registers. process used value those registers according timing rate described TMS320C2xx User's Guide, literature number SPRU127B.
(Timer Control Register) (Period Register) (Timer Value Register)
Timer setup generally done during initialization using following steps: Stop timer (TSS `0', TCR) initialize TDDR value (1st byte TCR). Initialize value. Load with with TDDR start timer.
leads following code:
Setting TMS320C2xx Interrupts Assembler
*Following values have been computed generate TINT rate with running with internal cycle time nsec. 2499d 9C3h TCR_STOP .set 0010h ;stop Timer load TDDR TCR_RUN .set 0020h ;load with TDDR (TRB ;load with (TRB ;start Timer (TSS PRD_VAL .set 09C3h ;Configuration Timer Period Register *The following lines configures Timer SPLK #IMR_VAL,IMR SPLK SPLK SPLK TCR_STOP,TEMP TEMP,TCR PRD_VAL,TEMP TEMP,PRD TCR_RUN,TEMP TEMP,TCR
;Mask interrupts: enables TINT ;stop Timer ;initialization TDDR ;initialization
CLRC IN
;load with ;load with TDDR ;start Timer ;enable interrupts
Setting TMS320C2xx Interrupts
Program Developed
Compiler
TMS320C2x/C2xx/C5x Compiler compatible with ANSI standards made preprocessor, parser, optimizer code generator. code generator produces assembly code that assembled linked.
Runtime Support
Some tasks that program must perform (e.g., memory allocation, string searches part language. ANSI standard defines complete runtime support functions performing these tasks. TMS320 fixed-point compiler includes library that contains ANSI standard runtime support functions gathered libraries:
rts2xx.lib (TMS320C2xx standard runtime support functions) rts.src (source library functions).
Both files described TMS320C2x/C2xx/C5x Optimizing Compiler User's Guide, literature number SPRU024D.
Setting TMS320C2xx Interrupts Assembler
Linker
user must create linker command file that specifies precise placement sections. structure linker command files used program remains same assembly program. fact, when linking code through, following considerations must observed
both stack heap size using -stack -heap options. Allocate seven sections produced C-compiler into memory. These include four initialized sections three uninitialized sections.
Table Memory Allocation
Directive .text .cinit .switch .const .bss .stack .sysmem Type initialized initialized initialized initialized uninitialized uninitialized uninitialized Description executable code data tables initialize global static variables tables switch statements data constants declared const global static variables system stack heap (dynamic memory) Link program memory program memory program memory data memory data memory data memory data memory
Initializing Environment
Before running program, environment created. This done either using boot.asm module rts2xx.lib) writing your boot routine. both cases, this boot routine ensure four operations
Initialization stack (creation .stack section setup) This step performs creation .stack section initialization both stack frame pointers. Initialization status registers. This allows starting processor known state. Auto-initialization global variables Calling main function forget that program necessarily main function.)
Interrupt initialization
This section describes access involved registers from There three types registers:
Those mapped space Those mapped data space Status registers (ST0 ST1)
Setting TMS320C2xx Interrupts Assembler
I/O-Mapped Registers
first thing declare these registers: example: Name #define Address 0xFFEC /*Interrupt Control register*/
access these registers writeport readport functions. These functions assembler-coded functions find inout.asm. address depends used DSP. Register name writport ((int Register name readport((int Value written register IC_Value); Temp variable &I);
Data-Mapped Registers
First, these registers have defined: unsigned *IMR (unsigned 0x0004; unsigned *IFR (unsigned 0x0006; /*c203 definition/ /*c203 definition/
write into these registers follow this statement: *IMR IMR_Value; This equivalent SPLK read those registers use: IMR_BUF *IMR; #IFR_CLR,IFR");
Status Registers
status registers only accessed using asm-statements, such shown above.
Setting TMS320C2xx Interrupts Assembler
Hardware
Figure Circuit Diagram
Hardware
circuit diagram shown Figure complete. suggests method there other options that offer improved operation.
Comments
DIV1 DIV2 chosen input clock mode clock mode*1. detailed information Reset pin, please consult D/S. booting from EPROM just using external memory.
Setting TMS320C2xx Interrupts Assembler
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Setting TMS320C2xx Interrupts Assembler

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