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EE-181

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EE-181
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Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus
Contributed by Thorsten Lorenzen April 17, 2003
1 Introduction
The purpose of this note is to describe how to hook up video devices like a CIF (Common Interface Format) Single-Chip Digital Camera to the external bus of the ADSP-BF535 Blackfin® Processor. Because of its architecture and video processing capabilities, Blackfin Processors will interface with video devices. The ADSP-BF535 as the first part of the Blackfin family is not equipped with a standard interface that glueless interact with video devices. This note is dedicated to show how the Asynchronous Interface can be used to receive video in CIF sizes.
and must be linked to the ADSP-BF535 for data transfers. Additionally, some pins are required for device control and configuration purposes. The pin HREF asserted (polarity can be chosen) indicates active video pixels (image data).
2 Output Format of the OV6630
The OV6630 is a CMOS Image sensor provided as a single chip video / imaging camera device designed to provide a high level functionality in a single, small-footprint package. For more details about the functionality it is referred to the internet address below. In order to explain the way been accessed by the ADSP-BF535 Processor see the schematic of the required output pins in figure 2.1. The datasheet for the OV6630 can be found at www.ovt.com As it can be seen in figure 2.1 the pins Y7:0 and UV7:0 are required to transfer data. The PCLK represents the clock aligned to the data. Each raising edge of the PCLK will indicate valid data on the bus. These pins are necessary
Figure 2.1
Because of the programmable sensor size as it is discussed below HREF provides a way to distinguish between active video pixels and blank data. The blank data of the modified senor field will also be transferred and is represented by hex "10" on Y7:0 and hex "80" UV7:0. Figure 2.2 shows a transfer of one pixel, blanking and HREF indicating an active pixel. Due to the configuration the sensor is set to output over a 16 -bit bus in this note. One pixel exists of one byte of luminance and one byte of
chrominance information that can be transferred the same time. the VSYNC pin on channel 1 and the HREF pin on channel 4. It can be seen if the sensor is set to transfer e.g. 200 lines the HREF will be asserted 200 times also. Each start of frame will be indicated by VSYNC around 2 ms before HREF asserts.
Figure 2.2
The windowing feature of the OV6630 image sensors allows user-definable window sizing as required by the application. Window size setting (in pixels) ranges from 2 x 2 to 356 x 292, and can be positioned anywhere inside the 356 x 292 boundary. Note that modifying window size and / or position does not change frame or data rate. The OV6630 imager alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical region. The default output window is 352 x 288. Figure 2.3 shows it graphically.
Figure 2.4
3 Asynchronize Interface of the ADSP-BF535 Blackfin Processor
The Processors asynchronous interface is used to receive the video data. 32-bit data can be fetched in a manner it is shown in figure 3.1.
Figure 2.3
In order to detect the first line of each frame the signal VSYNC asserts before. Figure 2.4 shows
Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus (EE-181) Page 2 of 10
Figure 3.2
Figure 3.1
As mentioned in the ADSP-BF535 Blackfin Hardware Reference Manual after a read cycle is initiated the Async Memory Select line ( / AMS) , Async Ouput Enable line ( / AOE) and the Async Read Enable line ( / ARE) become asserted. After a multicycle "Read Access" delay (Configured by the Async Interface Bank Control Register), the / ARE pin normally de-assert to complete the read operation. But if the interface is configured to extend the access, the / ARE pin remains low until the ARDY pin has been sampled high. The data will be fetched one cycle after this happened. Due to the architecture of the ADSP-BF535, a DMA-controlled data download is somewhat non-intuitive. Each data transfer is split into bursts of eight read access. After the burst, a gap appears because of internal bus activity. Figure 3.2 illustrates this. As shown in the figure, the first DMA is set up to read 32 data words (shown as Channel 2, the / ARE signal). The large gap before the next DMA is required for loading the next DMA descriptor.
Note also that each DMA transfer is split into bursts of eight accesses (in this configuration, four bursts per DMA execution). Understanding this behavior is crucial for developing a proper DMA interface. Figure 3.3 zooms into one of these burst patterns to analyze how many cycles are taken for each access.
Figure 3.3
The peripheral clock "SCLK" is displayed in channel 1 and channel 2 shows the / ARE pin. After eight read strobes are done nine extra cycles are taken to place the data into internal memory.
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4 Interface the ADSP-BF535 Processor into the OV6630
5 Data Structure and Improvements
Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus (EE-181) Page 4 of 10
Figure 4.1
Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus (EE-181) Page 5 of 10
At the raising edge of PCLCK video data can be taken To half the frequency each raising edge of PCLCK will change the state of the FlipFlops output "74HC74". Each rising edge of 74HC74s Q & / Q will fetch data to the certain latch.
74HC74 Q0 to Top LVT16374 CK 4.43 MHz 74HC74 Q0 / to Bottom LVT16374 CK ARDY
AOE / Top LVT16374 Q15:0 To DSP D15:0
Each rising edge of 74HC74s Q & / Q will put data to the output
/ AOE remains low until ARDY is sampled high
Each rising edge of / AOE will fetch 32 bits of data into the DSP Figure 5.1
After each read burst one access takes longer. That does not affect the transfer
Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus (EE-181) Page 6 of 10
Figure 5.2
Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External Memory Bus (EE-181) Page 7 of 10
Conclusion:
Video transfers with higher resolutions than CIF it is revered to the Note: "Interfacing the ADSP-BF535 to ADV7185 / 3 NTSC / PAL video decoder over the External Memory Bus". This Note is available soon.
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Figure C1
References:
-www.ovt.com -OV6630 Datasheet -OV7610MD Eva Board -ADSP-BF535 Datasheet -ADSP-BF535 Blackfin DSP Hardware Reference -VisualDSP++ 3.0
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Document History
Version April 17, 2003 January 23, 2003 January 09, 2003 August 06, 2002 Description Ported code example to VisualDSP++ 3.1 Changed according to new Blackfin naming convention. Typos. Schematics, Gerber files and PDFs are attached to the web site Initial release Rev. 0.2
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