High Quality, All-Digital Frequency Modulation Generation with ADSP-21

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High Quality, All-Digital Frequency Modulation Generation with ADSP-21

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AN-543 APPLICATION NOTE
High Quality, All-Digital Frequency Modulation Generation with ADSP-2181 AD9850 Direct Digital Synthesizer
Dean Becker
following describes implementation high quality all-digital generator with audio frequency input signals. signal output broadcast band monaural stereo. modulators have been with since time Major Edwin Armstrong (sometimes known father classic 1936 paper subject. first down paper fundamental concept fixed center frequency that varied constant deviation ratio that independent frequency modulating signal. became very popular because much noise generated nature exhibits characteristics. signal-to-noise ratio signal will found exceed that signal improvement ratio related deviation ratio. familiar with wideband broadcast band superior sound quality noise immunity when compared with broadcast. Analog modulators typically employ oscillator with varactor diode tuned circuit. voltage varactor varied modulating signal, which changes capacitance, therefore changing resonant point oscillator's tuned circuit, which shifts frequency. noted above, constant center frequency deviation ratio essential quality Much work been done embellish basic oscillator circuit provide needed stability. Even though complex circuitry added automatically compensate power supply temperature variations, these circuits still require periodic recalibration deal with component aging.
Recent developments digital signal processing (DSP) devices have made possible create high quality modulation using all-digital circuitry. This modulator does require periodic recalibration, does drift with temperature power supply variations, very easy reproduce since there analog adjustments (other than level input analog modulating signal). heart this circuit Direct Digital Synthesizer (DDS), such AD9850 Complete-DDS (C-DDS) device. AD9850 consists digital phase accumulator, phase/amplitude converter converter. creates linear ramp phase accumulator with frequency that dependent phase accumulator's input value. ramp mapped sampled sinusoidal signal phase-to-amplitude converter. sampled digital signal then converted filtered with reconstruction filter produce analog waveform. functions (except analog reconstruction filter) contained AD9850 chip. sampled signal created sample rate MHz, allowing high frequency output. Prior release AD9850, very fast, inexpensive C-DDS devices exist. more detailed explanation operation specifications C-DDS device, please refer theory operation AD9850 data sheet. HARDWARE IMPLEMENTATION implementation generator consists Analog Devices EZ-KIT Lite 16-bit development board, some decode circuitry, evaluation board DDS-the AD9850-FSPCB shown Figure
LINE AUDIO EZ-KIT LITE
AD9850/FSPCB
AD9850 AD1847
STEREO CODEC
ADSP-2181
ADSP-2181
DECODE LOGIC
8-BIT DATA 125MHz XOSC
OUTPUT
Figure Block Diagram Generator Implementation
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AD9850-FSPCB EVAL BOARD
MODIFIED CONNECTIONS
74AC574 CONNECT DIRECTLY 74AC574 PINS
EZ-KIT LITE BOARD
P2-30 P2-29 P2-28 P2-27 P2-26 P2-25 P2-24 P2-23
INTERFACE BOARD
74AC574 OE's FROM THEN 74LS04
RESET
IOMS
J2-41
74LS04
J2-2
74LS10
J2-39 J2-1
74LS04
74LS10
RESET
J3-37
Figure Schematic Decode Logic Interconnections
EZ-KIT Lite contains Analog Devices ADSP-2181 KS-133 16-bit with program memory data memory RAM. Hardware documentation comes with EZ-KIT Lite development board schematics AD9850 C-DDS AD9850 data sheet. decode logic interconnections shown schematic Figure AD9850-FSPCB evaluation board made interface parallel port Centronics-type connector buffers work with parallel port. simple connect external disabling buffers shown schematic, disconnecting output enables from ground plane wiring them VCC. With buffers disabled, ADSP-2181 EZ-KIT Lite drive AD9850 data lines directly. interface schematic decodes address create W_CLK (write clock) signal address create FQ_UD (frequency update) signal. These control signals used write consecutive frequency bytes into AD9850 then strobe entire 32-bit frequency word into operational register respectively. RESET brought initialize AD9850. Please refer AD9850 data sheet more information loading C-DDS. FIRMWARE IMPLEMENTATION programs described here. first monaural modulator (fm_xmit.dsp) second stereo (fmStereo.dsp). Both programs stand-alone single modules loaded into EZ-KIT Lite serial port using EZ-KIT Lite monitor. They begin with codec variable initialization. only difference here that codec sample rate fm_xmit while 44.1 FmStereo. (This will explained with FmStereo program). This part, initialization code, interrupt vectors codec initialization, copied from sample program that comes with EZ-KIT Lite. following partial listing Figure describes what happens every input sample from codec. First left right input samples divided ensure that they overflow they summed together. Next, deviation value multiplied previous then center frequency value added product. This done 32-bit double precision preserve accuracy C-DDS. Finally, 32-bit frequency word broken into four bytes sent AD9850 C-DDS.
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.const .const
w_clk= fq_ud= 0x0001; 0x0002; 9850 write clock address 9850 frequency update address input_samples: sec_reg; shadow register bank (rx_buf Left data (rx_buf Right data loopback inputs outputs ashift (hi); scale left input pass sr1; setup ashift (hi); scale right input left right together (tx_buf Left data (tx_buf Right data same output both channels 0x004e; peak deviation value 0xa4a8; peak deviation value codec value (MSW only, LSW=0) with LSWs=0 (us); codec deviation mr1; shift right align with next mr2; (ss); MSWs previous product 0x4710; center frequency 0xcb29; center frequency mr1; modulated deviation mr0; modulated deviation +ay0; LSWs first ar=ax1 save result MSWs phase number io(w_clk) sr0; output first byte lshift (hi); move align with D8-D15 io(w_clk) sr1; output second byte DDS, nop; io(w_clk) output third byte DDS, lshift (hi); move align with D8-D15 io(w_clk) sr1; output forth byte DDS, nop; io(w_clk) mr0; output fifth byte DDS, nop; io(fq_ud) sr0; output latch pulse, data irrelevant rti;
Figure Partial Listing Monaural Code
signal received conventional radio (mono) 90.3 MHz. C-DDS programmed frequency 34.7 will have first alias 90.3 MHz. first alias will attenuated sin(x)/x curve from sampling, there plenty signal drive radio. (The alias concept described Figure AD9850 data sheet.) Note that C-DDS cannot have pass filter with cutoff Nyquist output will block first alias. bandpass filter that passes should used filter fundamental other aliases. center frequency C-DDS 34.7 32-bit value 4710CB29H. peak deviation C-DDS offset 00275254H. number used deviation value twice that compensate fact that input divided avoid overflow. These constants arrived from equation: Stereo Implementation monaural case actually very straightforward. Creating signal stereo more involved. First all, there change addition hardware. stereo, three signals created summed together that then FM-modulate DDS. first signal same monaural case, left right channels. second signal pilot tone that level maximum signal. third signal left-minus-right channel, double sideband suppressed, carrier modulated tone. tone generated that rising edge every zero crossing tone. multiplex these signals frequencies that extend (assuming that input signal goes kHz). Clearly, keep sample rate used Fm_xmit, multiplex will alias into itself. codec sample rate 44.1 chosen with inserted samples evenly spaced between. This gives final sample rate 132.3 kHz. "extra" samples created using ADSP-2181 timer some careful coding. This sample rate provides nearly exact 16-bit phase input values Numerically Controlled Oscillators (NCOs) that create tones. following assembly code shown Figure partial listing stereo generator. Initialization redundant code mono generator have been omitted.
Value /(125 MHz/2E32) 34.3597 =125 MHz)
value transmit center frequency deviation could changed stored data memory could treated variables program. They could then changed fly, perhaps from switches serial port desired. When sending AD9850, several wait states used compensate decode logic. least cycle needed between I/Os AD9850 which provided needed instruction nop. first byte phase byte always zero. frequency bytes that follow output order from MSByte LSByte.
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dm(TSCALE) ax0; 251; dm(TPERIOD) ax0; dm(TCOUNT) ax0; dm(nco_19k) ax0; dm(nco_38k) ax0; pre-scalar auto load third interrupt fl1; input overdrive indicator dm(LplusR) ay0; fl1; input overdrive indicator dm(LminusR) remains generate multiplex modulating signal dm(LplusR); baseband signal dm(sin_38k); carrier (ss); with dm(sin_19k); carrier 0x0b85; factor carrier (ss); pilot tone dm(dds_samp) mr0; save result next iteration dm(dds_samp+1) mr1; save result next iteration fl1; input overdrive indicator reset pressing interrupt (IRQE) jump main; loop forever
accumulators. Phase must such that rising edge every zero crossing transition pilot tone.
reset fl1; wait interrupt loop forever main: idle; wait interrupt call dds_out; output previous sample putting this here gives constant update position with jitter dm(sample_flag); flag that during intr tstbit ax0; 1=codec intr, 0=timer intr jump timer_intr; skip codec part input_samples: IMPORTANT!. change number instructions timer, need adjust following TCOUNT accordingly. 188; provide next intr 44.1kHz dm(TCOUNT) ax0; this takes previous instructions interrupt latency into account timer; next intr's timer dm(rx_buf Left data dm(left) ax0; dm(tx_buf ax0; Left loopback} dm(rx_buf Right data dm(right) ax0; dm(tx_buf ax0; Right loopback} first three interrupts group dm(sample_number) ax0; initialize count timer_intr: dm(sample_number); timer interrupts after codec decrement count dm(sample_number) save count interrupt group jump ti1; exec second interrupt group timer; after third interrupt, wait codec generator 0x24c4; phase increment dm(nco_19k); phase update ay0; phase step dm(nco_19k) accumulation back into prep sine routine call sin; sine dm(sin_19k) save later generator 0x4988; dm(nco_38k); ay0; dm(nco_38k) call sin; dm(sin_38k)
following outputs previously calculated sample Execution time 31+(6*W), with W=3; dds_out: create deviation value 0x0027; peak deviation value 0x5254; peak deviation value dm(dds_samp+1); L+R, (L-R)@38K, dm(dds_samp); (uu); deviation mr1; shift right align with next mr2; (su);{ deviation (us);{ deviation mr1; shift right align with next mr2; (ss);{ MSWs previous product} center frequency 0x4710; center frequency 0xcb29; center frequency mr1; modulated deviation mr0; modulated deviation +ay0; LSWs first ar=ax1 save result MSWs output DDS} phase number io(w_clk) sr0; output first byte lshift (hi);{ move align with D8-D15 io(w_clk) sr1; output second byte DDS, nop; io(w_clk) output third byte DDS, lshift (hi); move align with D8-D15 io(w_clk) sr1; output forth byte DDS, nop; io(w_clk) mr0; output fifth byte DDS, nop; io(fq_ud) sr0; output latch pulse, data irrelevant rts;
ti1:
phase increment phase update phase step accumulation back into prep sine routine sine save later
generate signals (left); Left data (right); Right data ay0;
Figure Partial Listing Assembly Code Stereo Generator
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beginning code, ADSP-2181 internal timer have prescaler interrupt clock cycles after last timer interrupt. This places timer interrupts between each codec interrupt. More this later. firmware NCOs internally generated carriers also initialized they have proper phasing previously explained. routine then enters main loop, which executes once interrupt. First loop call output routine. calling output routine same point after interrupt, jitter created output signal. This subroutine similar fm_xmit, operates full 32-bit sample from multiplex generator. fm_xmit routine input samples were only bits. deviation value 0x00275254 equivalent kHz. rest output routine operates fm_xmit. routine then determines interrupt caused codec timer flag (sample_flag) interrupt routine. interrupt from codec, timer initialized starts create next interrupt. This done with count 188, which compensates instructions already executed since interrupt. This gives effect cycles between interrupts. Note that selection this timer value very critical create evenly spaced interleaved interrupts. this point left right input signals retrieved from their locations (and output back codec sanity check) sample number three start interrupt interleave process. routine then falls into housekeeping function timer interrupts. Sample_number decremented two. next pass through this routine (caused first timer interrupt) sample_number will decremented timer will autoload. third pass, sample_number will decremented zero this will cause timer shut off. cycle then repeats with next interrupt coming from codec. code that follows this executed interrupts. first creates carrier incrementing NCO, then creates sine carrier using routine copied from Analog Devices Applications Handbook, Volume This routine uses power series approximate sine phase angle. carrier then generated same fashion with phase increment twice that generator. difference left right signals then created checked overflow. Overflow will light EZ-KIT Lite board indicate condition. light must manually extinguished pressing interrupt button. Next multiplex generated. First left-plus-right signal recalled added product leftminus-right times carrier. This product created modulation about difference signal. then added product signal times constant 0x0b85, which yields reference carrier. multiplex sample then stored output after next interrupt, loop returns idle wait next interrupt. This routine example multirate processing. demonstrates capability ADSP-2181 flexibility AD9850. Even with additional code required stereo multiplex, there still room more. other possibility addition multiplex added into stereo multiplex done many broadcasts. this sample rate must further increased carrier created similar fashion carriers. Dynamic Performance graph spurious performance direct output AD9850 shown Figure First, there shielding breadboard prototype some pickup likely. first point that there appears clock feed through possibly half that frequency. When operating frequency near MHz, AD9850 anticipated have spurs that dBc. Figure shows that this fact case.
34.7
90.3
Figure Typical Output Spurious Performance
Notice that first alias 90.3 about down from fundamental 30.4 MHz. This close what calculated from (sin x)/x curve mentioned earlier. There spurs only down with respect signal 90.3 MHz, they least away could conventionally filtered. also found (not graph) that there were numerous spurs increments from 90.3 that went ±300 These were with respect 90.3 signal. Outside this range first spur
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from 90.3 (which away) energy found down with respect 90.3 signal. point reference, 1982 Reference Data Radio Engineers states page 30-6 that acceptable performance broadcast station with respect out-of-band radiation that between from carrier, emissions should dBc. From should beyond kHz, where transmitter power watts. Considering measurements above, seems that conventional lumped-element filtering would clean AD9850's output signal broadcastquality limits. Another possibility would filters; view high level output available from AD9850, losses could compensated without degrading SNR.
PRINTED U.S.A.
E3362-5-9/98

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