Codec interface driver recommendations with ADSP-21065L EZ-LAB AD1819A
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Interfacing ADSP-21065L SHARC AD1819A 'AC-97' SoundPort Codec
Codec interface driver recommendations with ADSP-21065L EZ-LAB AD1819A well other Analog Devices AC'97-compatible codecs such AD1819, AD1819B, AD1881, AD1881A, AD1882 AD1885
Version 2.4A
John Tomarakos Applications 10/12/99
AD1819
MIC1 MIC2 LINE SYNTH PHONE_IN Selector 16-bit Converter
16-bit Converter
RESET# SYNC
LINK
BIT_CLK
HP_OUT_L L_OUT
Tone Control
Stereo
SDATA_OUT
16-bit Converter
SDATA_IN
MONO_OUT R_OUT HP_OUT_R
Tone Control Stereo
16-bit Converter
PC_BEEP
G=Gain A=Attenuate M=Mute MV=Master Volume
Oscillators
XTALO
XTALI
Introduction
AD1819x (AD1819, AD1819A AD1819B) SoundPort Codec fully compliant AC'97 Analog Front that used processing playback analog signals personal computers. Audio Codec codecs used soundcards motherboard's interface with AC-97 digital controller/accelerator, directly motherboard's 64-bit microprocessor 'native signal processing' support. With extended codec features that have been added baseline AC'97 specification, AD1819x also easily interfaced Analog Devices ADSP-21xx ADSP-21xxx DSP, thus providing additional flexibility using codec embedded low-cost audio application. AD1819x also provide V.34 compatible modem analog front-end supporting modem sample rates filtering. This application note will describe interface low-cost 32-bit SHARC DSP, ADSP-21065L, three daisy chained AD1819As SPORT audio system. programming recommendations also applicable code compatible SHARC processors such ADSP-21061/61L, ADSP-21062/62L ADSP-21060/60L ADSP-21160. Using multiple AD1819s gives system designer more flexibility capture playback 'CD-Quality' audio providing inputs channel output channels SPORT processing multiple audio signals concurrently. additional hardware glue-logic required daisy-chaining, programming multiple AD1819s easily accomplished through simple register command scheme. Single multiple AD1819x driver source code examples provided application note reference purposes. This source code tested using 21065L EZ-LAB Development Platform, which includes AD1819A analog interface. Triple-codec source tested verified using SHARC EZ-LAB with Triple AD1819 MAFE board. Single codec drivers serve basis dual triple AD1819x codec interface requiring very little modification driver enable multi-codec interface, ability broadcast similar commands AD1819s through shared codec register address register data timeslots. latest revision AD1819 AD1819B. references AD1819 AD1819x this document refer AD1819A AD1819B well. programming recommendations this document also applicable AD1881, AD1881A, AD1882 AD1885 (AC-97 compliant codecs).
What AD1819x Offers Above Baseline AC-97 1.03 Specification
AD1819 exceeds AC'97 Version 1.03 Specifications offers additional features that useful interfacing. Some these include: Slot-16 Serial Mode Serial Port Multichannel Mode (TDM) Compatibility. This mode ensures that serial port time-slots bits, allowing much easier interface 16-bit/32-bit DSPs that support (time division multiplexed) interface. Slot-16 mode useful since always 16-bits equal length 16-bit slots eases serial port 'autobuffering' data, 'DMA chaining', along with SPORT's Multichannel Mode operation. Variable Sampling Rate Support Both Stereo Sigma-Delta ADCs DACs Variable sample rate allows 'record' 'play back' audio signals sample rate from 7KHz 48Khz 1Hhz increments with sample rate generator registers. AD1819A record transmit samples rate play back received samples another rate. left channels also programmed different rates right channels. addition resolution AD1819A also method running irrational modem rates 10/7 bits. with these modem sample rates AD1819A modem filters left channel. Please refer EE-Note titled "How AD1819A Variable Sample Rate Support" additional information (located Analog's site: www.analog.com). High Quality AC-97 Output greater than AC'97 1.03 defines least signal quality. AD1819 exceeds this specification, providing greater than dynamic range provide near 'CD-Quality' sound with Multibit Sigma Delta converter technology. Simple, Glueless Interface Daisy-Chaining Three AD1819s Three AD1819s easily interfaced Analog Devices provide input channels output channels SPORT. From hardware standpoint, additional glue circuitry required connection multiple codecs. Each codec pins that used daisy-chaining AD1819s: CS0, CS1, CHAIN_IN CHAIN_CLK. From software point view, communicate AD1819s once, read/write codec registers desired codec time with Mask Bits AD1819's Serial Configuration Register. Analog Devices only generation AC-97 1.03 vendor implement simple multi-codec scheme. Phat Stereo Enhancement Provides wider three dimensional sound stereo output field giving impression spaciousness. phase expansion capability allows user simulate effect sound source coming from another direction other than left right stereo speaker sources.
21065L EZ-LAB AD1819A Audio Development System
AD1819A
SPORT1
ADSP21065L
Left/Right Speakers
Stereo Line Stereo
AD1819x ADSP-2106x SHARC Serial Interface Overview
AD1819x (AD1819, AD1819A, AD1819B) Serial Port functionality very similar other Analog Devices SoundPort Codecs like AD1843 AD1847. It's interface communicates with AC'97 controller, ASIC time-division multiplexed (TDM) mode, where codec register command/status information DAC/ADC data received transmitted different timeslots frame. AD1819 communicates with AC'97 controller digital serial link, which referred "AC-link." AD1819x incorporates digital serial interface that links AC'97 controller. pins assigned AD1819x are: SDATA_IN, SDATA_OUT, SYNC, BIT_CLK RESET#. digital audio data command/status information communicated over this point point serial interconnection DSP. breakout signals connecting shown Figure detailed description AC-link serial protocol between codec, reader refer next section.
Digital Controller
RFSx SYNC
Codec
BIT_CLK SDATA_IN SDATA_OUT RESET#
ADSP-2106x
SPORT Transfers Internal
RCLKx TCLKx FLG2 (Flag2
AD1819
Figure Example AD1819x Interconnection ADSP-2106x SHARC DSP's SPORT(0 AC-97 component specification defines digital serial connection known AC-Link, which bi-directional, fixed rate, serial digital stream. AC'97-compatible codec handles multiple input output audio streams, well command register accesses employing time-division-multiplexed (TDM) scheme. baseline AC-link architecture divides each audio frame into outgoing incoming data streams, each with 20-bit sample resolution. AD1819 also includes additional mode operation, considered Enhanced AC-link Protocol Extension, also referred SLOT-16 Mode. This extension very similar such that also also bi-directional, fixed rate, serial digital stream. This Modified AClink divides each audio frame into outgoing incoming data streams, each 16-bits slot. This allows software overhead transmit receive data thus enables more simplified interface ADSP-21xx ADSP-21xxx DSP. achieve this, AD1819's SLOT-16 Mode Operation will place DAC/ADC command/status Timeslots 16-bits allow proper 16-bit alignment DSP's serial port. AC-97 protocol could also implemented with 18-bit 20-bit DAC/ADC resolution with larger data word processors, given headroom that AC-link architecture provides. This application note will only assume 16-bit data placing AD1819x SLOT-16 mode. this time, there performance benefit using 18-bit 20-bit words, since larger 20-bit timeslots will necessarily improve dynamic range SNR. Also, phase always 16-bits, other larger word slots would skewed relative timeslot alignment. This would then require programmer shift/extract/deposit instructions data coming after 16-bit slot that proper memory register alignment occurs timeslot data. still possible write driver that assumes 20-bit slots, although programmer would have additional instructions ensure that data packed sent properly. 16-bit cannot easily handle additional headroom 20-bit words, while 32-bit would have overhead packing unpacking 20-bit data after initial 16-bit timeslot. Again, since there benefit using larger data word timeslot sizes, AD1819 while SLOT-16 mode recommended interfacing serial port found ADI's ADSP-21xx ADSP-2106x DSPs.
AD1819x (AD1819/A/B) "AC-Link" Serial Port Clocks Frame Sync Rates
keep clock jitter minimum, AD1819x derives clock internally from externally attached 24.576 crystal required AC-97 specification), drives buffered divided down (1/2) clock ADSP-2106x over AC-link under signal name BIT_CLK. crystal frequency different, would longer AC-97 compliant since also affects actual value selected sample rate. Meeting AC-97 compliance necessary embedded designs (for tips using different crystal frequency, refer EE-Note Analog Devices Site: www.analog.com). Clock jitter AD1819x DACs ADCs fundamental impediment high quality output, internally generated clock provided AD1819x with clean clock that independent physical proximity ADSP-2106x processor. BIT_CLK, fixed 12.288 MHz, provides necessary clocking granularity support 16-bit outgoing incoming time slots (12, 20bit outgoing incoming time slots normal AC-97 mode). AC-link serial data transitioned each rising edge BIT_CLK. receiver AC-link data, AD1819x outgoing data ADSP-2106x incoming data, samples each serial falling edges BIT_CLK. AD1819x drives serial clock 12.288 MHz, which ADSP-2106x then qualifies with synchronization signal construct audio frames. beginning audio sample packets, "Audio Frames", transferred over AC-Link synchronized rising edge SYNC signal. SYNC used serial interface frame synchronization must generated ADSP2106x AC-97 Controller. Synchronization AC-link data transactions signaled ADSP-2106x RFSx signal. SYNC, fixed kHz, derived dividing down serial clock (BIT_CLK). ADSP-2106x SHARC takes BIT_CLK RCLKx/TCLKx SHARC equivalent terms) input generates SYNC (RFSx) dividing BIT_CLK 256. This yields 48kHz SYNC signal whose period defines audio frame, which required meet AC-97 audio frame rate requirement. SYNC (RFSx) pulse driven ADSP-2106x processor programming RFSDIV register DSP. generate frame sync with externally generated 12.288 SCLK, must value (0x00FF) RFSDIV control register.
SDATA_IN SDATA_OUT pins handle serial data input output AD1819x. Both AD1819x's SDATA_IN SDATA_OUT pins transmit receive data different timeslots addition Phase) frame normal AC-97 mode, different timeslots Data slots) SLOT-16 mode. AD1819x transmits data every rising edge BIT_CLK (RCLKx/TCLKx) samples received data falling edge BIT_CLK (RCLKx/TCLKx).
When audio frame rate equivalent selected sample rate, then Valid Data Slot bits Phase timeslot well request bits AD1819's Serial Configuration Register used control sample data flow between codec DSP. When frame rate equivalent converter sample rate, valid request bits ignored since they will always
AD1819x/ADSP2106x "AC-Link" Digital Serial Interface Protocol
AC-link protocol described AC'97 specification provides special 16-bit time slot (Slot often called 'TAG Phase') wherein each conveys valid corresponding time slot within current audio frame. given position slot indicates that corresponding time slot within current audio frame been assigned data stream, contains valid data. slot "tagged" invalid, responsibility source data, (AD1819x input stream, ADSP-2106x output stream), stuff positions with during that slot's active time. source code example Appendix ADSP-2106x processor ensures than invalid slots stuffed with 0's. SYNC remain high total duration BIT_CLKs beginning each audio frame, although interfacing, usually pulses frame sync approximately BIT_CLK, which also acceptable AD1819x. first timeslot portion audio frame defined "Tag Phase". remainder audio frame defined "Data Phase."
Slot
SYNC (RFSx) OUTGOING STREAMS INCOMING STREAMS
DATA
LEFT LEFT
RIGHT RIGHT
OPT. RSRVD OPT. OPT.
RSRVD RSRVD
RSRVD RSRVD
RSRVD RSRVD
RSRVD RSRVD
RSRVD RSRVD
RSRVD RSRVD
STATUS STATUS DATA
Phase
Data Phase
Figure Standard AC'97 Version 1.03 Bi-directional Audio Frame
Slot
SYNC (RFSx)
OUTGOING STREAMS INCOMING STREAMS
DATA
LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
STATUS STATUS DATA LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
MASTER AD1819
SLAVE1 AD1819
SLAVE2 AD1819
Data Phase Phase
Figure Modified AD1819x 'AC-97' Bi-directional Audio Frame Configured SLOT-16 Mode
ADSP2106x AD1819x Audio Output Frame (DTx SDATA_OUT)
audio output frame data streams correspond multiplexed bundles digital output data targeting AD1819x inputs, control registers. Each audio output frame support 16-bit outgoing data time slots default, actually 20-bit outgoing timeslots after 16-bit slot must AD1819x into Slot-16 mode SPORT compatibility). Slot special reserved time slot containing bits, which used AC-link protocol infrastructure. Within slot first global (SDATA_OUT slot which flags validity entire audio frame. "Valid Frame" this indicates that current audio frame contains least slot time valid data. next positions sampled AD1819 indicate which corresponding time slots contain valid data. Note that Slot-16 mode, positions always assumed zero. this data streams differing sample rates transmitted across AC-link fixed audio frame rate. timing diagram Figure illustrates time slot based AClink protocol Slot-16 Mode. Serial timings Figure assume either SHARC's SPORT0 SPORT1 pins. SPORT0 RFS0 frame sync, TCLK0 serial clock, DT0/DT0A data transmit pin. These timings also apply SPORT1's RFS1 DT1/DT1A pins, while serial clock would correspond TCLK1.
Phase 16-bits
Data Phase 20.8uS KHz)
SYNC (RFSx) BIT_CLK(TCLKx) SDATA_OUT (DTx)
12.288
81.4
slot(1) slot(2)
slt(12)
previous Audio Frame
Valid Frame
Time Slot "Valid" Bits ("1" time slot contains valid data)
Slot
Slot
Slot
Slot
Figure AD1819x Audio Output Frame SLOT-16 Mode ADSP-2106x AD1819x Data Path
**Note: timing figure differs from standard AC-97 timing slots, bits length data phase portion audio frame. timeslots bits length (SLOT16 Mode) ADSP-2106x during initial enabling SPORT that proper data alignment slots occur. Also, frame sync generated duration Phase, described AC-97 spec AD1819 data sheet. generates frame sync approximately serial clock cycle. However this does affect codec operation, since codec samples frame sync only first cycle prior transmission Phase timeslot. Setup hold times AD1819 relaxed enough meet SHARC RFSx external generation timings listed ADSP-2106x data sheet.
audio output frame, shown Figure begins with high transition SYNC. SYNC synchronous rising edge BIT_CLK. immediately following falling edge BIT_CLK, AD1819x samples assertion SYNC. This falling edge marks time when both sides AC-link aware start audio frame. next rising BIT_CLK, ADSP-2106x transitions SDATA_OUT into first position slot (Valid Frame bit). Each position presented AC-link rising edge BIT_CLK, subsequently sampled AD1819x following falling edge BIT_CLK. This sequence ensures that data transitions subsequent sample points both incoming outgoing data streams time aligned.
AD1819 samples SYNC assertion here
SYNC
ADSP-2106x samples first SDATA_OUT frame here
RFSx
BIT_CLK SDATA_OUT
Valid Frame
TCLKx
slot(1) slot(2)
previous Audio Frame
Figure Start Audio Output Frame
SDATA_OUT's composite stream justified (MSB first) with non-valid slots' positions stuffed with ADSP-2106x. software initialize transmit buffer 0x0000s SPORT ISR. (Note that this done SPORT1 transmit received interrupt service routines shown Appendix event that there less than valid bits within assigned valid time slot, ADSP-2106x should always stuff trailing non-valid positions 16-bit slot with 0's. When mono audio sample streams output from ADSP-2106x, necessary that BOTH left right sample stream time slots filled with same data.
AD1819x/ADSP2106x Audio Input Frame (SDATA_IN DRx)
audio input frame data streams correspond multiplexed bundles digital input data targeting ADSP-2106x. case audio output frame, each AD1819x audio input frame consists 16-bit time slots after programs codec SLOT-16 Mode. Slot special reserved time slot containing bits which used AC-link protocol infrastructure. timing diagram Figure illustrates time slot based AC-link protocol Slot-16 Mode, Phase's positions zero. Serial timings Figure assume either SHARC's SPORT0 SPORT1 pins. SPORT0 RFS0 frame sync, RCLK0 serial clock DR0/DR0A data receive pin. These timings also apply SPORT1's RFS1 DR1/DR1A pins, while serial clock would correspond RCLK1.
Phase 16-bits Data Phase
20.8uS KHz)
SYNC (RFSx) BIT_CLK (RCLKx) SDATA_IN (DRx)
12.288
81.4
slot(1)
slot(2)
slot(12)
previous Audio Frame
Time Slot "Valid" Bits Codec ("1" time slot contains valid data) Ready
Slot
Slot
Slot
Slot
Figure Modified AC-link Audio Input Frame AD1819x ADSP-2106x Data Path
**Note: timing figure differs from standard AC-97 timing slots, bits length data phase portion audio frame. timeslots bits length (SLOT16 Mode) ADSP-2106x during initial enabling SPORT that proper data alignment slots occur. Also, frame sync generated duration Phase, described AC-97 spec AD1819 data sheet. generates frame sync approximately serial clock cycle. However this does affect codec operation, since codec samples frame sync only first cycle prior transmission Phase timeslot. Setup hold times AD1819 relaxed enough meet SHARC RFSx external generation timings listed ADSP-2106x data sheet.
audio input frame, shown Figure (data samples sent from AD1819x) begins with high transition SYNC/RFSx. SYNC synchronous rising edge BIT_CLK/RCLKx. immediately following falling edge BIT_CLK, AD1819x samples assertion SYNC. This falling edge marks time when both sides serial link aware start audio frame. next rising BIT_CLK, AD1819x transitions SDATA_IN into first position slot ("Codec Ready" bit). Each position presented AC-link rising edge BIT_CLK, subsequently sampled ADSP-2106x following falling edge BIT_CLK. This sequence ensures that data transitions, subsequent sample points both incoming outgoing data streams time-aligned. SDATA_IN's composite stream justified (MSB first) with non-valid positions (for assigned and/or unassigned time slots) stuffed with AD1819x. SDATA_IN data sampled falling edges BIT_CLK
AD1819 samples SYNC assertion here ADSP-2106x samples first SDATA_IN frame here
SYNC BIT_CLK SDATA_IN
Codec Ready
RFSx RCLKx
slot(1) slot(2)
previous Audio Frame
Figure Start Audio Input Frame
Codec Ready (Most Significant Slot
Within slot first global (SDATA_IN slot which flags whether AD1819x "Codec Ready" state not. "Codec Ready" this indicates that AD1819x ready normal operation. This condition normal following deassertion power reset example, while AD1819's voltage references settle. When "Codec Ready" indicates that serial-link, AD1819 control registers, least subsystems described Powerdown Control/Status Register operational. Prior attempts putting codec into operation ADSP-2106x should poll first audio input frame (SDATA_IN slot indication that AD1819x gone "Codec Ready". Below example ADSP-2106x Assembly Language Instructions accomplish 'Poll Codec Ready' task:
Wait_Codec_Ready: DM(rx_buf 0x8000; JUMP Wait_Codec_Ready; Wait CODEC Ready State status from AD1819 phase slot0*/ mask codec ready phase test codec ready status flag flag continue wait
Once AD1819x sampled "Codec Ready" then next positions Slot-16) sampled ADSP-2106x indicate which corresponding time slots assigned input data streams, that they contain valid data. There several sub-functions within AD1819x that independently busy/ready. global "Codec Ready" indicates that least these sub-functions available. responsibility probe more deeply into AD1819x register file determine which AD1819x subsections actually ready. addition polling "Codec Ready" indicator bit, Power-Down Control/Status Register useful monitoring subsystem readiness. programmer choose poll Power-Down Control/Status Register wait Reference Voltage, Analog Mixer, Section Stabilization after polling Codec Ready Bit. This step would ensure that will modify codec registers until conversion resources analog circuitry have stabilized. This step recommended AC-97 1.03 specification, although source code example Appendix does perform this step, since found successful programming AD1819x achieved after simply polling "Codec Ready" indicator bit.
Configuring ADSP-21065L Serial Port Interface
When interfacing AD1819A codec ADSP-21065L SHARC processor, interconnection between devices through either SPORT0 SPORT1. application code section this document, SPORT1 used example drivers since 21065L EZ-LAB makes SPORT1 codec interface. Both codec serial port shift data first, AD1819A's BIT_CLK frequency 12.288 less than SCLK maximum 2106x. Therefore, DSP's CLKOUT frequency must greater than 12.288 Mhz.
Figure ADSP-21065L SPORTs
RX0a RX0b RFS0 RCK0 RX1a RX1b RFS1 RCK1
ADSP 21065
TX0a TX0b TFS0 TCK0 TX1a TX1b TFS1 TCK1
Table ADSP-21065L Serial Port Pins
Function
Transmit data Transmit clock Transmit frame sync/ word select Receive data Receive cock Receive frame sync DR0A
SPORT0
DT0A DT0B
SPORT1
DT1A
DT1B
TCLK0 TFS0 DR0B
TCLK1 TFS1 DR1A DR1B
RCLK0 RFS0
RCLK1 RFS1
ADSP-21065L Serial Ports have transmit receive data pins both transmit side receive side. Transmit Channels DT0A, DT1A Transmit Channels DT0B, DT1B Receive Channels DR0A, DR1A Receive Channels DR0B, DR1B
NOTE: ADSP-21065L SPORT channel pins functional multichannel mode. Both transmitter receiver have their serial clocks. TFSx frame sync becomes output 'transmit data valid' used, while RFSx used control start multichannel frame both data transmission reception.
RFS1
SYNC BIT_CLK SDATA_IN SDATA_OUT
ADSP-21062
SPORT Transfers Internal
RCLK1 TCLK1 FLGn (Flag_n
AD1819
RESET#
Figure Example AD1819A/ADSP-21062 SHARC Serial Port Interconnections (assuming I/0)
IMPORTANT SERIAL INTERCONNECTION NOTES: 21065L's TFSx line output multichannel mode (TDV Transmit Data Valid). should left unconnected tied with RFSx together AD1819x Frame Sync. RFSx used signal start frames both reception transmission data. Connecting TFSx(TDVx) could cause contention with RFSx (SYNC) will most likely lock SPORT possibly damage RFSx over time!!!
10-K 20-K pull-down resister recommended ADSP-2106x's (DT0 DT0A DT1A) line. lines ADI's SHARC DSPs have internal pull-up, which cause AD1819A enter test mode, referred AC'97 spec. `ATE Factory Test Mode'. pull-down required ensure proper codec serial operation. Since BIT_CLK master serial clock, DSP's RCLKx TCLKx signals external generation, since they slave (input) signals. synchronize shifting data channels, RCLKx TCLKx pins tied together BIT_CLK. Volt Interfaces, AD1819x output signals connected inputs must level-converted down from Volts Volts (See Next Section 3.1).
ADSP-21065L
Level Shifting Considerations
ADSP-21065L derivative SHARC family that targeted low-cost/high-performance consumer oriented applications. Since Volt part, Volt AC-link signals that AD1819A provides will damage driver pins 21065L serial port. Level-shifting input signals recommended. SPORT output signals that inputs AD1819 need level shifted since AD1819A will recognize volts valid high level. Also, other SHARC processors like ADSP-21060L, ADSP-21062L ADSP-21061L should level shift input serial port signals. Figure below shows interface between AD1819A ADSP-21065L. ADI's code compatible AC-97 2.01 parts, AD1881/AD1881A/AD1882/AD1885, include digital I/O, removing need level shifting.
Figure 21065L EZ-LAB DSP/Codec Interface
ADSP-21065L
74LV125
DR0A RCLK0 TCLK0 DT0A RFS0
AD1819A
3.3V-to-5V Level Translator
SDATA_IN BIT_CLK
SDATA_OUT SYNC
Note: Second Generation pin-for-pin compatible AC-97 codecs, AD188x series, have Volt capability digital portion chip, thus level shifting required
order facilitate serial communications with AD1819A, SPORT1 connections configured shown Table Figure
Table
ADSP-21065L Pin: RCLK1, TCLK1 RFS1 TFS1 unconnected DR1A DT1A AD1819A Pin: BIT_CLK SYNC -SDATA_IN STATA_OUT Driven codec -codec
Figure Block Diagram ADSP-2106x Serial Interface AD1819 Codecs
SPORT0
/RESET SDATA_OUT SDATA_IN SYNC BIT_CLK CHAIN_IN CLOCK_OUT XTAL_OUT XTAL_IN DVDD FLG2 TFS0 RFS0 RCLK0 TCLK0
AD1819 MASTER
Timeslots
ADSP-2106x
AC97 CONTROLLER
24.576MHz 22pF 22pF
AD1819 SLAVE
XTAL_IN
/RESET SDATA_OUT SDATA_IN SYNC BIT_CLK CHAIN_IN CHAIN_CLK XTAL_OUT
Timeslots
AD1819 SLAVE
Timeslots XTAL_IN
/RESET SDATA_OUT SDATA_IN SYNC BIT_CLK CHAIN_IN CHAIN_CLK XTAL_OUT DVDD
Slot
SYNC (RFS0)
OUTGOING STREAMS INCOMING STREAMS
DATA
LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
STATUS
STATUS DATA LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
MASTER AD1819
SLAVE1 AD1819
SLAVE2 AD1819
Data Phase Phase
Figure Timeslot Allocation Multiple AD1819 Bi-directional Audio Frame
SPORT Channels Interrupt Vectors
There dedicated channels both SPORT0 SPORT1 ADSP-21065L. addresses registers shown table below each corresponding channel SPORT data buffer. multichannel mode, only channels active, because channel pins disabled Multichannel Mode.
Table SPORT channels data buffers
Data Buffer Address Rx0A Rx0B Rx1A Rx1B Tx0A Tx0B Tx1A Tx1B 0x0060 0x0064 0x0030 0x0034 0x0068 0x006C 0x0038 0x003C 0x0070 0x0074 0x0050 0x0054 0x0078 0x005C 0x0058 0x005C Description Serial port receive; data Serial port receive; data Serial port receive; data Serial port receive; data Serial port transmit; data Serial port transmit; data Serial port transmit; data Serial port transmit;
Each serial port transmit interrupt receive interrupt (shown Table below). With serial port disabled, interrupts occur word word basis, when word transmitted received. Table also shows interrupt priority, because their relative location another interrupt vector table. lower interrupt vector address, higher priority interrupt. Note that channels transmit receive side each SPORT share same interrupt location. Thus, data both buffers processed same time, conditional basis depending state buffer status bits SPORT control registers.
Table ADSP-21065L Serial Port Interrupts
Interrupt Function
SPR0I SPR1I SPT0I SPT1I EP0I EP1II
Priority
SPORT0 receive channels SPORT1 receive channels SPORT0 transmit channels SPORT1 transmit channels Ext. port buffer channel Ext. port buffer channel
Highest
Lowest
Interrupt names defined def21065.h include file supplied with ADSP-21000 Family Visual Development Software.
Serial Port Related Registers
This section briefly highlights list available SPORT-related registers that will need programmed when configuring SPORTs Multichannel Mode. program these registers, write appropriate address memory using symbolic macro definitions supplied def21065l.h file (included with Visual tools /INCLUDE/ directory). External devices such another 21065L, host processor, write read SPORT control registers serial port operation enable particular SPORT. These registers shown table below. SPORT registers covered section 4.8. will next section, many available registers shown below need programmed Multichannel Mode. These registers highlighted bold text.
Table Serial Port Registers
SPORT0 Register STCTL0 SRCTL0 TDIV0 RDIV0 MTCS0 MRCS0 MTCCS0 MRCCS0 KEYWD0 IMASK0 0xe0 0xe1 0xe4 0xe6 0xe8 0xe9 0xea 0xeb 0xec 0xed Address Description SPORT0 transmit control register SPORT0 receive control register SPORT0 transmit divisor SPORT0 receive divisor SPORT0 multichannel transmit select SPORT0 multichannel receive select SPORT0 multichannel transmit compand select SPORT0 multichannel receive compand select SPORT0 receive comparison register SPORT0 receive comparison mask register
SPORT1
STCTL1 SRCTL1 TDIV1 RDIV1 MTCS1 MRCS1 MTCCS1 MRCCS1 KEYWD1 IMASK1
0xf0 0xf1 0xf4 0xf6 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd
SPORT1 transmit control register SPORT1 receive control register SPORT1 transmit divisor SPORT1 receive divisor SPORT1 multichannel transmit select SPORT1 multichannel receive select SPORT1 multichannel transmit compand select SPORT1 multichannel receive compand select SPORT1 receive comparison register SPORT1 receive comparison mask register
Multichannel Mode, available SPORT data buffers that active channel registers (which highlighted below). these registers that actually used transfer data between AD1819A controller ADSP21065L. controller used transfer data from internal memory without intervention from core. SPORT Data Buffers TX0_A RX0_A TX1_A RX1_A TX0_B RX0_B TX1_B RX1_B 0xe2 0xe3 0xf2 0xf3 0xee 0xef 0xfe 0xff SPORT0 transmit data buffer, channel data SPORT0 receive data buffer, channel data SPORT1 transmit data buffer, channel data SPORT1 receive data buffer, channel data SPORT0 transmit data buffer, channel data SPORT0 receive data buffer, channel data SPORT1 transmit data buffer, channel data SPORT1 receive data buffer, channel
Example SPORT1 Register Configuration Audio Processing
configuration SPORT1, with ADSP-21065L EZ-LAB fixed sample rate, follows: 16-bit serial word length Enable SPORT1 transmit receive functionality Enable chaining functionality SPORT1 transmit receive External Serial Clock (RCLK1) codec provides serial clock ADSP-21065L. Transmit Receive chaining enabled. program declares buffers tx_buf[5] rx_buf[5] transfers SPORT0 transmit receive serial data. Both buffers reserve locations memory reflect AD1819A time slot allocation single codec. chaining almost certainly required, interrupt service overhead will chew much DSP's bandwidth. Multichannel Frame Delay i.e., frame sync occurs SCLK cycle before word. frames marked pulse driven SYNC serial clock period before frame begins.
Program_SPORT1_Registers: program sport0 receive control register 0x0F0C40F0; chans, rfs, rclk, slen sden&schen enabled*/ dm(SRCTL1) sport receive control register sport1 transmit control register 0x001C00F0; mfd, data depend, slen sden schen enabled dm(STCTL1) sport transmit control register
ADSP-21065L provides internally generated frame sync (RFS1). must frame rate since AC97 specified frame rate AD1819A kHz. Since AD1819A serial clock 12.288 MHz, divide factor will produce internally generated frame sync. sport1 receive frame sync divide register 0x00FF0000; SCKfrq(12.288M)/RFSfrq(48.0K)-1 0x00FF dm(RDIV1)
companding. sport1 transmit receive multichannel companding enable registers 0x00000000; companding dm(MRCCS1) companding receive dm(MTCCS1) companding transmit
Multichannel Mode Length multichannel words enabled. This allows AD1819A audio frame ADSP-21065L multichannel frame. sport1 receive transmit multichannel word enable registers 0x0000001F; enable transmit receive channels dm(MRCS1) dm(MTCS1)
Registers ADSP-21065L Serial Ports
following register descriptions provided defs21065l.h file programming registers associated with processor's controller. will look these registers programmed chaining, which registers reinitialized automatically whenever serial port interrupt request generated next section. Table SPORT Registers Register Description Register Channel Index Register IIR0A Channel Modify Register IMR0A Channel Count Register CR0A Channel Chain Pointer Register CPR0A Channel General Purpose Register GPR0A Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register Channel Index Register Channel Modify Register Channel Count Register Channel Chain Pointer Register Channel General Purpose Register IIR0B IMR0B CR0B CPR0B GPR0B IIR1A IMR1A CR1A CPR1A GPR1A IIR1B IMR1B CR1B CPR1B GPR1B IIT0A IMT0A CT0A CPT0A GPT0A IIT0B IMT0B CT0B CPT0B GPT0B IIT1A IMT1A CT1A CPT1A GPT1A IIT1B IMT1B CT1B CPT1B GPT1B
SPORT0 Receive Channel
Address 0x60 0x61 0x62 0x63 0x64 0x30 0x31 0x32 0x33 0x34 0x68 0x69 0x6A 0x6B 0x6C 0x38 0x39 0x3A 0x3B 0x3C 0x70 0x71 0x72 0x73 0x74 0x50 0x51 0x52 0x53 0x54 0x78 0x79 0x7A 0x7B 0x7C 0x58 0x59 0x5A 0x5B 0x5C
SPORT0 Receive Channel
SPORT1 Receive Channel
SPORT1 Receive Channel
SPORT0 Transmit Channel
SPORT0 Transmit Channel
SPORT1 Transmit Channel
SPORT1 Transmit Channel
Setting ADSP-21065L Controller Chained SPORT Transfers
efficiently transmit receive digital audio data to/from AD1819A, recommended method serial port Chaining transfer data between serial core. There obvious benefits doing this. First all, transfers allow efficient transfer data between serial port circuitry internal memory with zero-overhead, i.e. there processor intervention SHARC core manually transfer data. Secondly, there one-to-one correspondence location word transmit receive SPORT buffers with actual audio frame timeslot serial bus. Thirdly, entire block audio frame) data transmitted received before generating single interrupt. 'chained-DMA' method serial port processing more efficient SHARC process data, versus interrupt driven transfers, which occur more frequently, every serial word transmitted received. Using chained transfers allows ADSP-21065L controller autoinitialize itself between multiple transfers. When entire contents current SPORT buffers rx_buf tx_buf have been received transmitted, ADSP-21065L automatically another serial port transfer that continuously repeated every interrupt. further information chaining, reader refer section 6.3.4 ADSP-2106x User's Manual, section chapter ADSP21065L User's Manual. chain pointer register (CPxxx) used point next buffer chaining parameters stored memory. SPORT transfers AD1819A initiated writing buffer's memory address CPR1A register SPORT1 receive CPT1A register SPORT1 transmit. transmit receive SCHEN_A SCHEN_B bits SPORTx Control registers enable chaining. auto-initialize repetitive DMA-chained transfers, programmer needs buffer memory called Transfer Control Block (TCB) that will used initialize further continue chained process. Transfer Control Blocks locations Internal Memory that store register information specified order. example, Figure below demonstrates defined TCBs internal memory SPORT1 Channel Chain Pointer Register (CPR1A CPT1A) stores location next parameters automatically downloaded controller completion transfer, which this case points back itself repeat same
Figure TCBs Chained Transfers SPORT1 Channel Receive Transmit rcv1a_tcb[8]
DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb DM(rcv1a_tcb
ECEPx (not used with SPORTs) EMEPx (not used with SPORTs) EIEPx (not used with SPORTs)
xmit1a_tcb[8]
DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb DM(xmit1a_tcb GPT1A CPT1A CT1A IMT1A IIT1A
GPR1 CPR1 CR1A IMR1A IIR1A
TCBs both transmit receive buffers defined variable declaration section assembly code. AD1819A initialization code shown appendix TCBs SPORT1 channel defined follows: .var rcv_tcb[8] .var xmit_tcb[8] receive transmit
Note that count modify values initialized buffer declaration that they resident after reset boot. However, runtime, further modification buffer required initiate autobuffer process. setup initiate chain SPORT operations runtime, 21065L program follow this sequence: SPORT transmit Receive TCBs (transfer control blocks). TCBs defined data variable declaration section your code. Before setting values kicking process, make sure SPORT registers programmed along with appropriate chaining bits required step Write SPORT0 transmit receive control registers (STCTL0 STCRL0), setting SDEN_A enable SCHEN_A chaining enable Write internal memory index address register (IIxxx) first CPxxx register start chain. order should follows: write starting address SPORT buffer TCBs internal index register IIxxx location (TCB buffer base address need starting address defined buffer runtime copy into this location TCB. write internal modify register value IMxxx (TCB buffer base address Note that this step skipped location buffer initialized variable declaration section your code. write count register Cxxx value (TCB buffer base address Also note that this step skipped location buffer initialized variable declaration section your code. IIxxx value buffer that previously stored step (a), with that internal address value, write modified value chain pointer location (TCB buffer base offset write same `PCI-bit-set' internal address value from step manually into that channel's chain pointer register (CPxxx). this moment chaining begins.
interrupt request occurs whenever Count Register decrements zero. SPORT chaining occurs independently transmit receive channels serial port. After SPORT1 receive buffer (rx_buf) filled with data, SPORT1 receive interrupt generated, data placed receive buffer available processing. controller will autoinitialize itself with parameters buffer begin refill receive buffer with data next audio frame. processed data then placed SPORT transmit buffer, where will then DMA'ed from memory SPORT DT1A pin. After entire buffer transmitted from internal memory SPORT circuitry, controller will autoinitialize itself with stored parameters perform another transfer data that will placed same transmit buffer (tx_buf). Below example assembly instructions used receive transmit buffers Transfer Control Blocks SPORT1 Channel which shown 21065L EZ-LAB example shown appendix These values reloaded from internal memory controller after entire SPORT buffer been received transmitted.
.segment dm_codec;
define buffer sizes match number active channels .var rx_buf[5]; receive buffer transmit buffer .var tx_buf[5] ENABLE_VFbit_SLOT1_SLOT2, SERIAL_CONFIGURATION, 0xFF80, 0x0000, 0x0000; Chaining Transfer Control Blocks .var rcv_tcb[8] .var xmit_tcb[8] .endseg;
valid bits slot serial configuration register address slot-16 mode SPORT compatibility stuff other slots with zeros
receive transmit
.segment pm_code; /*-*/ Controller Programming SPORT1 Setup SPORT1 Chaining: /*-*/ Program_DMA_Controller: 0x0001FFFF; register mask sport1 control chain pointer register tx_buf; dm(xmit_tcb internal address used chaining dm(xmit_tcb internal memory modifier dm(xmit_tcb internal memory buffer count xmit_tcb chain intn pointer containing tx_buf address mask pointer BSET dm(xmit_tcb write transmit block chain pointer buffer dm(CPT1A) transmit block chain pointer, initiate transfers Note: Tshift0 will automatically loaded with first values buffer. buffer pointer IIT1A will increment twice modify modify value specified IMT1A
sport1 control chain pointer register rx_buf; dm(rcv_tcb internal address used chaining dm(rcv_tcb internal memory modifier dm(rcv_tcb internal memory buffer count rcv_tcb chain intn pointer containing rx_buf address mask pointer BSET dm(rcv_tcb write receive block chain pointer buffer dm(CPR1A) receive block chain pointer, initiate transfers .endseg;
AD1819A Serial Port Time Slot Assignments, Buffer Relationships
SPORT Multichannel Mode Time Slot AD1819A communication SLOT16 Mode follows: Timeslot SDATA_OUT (DT1A) Phase (ADSP-2106x) Command Address Port (Control Word Input) Command Data Port (Control Register Data Input) Master Playback Left Channel Master Playback Right Channel Slave Playback Left Channel Slave Playback Right Channel Slave Playback Left Channel Slave Playback Right Channel Reserved Future should always stuff with Reserved Future should always stuff with Reserved Future should always stuff with Reserved Future should always stuff with Reserved Slot, SLOT16 Mode extension Reserved Slot, SLOT16 Mode extension Reserved Slot, SLOT16 Mode extension SDATA_IN (DR1A) Phase (Codec) Status Address Port (Status Word Output) Status Data Port (Control Register Read Data Output) Master Capture (Record) Left Channel Master Capture Right Channel Slave Capture Left Channel Slave Capture Right Channel Slave Capture Left Channel Slave Capture Right Channel Reserved Future AD1819 fills with Reserved Future AD1819 fills with Reserved Future AD1819 fills with Reserved Future AD1819 fills with Reserved Slot, SLOT16 Mode extension Reserved Slot, SLOT16 Mode extension Reserved Slot, SLOT16 Mode extension
Corresponding ADSP-21065L SPORT0 Buffer Addresses Associated Timeslots rx_buf[9] SPORT receive buffer Slot Description Phase (AD1819) Status Address Port Status Data Port Master Capture (Record) Left Channel Master Capture Right Channel Slave Capture Left Channel Slave Capture Right Channel Slave Capture Left Channel Slave Capture Right Channel Data Memory Direct Address DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf DM(rx_buf
tx_buf[9] SPORT transmit buffer Slot Description Phase (DSP) Command Address Port Command Data Port Master Playback Left Channel Master Playback Right Channel Slave Playback Left Channel Slave Playback Right Channel Slave Playback Left Channel Slave Playback Right Channel Data Memory Direct Address DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf DM(tx_buf
Note: Even though there slots audio frame, buffer size well number channels enabled SPORT multichannel control registers) should size number slots containing valid data reduce IOP-bus overhead. single codec system, buffer sizes should words. dual codec system, buffer sizes should words while triple codec system, buffers words length. However, when processing data from transmit interrupt while running sample rate less than kHz, recommended dummy slots, dummy words transmit buffer. codecs, this would correspond words. will cover these recommendations sections 6.1, 6.3.
AD1819's Serial Configuration Register (Address 0x74)
AD1819's serial configuration register (located codec index address 0x74) additional functionality which Analog Devices addition register mapping AC'97 specification. Understanding this register successful communication between multiple AD1819As, especially variable sample rate applications running less than kHz. Serial Configuration Register allows perform following functions: Operate AC-link SLOT-16 mode, slots 16-bits length. This mode should soon codecs fully functional. Codec Register Mask Bits Master Codec, Slave Codec, Slave codec, thus allowing communicate codec time setting/reading registers. Setting Mask bits will allow program codecs same time. enable that will force Status Address Data Slots (Slots display contents serial configuration default. This will allow host processor read request bits codecs requesting data, which required DACs running slower rate different rate than ADCs. Below more detailed description Serial Configuration Register:
Serial Configuration (Index 74h)
Number Name Serial Configuratio
Default
SLOT1
REGM2
REGM
REGM0 DRQEN
DLRQ
DLRQ1
DLRQ0
DRRQ2
DRRQ1
DRRQ0
SLOT16 REGM0 REGM1 REGM2
Enable 16-bit slots SLOT16 makes Link slots bits length, formatted into Slots Master codec register mask Slave codec register mask Slave codec register mask your system uses only single AD1819, ignore register mask slave 1/slave request bits. write this register, write ones register mask bits. DxRQx bits read-only.
DRQEN
Fill idle status slots with request reads, stuffs requests into output address slot (AC-Link Slot DRQEN bit, then AD1819 will fill otherwise- unused AC-link status address data slots with contents register 74h. That makes somewhat simpler access information, because don't need continually issue Aclink read commands register contents. Also, requests reflected Slot bits (11.6).
DRRQ0 DRRQ1 DRRQ2 DLRQ0 DLRQ1 DLRQ2
Master codec right request Slave codec right request slave codec right request Master codec left request Slave codec left request Slave codec left request
codec asserts DxRQx when corresponding channel accept data next frame. These bits snapshots codec state taken when current frame began (effectively, rising edge SYNC), they also take notice samples current frame.
Configuring AD1819A Serial Link SLOT-16 Mode SPORT Compatibility
Slot 16-Mode allows efficient communication interface between DSPs AD1819A. Slot-16 mode useful since always 16-bits equal length slots eases serial port autobuffering chaining. DSPs that support interface usually provide capability program different slots different word lengths. This mode ensures that slots 16-bits, allowing much easier interface 16-bit/32-bit DSPs. will generate frame sync every serial clock cycles, instead having Phase slot with 20-bit slots, AD1819A will generate 16-bit slots serial clock cycles: Phase 20-bit timeslots)= clock cycles becomes, Phase 16-bit timeslots) clock cycles Note that will generate frame sync every serial clock cycles. With SCLK running 12.288 MHz, will then produce 48KHz frame sync SLOT-16 mode. initially configure AD1819A conform schemes, should initially program AD1819s 16-bit slots soon codec multiple codecs) operational. successful technique that been used ADI's Applications Group initially fill SPORT transmit buffer with register information codecs SLOT-16 mode. soon serial port operation enabled codecs reset fully operational, codecs will respond DSP's repeated request AC-link SLOT-16 mode. example, 21065L codec driver (shown Appendix initially fills tx_buf with correct phase info, serial configuration address, data codecs SLOT-16 mode with codec register mask bits set. buffer initialization shown below:
#define #define SERIAL_CONFIGURATION ENABLE_Vfbit_SLOT1_SLOT2 0x7400 0xE000
.var tx_buf[9] ENABLE_Vfbit_SLOT1_SLOT2, valid bits slot SERIAL_CONFIGURATION, serial configuration register address 0x74 0xFF80, initially SLOT-16 mode SPORT compatibility 0x0000, stuff other slots with zeros 0x0000, 0x0000, 0x0000, 0x0000, 0x0000;
Figure Enabling SLOT16 Mode Immediately After Sport Operation Begins
Phase Slot
SYNC (RFS0) SDATA_OUT (DT0)
E000
Data Phase
7400F F8000
DATA
LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
MASTER 1819
SLAVE1 1819 SLAVE2 1819
Note, 16-bit data intended slot shifted over 4-bits into slot-1 because default 20-bit slots
After codec reset, slots 1-11 20-bit slots, needs ensure that it's desired codec register data slot shifted bits take into account that slot bits after SPORT operation enabled (Figure 14). instead writing 0xF800 into Serial Configuration Register, sends 0xFF80. AD1819 will then recognize data 20-bit Command Register Data Slot that SLOT-16 mode required, well enabling register mask bits codecs. Setting mask bits codecs will allow program codecs same time same register configuration. Once SPORT0 enabled transfers initialized, will start transmitting above information codecs 16-bits slot.
Programming Multiple AD1819xs Serial Configuration Register
stated earlier, Serial Configuration Register (Address 0x74) Vendor Defined register Analog Devices. Multi-codec index register communication easily manageable through REGMx bits (D12, D14) Master Slave Slave codecs. bits shown bit-level chart address 0x74. Setting desired REGM corresponding codecs will determine that codec will respond Command Register reads writes.
Serial Configuration (Index 74h)
Number Name Serial Configuratio
Default
SLOT1
REGM2
REGM
REGM0 DRQEN
DLRQ
DLRQ1
DLRQ0
DRRQ2
DRRQ1
DRRQ0
Index 74h, (REGM0) enables Master AD1819 indexed address reads/writes Index 74h, (REGM1) enables Slave AD1819 indexed address reads/writes Index 74h, (REGM2) enables Slave AD1819 indexed address reads/writes table below shows Mask selection label names used 2106x codec driver example. These labels used Serial Configuration Register accessing registers codecs. Whenever command register writes sent address 0x74, 'SET BIT' instructions using these labels codec data bits D12, D14.
Selected AD1819 Master Slave1 Slave2 Master Slave1 Master Slave2 Broadcast
#define macro Label Name MASTER_Reg_Mask SLAVE1_Reg_Mask SLAVE2_Reg_Mask MASTER_SLAVE1 MASTER_SLAVE2 MASTER_SLAVE1_SLAVE2
Mask Bits 0x1000 0x2000 0x4000 0x3000 0x5000 0x7000
Codec Register Data Bits:
Note: 21062/Triple AD1819A MAFE EZ-LAB Codec Driver assumes that REGMx bits enable broadcast data writes codec indexed addresses. 21065L EZ-LAB Single AD1819A driver, only Master REGM0 set. Thus write codec indexed command register will broadcast register data writes codecs. Reading codec registers will result logical OR'ing index register masked codecs. example, with codec mask bits set, reading given register address will result data registers being logically OR'ed together. When attempting read multiple registers same time, codec higher chain will take precedence. example, when reading register from codecs, value Master's requested register contents will transmitted serial bus.
AD1819A Serial Configuration Register Master Slave Request Bits
Serial Configuration Register (Address 0x74), Vendor Defined register Analog Devices, includes support transmitting data DACs different sample rates than ADCs. Variable Sample Rate support, Analog Devices added request bits AD1819A's Serial Configuration Register. This feature allows sample rate conversion done AD1819A/DSP interface itself, removing burden from have include interpolation decimation routines change from sample rate another. AD1819A Variable Sample Rate Support defined follows: AD1819A capable sampling analog signals converting digital signals from increments either left right ADCs left right DACs. sample rate generator registers included AD1819A, either left right channels assigned either sample rate generated sample convert signals desired sample rate. normal AC-97 protocol specifies fixed sample rate, which valid sample transmitted received every audio frame. Since AD1819A slower sample rates, there will always valid sample every audio frame. application requires sample rate conversion, would need know when valid sample requested from AD1819A. example, sample rate different than sample rate, would need know when transmit data only when AD1819A needs sample. accomplish this, AD1819A's Serial Conversion Register Includes Left Right request bits (for Master, Slave1 Slave2 AD1819s) that will notify AC-97 host processor that needs sample next audio frame (based it's modified increment sample rate).
Serial Configuration (Index 74h)
Number Name Serial Configuratio
Default
SLOT1
REGM2
REGM
REGM0 DRQEN
DLRQ
DLRQ1
DLRQ0
DRRQ2
DRRQ1
DRRQ0
activate request support (which reset default operation), driver must write D11, DRQEN bit, Serial Configuration Register. Once enabled, idle Status Address Timeslot (AC-Link Timeslot will always transmit requests into Least Significant Bits Address Timeslot. previously idle Status Data Timeslot (AC-Link Timeslot will always contain contents Serial Configuration Register 0x74. This makes much easier access request information, because will have continually issue AC-link read commands request contents from register 0x74. request bits single codec AD1819A system should inspected looking DLRQ0 (bit Master codec left request Slot left channel sample requests DRRQ0 (bit Master codec right request Slot right channel sample requests. AD1819A asserts DxRQx when corresponding channel accept data next frame. These bits snapshots codec state taken when current frame began (effectively, rising edge SYNC), they also take notice samples current frame. choose poll requests Status Data Slot, these request bits ACTIVE HIGH. choose poll request Status Address Slot (Timeslot while SLOT-16 mode with DRQEN enabled, these bits ACTIVE should inspected following locations bits (not which true AC-97 mode). ordering request bits follows: Status Address Slot Assingments with DRQEN enabled given audio frame, Request, 1=No Request): Reserved (Stuffed with Control Register Index (when codec commands prior frame. this always shows 0x74) DLRQ0 Request Slot Master Codec Left DLRQ0 Request Slot Master Codec Right DLRQ1 Request Slot Slave1 Codec Left DLRQ1 Request Slot Slave1 Codec Right DLRQ2 Request Slot Slave2 Codec Left DLRQ2 Request Slot Slave2 Codec Right Reserved (Stuffed with
Programming AD1819A Indexed Control Registers
Addr. 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x74 0x76 0x78 0x7A 0x7C 0x7E Index Register Name Reset Master Volume Reserved Master Volume Mono Reserved PC_BEEP Volume Phone Volume Microphone Volume Line Volume Volume Video Volume Volume Record Select Record Gain Reserved General Purpose Control Reserved Power-Down Control/Status Reserved Serial Configuration Miscellaneous Control Bits Sample Rate Sample Rate Vendor Vendor #define label 2106x program REGS_RESET MASTER_VOLUME RESERVED_REG_1 MASTER_VOLUME_MONO RESERVED_REG_2 PC_BEEP_VOLUME PHONE_VOLUME MIC_VOLUME LINE_IN_VOLUME CD_VOLUME VIDEO_VOLUME AUX_VOLUME PCM_OUT_VOLUME RECORD_SELECT RECORD_GAIN RESERVED_REG_3 GENERAL_PURPOSE THREE_D_CONTROL_REG RESERVED_REG_4 POWER_DOWN_CNTL_STAT RESERVED_REG_5 SERIAL_CONFIGURATION MISC_CONTROL_BITS SAMPLE_RATE_GENERATE_0 SAMPLE_RATE_GENERATE_1 VENDOR_ID1 VENDOR_ID2 Defined State 0x0400 0x0000 0xXXXX 0x8000 0xXXXX 0x8000 0x8008 0x8008 0x8808 0x8808 0x8808 0x8808 0x8808 0x0404 0x0F0F 0xXXXX 0x8000 0x0000 0xXXXX 0x000X 0xXXXX 0xFF80 0x0000 0xBB80 0xBB80 0x4144 0x5300 DSP?
Registers highlighted bold have been altered from their default states 21065L talkthru example. Other registers that highlighted marked with their default reset state user configurable. other registers marked with DSP.
indexed control registers that used initially ADSP-21065L using memory buffer, where register addresses stored even number memory buffer locations, their corresponding register data stored adjacent numbered memory locations buffer. ADSP-21065L example, registers programmed during codec initialization. example assembly language buffer initialization shown below:
.var Init_Codec_Registers[34] MASTER_VOLUME, MASTER_VOLUME_MONO, PC_BEEP_Volume, PHONE_Volume, MIC_Volume, LINE_IN_Volume, CD_Volume, VIDEO_Volume, AUX_Volume, PCM_OUT_Volume, RECORD_SELECT, RECORD_GAIN, GENERAL_PURPOSE, THREE_D_CONTROL_REG, MISC_CONTROL_BITS, SAMPLE_RATE_GENERATE_0, SAMPLE_RATE_GENERATE_1, 0x0000, 0x8000, 0x8000, 0x8008, 0x8008, 0x0000, 0x8808, 0x8808, 0x8808, 0x0808, 0x0404, 0x0F0F, 0x8000, 0x0000, 0x0000, 0xBB80, 0xBB80;
Programming AD1819A Registers Using Zero Overhead Loop Construct
following assembly language hardware LOOP shows values Init_Codec_Registers[ buffer sent appropriate slots Serial Port bus:
#define #define #define #define ENABLE_Vfbit_SLOT1_SLOT2 TAG_PHASE COMMAND_ADDRESS_SLOT COMMAND_DATA_SLOT 0xE000
Initialize_1819_Registers: Init_Codec_Registers; ENABLE_Vfbit_SLOT1_SLOT2;
pointer codec initialization commands enable valid frame bit,and slots data bits
LCNTR Codec_Init UNTIL LCE; dm(tx_buf TAG_PHASE) valid slot bits phase slots 0,1,2 dm(I4, fetch next codec register address dm(tx_buf COMMAND_ADDRESS_SLOT) codec address into slot dm(I4, fetch register data contents dm(tx_buf COMMAND_DATA_SLOT) /*put codec register data into slot Codec_Init: idle; wait until frame transmitted
Explanation AD1819A Codec Initialization Loop buffer pointer first point codec register buffer. Slot Phase) enable valid frame bit, slot valid slot valid writing value 0xE000 DM(tx_buf Loop Counter Register LCNTR number registers programmed. this case registers three codecs will same value. multiple codecs programmed same configuration, initially filling tx_buf with initialized Serial Configuration Register Data, codecs SLOT16 mode with three Codec Register Mask bits set. three codecs will then respond command register address data writes. Memory writes DM(tx_buf will codec register address Memory writes DM(tx_buf will send register write data codec address specified previous timeslot. IDLE instruction will allow nothing wait SPORT0 transmit interrupt after data placed appropriate locations SPORT buffer tx_buf. Waiting SPORT interrupt will guarantee that data transmit buffer been shifted bus, thus telling safe next codec command register address register data value initialization buffer transfer those contents 'transmit buffer' queue.
Readback AD1819A Registers Verification Debugging Using ZeroOverhead LOOP
There instances during debugging stage driver code, programmer want verify desired values AD1819A's internal registers. easy this output buffer where read requests registers stored after codec initialization. readback status codec registers also done using hardware loop. following assembly language instructions shown below used initiate codec read requests registers shown Init_Codec_Registers[ buffer, which name buffer used AD1819a driver. results read requests then placed output buffer called Codec_Init_Results[ which even memory addresses contain AD1819A register address, DSP's address buffer contains register data AD1819A address. 21065L EZ-LAB, AD1819A registers then verified with JTAG emulator VDSP RS232 debug monitor setting breakpoint after this section code opening memory window that shows values stored memory buffer. After successful debugging custom code these instructions then removed.
#define #define #define #define #define
ENABLE_Vfbit_SLOT1 TAG_PHASE COMMAND_ADDRESS_SLOT STATUS_ADDRESS_SLOT STATUS_DATA_SLOT
0xC000
Verify integrity AD1819a indexed control register states communication successful verify_reg_writes: Init_Codec_Registers; Codec_Init_Results; ENABLE_Vfbit_SLOT1; enable valid frame bit, slots data bits LCNTR ad1819_register_status UNTIL LCE; dm(tx_buf TAG_PHASE) r15;/*set valid slot bits phase slots 0,1,2 dm(I4,2); indexed register address that inspected 0x8000; read request command address word read request with indirect register value dm(tx_buf COMMAND_ADDRESS_SLOT) /*send command address timeslot*/ idle; wait audio frame by,latency getting data idle; dm(rx_buf STATUS_ADDRESS_SLOT); dm(I5,1) dm(rx_buf STATUS_DATA_SLOT);/* fetch requested indexed register data dm(I5,1) store results buffer ad1819_register_status: nop; wait until frame transmitted
Explanation AD1819A Codec Register Readback Loop buffer pointers first point codec register buffer codec results buffer. Slot Phase) enable valid frame slot valid writing value 0xC000 DM(tx_buf Loop Counter Register LCNTR number registers read from AD1819A. this case registers codecs will same value. Memory writes from DM(tx_buf will read request codec register address specified Init_Codec_Registers[ buffer. Since modifying two, only reading AD1819A register addresses from thins input buffer, OR'ing read request (the MSB) transmitting read request address address timeslot. IDLE instructions required correctly readback codec, since audio frame required send readback request, audio frame then required send contents register requested next audio frame. Memory reads from DM(rx_buf will fetch register read address Memory reads from DM(rx_buf will fetch register read data codec address specified previous timeslot. pointer copies register address data Codec_Init_Results[ buffer every read request. resulting buffer contents alternates with codec addresses even addresses, codec data corresponding codec register address memory locations. This configuration similar that input Init_Codec_Registers[ buffer, user than easily compare codec programming buffer codec read results buffer.
Processing AD1819A Audio Samples SPORT
21065L's SPORT1 Interrupt Vectors Interrupt Service Routines used process incoming information from AD1819As through serial port. described earlier section 3.4, information sent from AD1819A DMA-Chained (i.e., SPORT receives entire block AD1819A frame data before SPORT interrupt occurs, settings automatically reloaded repeat transfer codec data) into rx_buf[ buffer interrupt generated when buffer filled with data. Therefore, when interrupt routine being serviced data from active receive timeslots been filled into receive buffer. When interrupt routine being services, data from buffer been transferred serial port. Output left right samples, codec commands, valid information filled into transmit buffer tx_buf[ transmission SPORT. programmer option executing algorithm from either transmit interrupt receive interrupt. Figure below shows high level logical view audio streams that processed when interfacing AD1819s SHARC DSP. With stereo ADCs DACs each codec, each SHARC serial port capable processing input audio channels send output audio streams output channels. This type multiple codec configuration find applications low-cost audio designs, such implementation channel digital mixing console, provide low-cost solution running surround algorithms requiring channels audio playback. With both SPORT0 SPORT1, ADSP-21065L interface AD1819s, resulting audio system with audio input output channels.
Figure High-Level View Three-AD1819 SHARC Audio System
Analog Stereo
Channel
ADSP-2106x
Daisy-Chained AD1819 Analog Front
Channel Channel Channel Channel
Processing
Channel
Using SPORT interrupt routine, processor detect valid data from codecs. DSP's interrupt routine then send audio data from given input channel that channels processing algorithm places results back output channel stream SPORT buffer) conversion that AD1819A DAC. this section will investigate methods processing data from either SHARC's SPORTx receive interrupt vector transmit interrupt vector. With AD1819A variable sample rate capabilities, possible sample signals rate playback samples another sampling rate. example codec driver Appendix shows test valid data coming current frame. sampling rates less than kHz, there will always valid data, DSP's SPORT audio processing must allow early return from interrupt with processing valid data detected current frame. example, running sampling rate would result valid data coming once every frames (48KHz Frame Rate sampling rate calls processing routines would made every SPORT calls. variable sample rate applications where there always valid sample audio frame, slot0 valid slot bits left/right channel data slot synchronization becomes more crucial cannot ignored programmer, SPORT timing relationships instance, interrupt routine poll valid bits buffer while valid left right data been DMA'ed into receive buffer. Another problem occurs when processing audio SPORT's interrupt with only slots/DMA words enabled. valid slot bits transmit buffer transmission, slot data already been DMA'ed SPORT registers. slot information, instead getting shifted next audio frame, will remain buffer will transmitted until following frame. Since will have been late write data transmit buffer because these TDM, interrupt timing differences, AD1819A will miss converting processed samples, resulting minor severe audible distortion. However, there tricks will discuss this section that will enable programmer successfully write variable sample rate codec driver. After extended testing experimenting search
most efficient driver implementations, found using SPORT interrupts process data, when setting codec sample rate less than default kHz., resulted lowest DSP's bandwidth utilization. However, rx-based processing with 16-word buffers active slots removes restriction having read write valid information early SPORT receive interrupt service routine. example AD1819A audio service routine data flow sequence (this procedure actually used reference ADSP21065L codec drivers) processing audio data SPORT1 transmit receive shown below Figure This diagram shows flow audio samples from serial port registers, buffers, from there, audio samples copied into temporary memory locations simple loopback, used inputs audio processing routines. output data then copied from output queue into transmit buffer, where then transferred SPORT transmit data register shifting serial port. Again, codec processing instructions serviced executed from either transmit receive interrupt vector. assume ADCs/DACs 48-kHz default sampling rate, there never concern bit, valid bit, request alignment. codecs kHz, then SPORT1 receive skip testing audio data since valid bits data should always 1's.
Figure Example 21065L EZ-LAB AD1819 Software Driver
SPORT1 Buffer
RX_BUF Slot Addr
SPORT1 data, register
Data Left Right
Audio Data Holders
Left_Channel_In) Right_Channel_In)
SPORT1 Buffer
TX_BUF Slot Codec Addr
SPORT1 data,
Codec Data Left Right
Audio Data Holders
DM(Left_Channel_Out) Right_Channel_Out)
Example SPORT1 Interrupt Service Routine Workflow
Initially clear transmit buffer slots tx_buf (stuff slots with data sent, conform AC'97 spec) Check AD1819 Stereo ADCs valid data from Phase Slot Also, instead polling Valid Bits, request bits address 0x74 checked DACs requesting data (This only applicable processing data sample rates less than kHz) Phase Bits slot Notify AD1819 DACs that valid data being transmitted current frame, depending either ADCs containing data, DACs requesting data. Based Step results, valid data from AD1819a SPORT receive buffer rx_buf Save Codec Data Registers Memory Processing Desired Algorithm Transmit Algorithmic Results AD1819A DACs SPORT buffer tx_buf.
Important 21065L EZ-LAB SPORT1 AD1819A Multichannel Timing Notes
single codec system (such 21065L EZ-LAB AD1819A), programmer needs careful choice implementing custom driver. Ideally, wish implement buffers with minimum amount memory required with least possible number channels enabled, memory savings reduction transfer bandwidth utilization. single AD1819A codec system, this would require buffer words. some cases, programmer discover that driver that runs successfully longer runs correctly slower sample rates. other instances, driver that clean distortion) kHz, integer divisor kHz, will sound distorted fractional sample rates such 8.124 kHz. This because fractional sample rate ratios kHz, valid bits being unpredictable patterns compared AD1819As request bits, which alternative patterns. this case algorithm result accidentally transmitted AD1819 twice skip output sample because data overruns under-runs. this section will timing various methods processing data successful DSP/Codec driver implementations. (The topics discussed here apply multi-codec systems with additional buffer words slots enabled, will discuss three codec system timing issues detail, since timing issues described here apply multiple AD1819As interfaced SHARC SPORT) SPORT chaining mode, interrupts always least timeslots apart (See Figure below). This because after Transmit downloaded from memory reactivated SPORT transmit channel prepares data transmission, controller initially places first words from SPORT transmit buffer into SPORT1 buffer FIFO registers. This automatically decrements Transmit Count Register two. After assertion chained-DMA interrupt, would need wait until active chained-DMA transfer brings data channels current frame which valid bits request bits set, because Receive Count Register always delayed behind Transmit Count Register value two. before timeslot even begins transmit/receive activity, Count while Count (assuming have declared 5-word buffers with active timeslots enabled serial port). transmit interrupt occurs when Count this interrupt request occurs second clock cycle immediately after timeslot received. While this transmit interrupt generated, transmit data left channel timeslot currently shifting SPORT's TX-shift register slot while AD1819 right channel data timeslot TX1A register queue, waiting transmitted after timeslot data finished shifting SPORT. time both transmit receive interrupts latched current frame (after timeslot TCBs will reloaded, internal memory transfers will occur until next frame sync, which would occur time-slots later (with exception words buffer, which reload into SPORT shift register data buffer TX1A previous channel data shift TX-shift register). After each reloading Transmit parameters, first values from buffer automatically reloaded into tx-shift register data buffer after previous timeslots data shifted SPORT TX-Shift register, remain 'tx-queue' until generates next frame sync within 16-bit timeslots. Figure AD1819/SPORT Timeslot, Count Interrupt Timing Relationships
RFS1 DR1_A
SLOT0 SLOT1 SLOT2 SLOT3 SLOT4 -//-No activity Slots Interrupt Here
CR1A (DMA Count Reg) DT1_A
SLOT0 SLOT1 SLOT2 SLOT3 SLOT4 -//-No activity Slots CT1A Interrupt Here (DMA Count Reg) queue reloaded with tx_buf values slots shifted SPORT1 12.288 SCLK) (16-bits/timeslot) timeslots) 2.604 microseconds Instruction Execution 16.667 nanoseconds instruction 2.604 microseconds 16.667 nanoseconds 156.25 cycles
Multichannel, Methods Implementation Processing Data
that have examined section relative timing difference SPORT interrupts between transmit receive channels, will investigate various implementation methods ensure proper data alignment processing data from AD1819A. Note that these methods apply single codec case they become necessary follow when running slower sample rates. multiple codecs, these recommendations still apply, additional buffer words number active timeslots enabled frame would need added extra timeslots words dual codec system, extra timeslots words triple codec system).
Insert Delay Loop 5-word buffers with channels active Audio processing SPORT Transmit Interrupt
method guaranteeing left/right data slots will available when entering SPORT interrupt detecting corresponding bits valid, implement delay loop simply wait data. This method only applicable have declared SPORT1 buffer size along with active channels enabled SPORT multichannel enable register, equivalent size SPORT1 buffer enabled channels. Immediately before fetching left right data delay loop added wait data. This coded follows:
LCNTR=126, Delay_Getting_Data UNTIL LCE; NOP;
Delay_Getting_Data:
This delay loop only required user needs sample rates with frame rate when processing data from interrupt while only declaring buffer size along with channels enabled. estimated that while waiting left channel slot takes Cycles MIPs. While waiting right channel data slot takes approximately cycles. Because interrupt latency previous instructions this point, found using 21065L EZ-LAB that Loop counter value guarantees enough time right channel data received. This approach probably acceptable most designs, been found work smaller audio applications. This definitely true programmer needs include other background processing interrupt routines that need executed during this time. Thus this method preferable method because loss MIPs bandwidth (about loss bandwidth utilization). programmer should instead steps loss bandwidth estimated follows: MIPs AC-97 Audio Frame Rate) 1250 cycles process data cycles 1100 cycles, about loss available MIPs Recommended Driver Settings: .var rcv_tcb[8] .var xmit_tcb[8] .var rx_buf[5]; .var tx_buf[5] 0xE000, 0x7400, 0xFF80, 0x0000, 0x0000;
receive transmit
receive buffer transmit buffer valid bits slot serial configuration register address Slot-16 mode stuff other slots with zeros
sport1 receive transmit multichannel word enable registers
0x0000001F; dm(MRCS1) dm(MTCS1) imask SPT1I;
enable transmit receive channels
enable sport1 xmit
buffer words length with slots active buffer words length with active slots Audio Processing SPORT Interrupt
efficient implementation extend buffer size length enable active channels. This will guarantee that time generates interrupt, left right data current frame have been received time before reading samples. Slots dummy slots never used. However, advantage this implementation that core held waiting left right channels DMA'ed into RX_BUF. order implement this method with 21065L EZ-LAB RS232 Debugger, programmer required SPORT1 register clear routine reset SPORT1 activity. refer Appendix example SPORT1 register-clear routine) Recommended Driver Settings: .var rcv_tcb[8] .var xmit_tcb[8] .var rx_buf[5]; .var tx_buf[7] 0xE000, 0x7400, 0xFF80, 0x0000, 0x0000, 0x0000, 0x0000;
receive transmit tcb, count
receive buffer transmit buffer valid bits slot serial configuration register address Slot-16 mode stuff other slots with zeros
slots dummy slots
sport1 receive multichannel word enable registers 0x0000001F; enable receive channels dm(MRCS1) sport1 transmit multichannel word enable registers 0x0000007F; enable transmit channels dm(MTCS1) imask SPT1I; enable sport1 xmit
Both SPORT Interrupts audio processing receives AD1819A Data TAG/DAC reqister information transmits processed audio data AD1819A DACs 5-Word Buffers with rx/tx timeslots enabled
Using this method, buffer size active channels then both SPORT1 interrupts send/receive AD1819a audio data. Refer alternate AD1819 reference code this solution. Valid Bits Request Bits information passed from SPORT receive SPORT transmit through register variable stored memory.
Recommended Driver Settings: .var rcv_tcb[8] .var xmit_tcb[8] .var rx_buf[5]; .var tx_buf[5] 0xE000, 0x7400, 0xFF80, 0x0000, 0x0000;
receive transmit
receive buffer transmit buffer valid bits slot serial configuration register address Slot-16 mode stuff other slots with zeros
sport1 receive transmit multichannel word enable registers 0x0000001F; enable transmit receive channels dm(MRCS1) dm(MTCS1) imask SPT1I SPR1I; enable both sport1 xmit
When using audio processing transmitting output audio data AD1819A (using either methods programmer approximately cycles (assuming operation) upon entering SPORT write information DM(TX_BUF which phase slot, order that left right transmit data slots within same audio frame slot. done time, would send data current frame, bits would sent following frame. would then risk dropping samples, severe audible distortion results. timing requirement writing location estimated follows: 12.288 SCLK) (16-bits/timeslot) timeslots) 1.302 microseconds Instruction Execution 16.667 nanoseconds instruction microseconds 16.667 nanoseconds 156.25 78.125 cycles cycle interrupt request CLKIN cycle after last serial word shifted SPORT) cycles Interrupt Vector Latency cycle sync latch, cycle recognition, cycles branch vector) Instruction Cycles write from Therefore, when processing data slower sample rates kHz, recommended SPORT interrupt process audio transmit data this only required whenever using word buffer sizes. This reason using instead this situation follows: were processing, whenever interrupt occurs, slot data buffer already been loaded into TX1A register waiting next frame sync. Thus would late write buffer offset because already been transferred controller SPORT circuitry. This transfer would have occurred approximately timeslot, BIT_CLK cycles prior entering Interrupt Service Routine. fixed sample rate applications, interrupt still used process codec data selected algorithm, since bits valid left/right data occur every frame will always set. programmer therefore would concerned with polling valid bits request bits. one-audio-frame delay' would result transmitting processed data, realtime latency would negligible. actually would transmitting left right data that would correspond bits previous audio frame ISR, which does adhere AC-97 specification. However, since valid bits valid bits set, programmer longer concerned with carefully setting them appropriate time since these bits will always set.
Interrupt Audio Processing 5-word Buffer slots enabled 16-word Buffer Slots enabled
This method will allow programmer interrupt audio processing, without having install jump call routine SPORT interrupt vector after programming AD1819A. Another benefit that processing data from interrupt that guarantee that data left right information left right data been received newly filled buffer, after generation interrupt after slot (SLOT while same time interrupt will continue send dummy 'zero's timeslots This will ensure that there plenty time write slot location DM(TX_BUF time DSP's audio processing routine, long done before completion transmission SLOT14 data. After SLOT14 transmitted, ADSP-21065L will data into SPORT's TX1A register, while SLOT begins shifted SPORT T-shift register SLOT15 transmission. With this approach programmer safely wait duration 16-bit timeslots before writing value DM(TX_BUF which will transmitted following frame. terms cycles, this equates SLOT DMA'ed into TX1A register) SLOT5 Count cycle interrupt request CLKIN cycle after last serial word shifted into SPORT r-shift register) cycles Interrupt Vector Latency cycle sync latch, cycle recognition, cycles branch vector) SLOT SLOT5 16-bit slots SCLK cycles 171.25 Cycles Instruction Cycles Therefore, programmer Instruction Cycles (assuming operation) within 21065L SPORT Interrupt Service Routine which required write transmit slot information into DM(TX_BUF that correctly gets transmitted next audio frame. advantage this method that programmer restricted having write location beginning ISR. drawback that requires more memory buffer, transfer overhead increased from transfers 21065L's bus. Recommended Driver Settings: .var rcv_tcb[8] .var xmit_tcb[8] .var rx_buf[5]; .var tx_buf[16] 0xE000, 0x7400, 0xFF80, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
receive transmit tcb, count
receive buffer transmit buffer valid bits slot serial configuration register address Slot-16 mode stuff other slots with zeros
0x0000, 0x0000; sport1 receive multichannel word enable registers 0x0000001F; enable receive channels dm(MRCS1) sport1 transmit multichannel word enable registers 0x0000FFFF; enable transmit channels 0-15 dm(MTCS1) imask SPR1I; enable sport1
Using Valid Bits' Method 'DAC Request Bits' Method Transmit Processed Audio Data AD1819A DACs (For Variable Sample Rates kHz)
When processing audio data SPORT's transmit receive interrupt service routine, programmer option either poll valid bits incoming data request bits Serial Configuration address 0x74) determine when transmit processed audio data AD1819A DACs next audio frame. prepare data transmit next audio frame, DSP's SPORT instructions should simply include data transfers appropriate locations SPORT transmit buffer, which turn transferred serial port next frame sync assertion. DSP's SPORT interrupt routine's codec-specific instructions either would poll rx-ADC valid bits slot (slot poll request bits either Slot1 Slot2. either valid bits requests made, then executes instructions ensure that bits (slot left right channels set, since will place processed data left channel slot (slot right channel slot (slot4). will look both methods offer advantages disadvantages using either method.
6.3.1 'ADC Valid Bits' Method Polling Valid Bits Phase (Slot upon entering SPORT/codec interrupt service routine will tell needs fill buffer slots with valid data transmission next audio frame. Usually, will first poll these bits determine have save process left/right audio data slots Once save sample processing, will only transmit valid bit's corresponding channel data have received samples. This method more pipelined FIFO approach, which always will transmit newly processed sample DACs next audio frame every time sample process Using 'ADC valid bits' method usually yields clean ADC-DSP-DAC loopback path fractional variable sample rates kHz. Figure following page visually shows 21065L SPORT transmit receive buffers point when vectors SPORT interrupt process data. Typically, would this sort display RS232 VDSP monitor debugger JTAG VDSP EZ-ICE's 'two-column memory window'. Inspecting contents SPORT receive buffer 'rx_buf' will give indication have data. these valid bits set, then ensure that corresponding channel data will available SPORT transmit buffer transmission following audio frame. newly-filled SPORT receive buffer contains data from previous audio frame. that valid bits slots slot DM(rx_buf well Codec Ready D15, valid data exists slots DM(rx_buf +3), DM(rx_buf Slots 'Don't Care' conditions ignored this case. will usually contain status last codec read, DRQEN set, these slots will display contents address 0x74, serial configuration register. When detects that there valid data, then calls user's processing routine, sets flag notify background task that there data process. Thus, slower sample rates less than kHz, will only execute routine when detects valid data, result, will only transmit data when data that channel valid previous frame current SPORT ISR. Now, examining contents Transmit buffer figure below, that data copied into buffer transmitted next frame sync assertion result
detecting valid data previous frame. Since there valid data rx_buf[ ensures that valid bits slots well `Valid Frame' D15, DM(tx_buf +0). interrupt routine also places processed audio samples Slots Left Right channels. Unused slots filled with zeros.
Figure 'ADC Valid Bits' Method Transmitting Data Next Audio Frame
SPORT1 Receive Buffer
SPORT1 Transmit Buffer
rx_buf
rx_buf rx_buf rx_buf rx_buf rx_buf
Phase Addr Status Data Status Left Data Right
tx_buf
tx_buf tx_buf tx_buf tx_buf tx_buf
Phase Addr Command Data Command Left Data Right
0x9800 0xXXXX 0xXXXX 0x4012 0x40AB
0x9800 0x0000 0x0000 0x578A 0x32F
will examine some example 21065L Assembly Language Instructions incorporated 21065L SPORT Interrupt Service Routine (listed Appendix that show detect valid bits then slot bits transmission data next audio frame valid bits set. These instructions check have data from slot reading from DM(rx_buf Masking that value with 0x1800 tests positions corresponding slots
check_ADCs_for_valid_data: dm(rx_buf TAG_PHASE); 0x1800; dm(ADC_valid_bits) valid bits from phase slot*/ Inspect valid data Mask other bits
then quickly bits slots This will either bits left right channel zero valid data, will bits valid bits were set, thus will filling buffer locations with left right channel data:
set_tx_slot_valid_bits: dm(tx_buf TAG_PHASE); dm(tx_buf TAG_PHASE) SPORT! valid bits based valid bits info left/right channel bits tag, required Write tx-buf ASAP before it's shifted
that bits, save current left right channel data processing. will only save data whenever detect that have valid data. This done using SHARC's shifter 'Bit Test' instruction, then testing shifter result zero. zero, have valid data, move result '1', then save newly detected sample. This done follows:
check_AD1819_ADC_left: BTST M_Left_ADC; Check Master left valid
JUMP check_AD1819_ADC_right; dm(rx_buf LEFT); lshift dm(Left_Channel_In) check_AD1819_ADC_right: BTST M_Right_ADC; rti; dm(rx_buf RIGHT); lshift dm(Right_Channel_In)
valid data then save sample Master 1819 left channel input sample shift MSBs preserve sign 1.31 format save data holder processing
Check Master right valid valid data then save sample Master 1819 right channel input sample shift MSBs preserve sign 1.31 format save data holder processing
then call algorithm. This conditionally called only have detected audio data:
user_applic: call DSP_Audio_Routine; processing finished, playback results AD1819
After processing data, re-test valid bits determine needed send results next audio frame. these bits '1', copy results left right channels slots SPORT1 transmit buffer, where will await transmission AD1819A DACs through AC-link.
Playback_audio_data: Transmit Left Right Valid Data every time there ADCs have valid data dm(ADC_valid_bits); tx_AD1819_DAC_left: BTST M_Left_ADC; JUMP tx_AD1819_DAC_right; dm(Left_Channel_Out);/ lshift -16; dm(tx_buf LEFT) r15; tx_AD1819_DAC_right: BTST M_Right_ADC; jump tx_done; dm(Right_Channel_Out); lshift -16; dm(tx_buf RIGHT) r15;
Check need send right sample valid data then transmit sample channel output result back bits 0.15 SPORT output right result AD1819a Slot
Check need send right sample valid data then transmit sample channel output result back bits 0.15 SPORT output right result AD1819a Slot
Thus, 'ADC Valid Bits' Method provides easy predictable transmit data next audio frame. This method usually yields clean audio without Tag/Data/DMA timing issues that cause distortion sample rate values less than kHz. Ring buffers required fractional sample rate ratios. There limitations using this method process audio data. channels (LADC/LDAC RADC/RDAC) only same sample rates. cannot both ADCs DACs different rates unless AD1819A's request bits polled. will cover this method detail following section.
6.3.2 'DAC Request Bits' Method Polling Request Bits Serial Configuration Register (automatically Status Address Status Data slots when DRQEN set) when enter SPORT interrupt service routine will tell needs fill buffer slots with valid data transmission next audio frame. First, valid bits should polled determine have save process left/right audio data slots Once valid samples detected saved processing, will only transmit data Request Bits were AD1819A's Serial Configuration Register 0x74. This method fairly pipelined integer ratio sample rates that never have ADC/DAC sample overruns underruns, while fractional sample ratios ring buffers handle ADC/DAC sample rate jitter recommended (see next section). obvious benefit gained with polling request bits, that free left/right ADCs different sample rates than DAC, thus removing sample rate conversion routines DSP.
Figure 'DAC Request Bits' Method Transmitting Data Next Audio Frame
SPORT1 Receive Buffer
SPORT1 Transmit Buffer
rx_buf
rx_buf rx_buf rx_buf rx_buf rx_buf
Phase Addr Status Data Status Left Data Right
tx_buf
tx_buf tx_buf tx_buf tx_buf tx_buf
Phase Addr Command Data Command Left Data Right
0xF800 0x7400 0xF901 0x4012 0x40AB
0x9800 0x0000 0x0000 0x578A 0x32F
Figure shown above visually shows 21065L SPORT transmit receive buffers point when vectors SPORT interrupt process data. stated before, would this sort display RS232 VDSP debugger JTAG VDSP ICE's 'two-column memory window'. Inspecting contents SPORT receive buffer 'rx_buf' will give indication have data, AD1819A DACs requesting data request bits. these request bits set, then ensure that corresponding channel data will available SPORT transmit buffer transmission following audio frame. newly-filled SPORT receive buffer contains data from previous audio frame. that valid bits slots slot DM(rx_buf well Codec Ready D15, valid data exists slots DM(rx_buf +3), DM(rx_buf Slots contain information request bits through automatic display Serial Configuration Register (Codec address 0x74). This data automatically displayed when DRQEN this register. When detects that there valid data when detects request bits set), call user's processing routine, flag notify background task that there data process. programmer process data when either valid bits request bits current audio frame. Thus, slower sample rates less than kHz, will only execute filter routine detects valid data requests), result, will only transmit data when data that channel valid current audio frame SPORT ISR. Now, examining contents Transmit buffer figure above, that data copied into buffer transmitted next frame sync assertion result detecting valid data previous frame. Since there valid requests both left right channels rx_buf[ will ensure that valid bits slots well `Valid Frame' D15, DM(tx_buf +0). interrupt services routine also places processed audio samples Slots Left Right channels. Unused slots filled with zeros. will examine some example 21065L Assembly Language Instructions incorporated SPORT Interrupt Service Routine (listed Appendix that show detect active Request Bits, then transmit data slot bits transmission next audio frame: These instructions used poll "Active Low" Request bits Status Address Slot shift these bits, invert values, then used them bits left right timeslots
Check_DAC_request_bits: dm(rx_buf STATUS_ADDRESS_SLOT); request bits from address slot Mask AD1819 Master DRRQ0 DLRQ0 bits active request bits active lshift shift output info bits then copy shifted request information notify AD1819 slots will contain valid data. bits
set, then will copy data current ISR. This gets copied into Phase Slot
Set_TX_slot_valid_bits: 0x8000; dm(tx_buf TAG_PHASE) Write tx-buf ASAP before it's shifted out! valid bits based received request info Valid Frame Valid Slot bits slot phase
then poll Slot have data save data valid.
dm(rx_buf TAG_PHASE); information inspect valid data
before with 'ADC Valid Bits Method', detect valid data (bit value '1') save current left and/or
right channel data processing. validity tested with SHARC's barrel shifter:
check_AD1819_ADC_left: BTST M_Left_ADC; JUMP check_AD1819_ADC_right; dm(rx_buf LEFT); lshift dm(Left_Channel_In) check_AD1819_ADC_right: BTST M_Right_ADC; jump user_applic; dm(rx_buf RIGHT); lshift dm(Right_Channel_In) Check Master left valid valid data then save sample Master 1819 left channel input sample shift MSBs preserve sign 1.31 format save data holder processing
Check Master right valid valid data then save sample Master 1819 right channel input sample shift MSBs preserve sign 1.31 format save data holder processing
then call algorithm. This conditionally called only have detected audio data: user_applic: call (pc, DSP_Audio_Routine); processing finished, playback results AD1819
After processing data, test Request bits determine needed send results next audio frame. these bits set, copy results left right channels slots SPORT1 transmit buffer, where will await transmission AD1819A DACs through AC-link.
Playback_audio_data: Transmit Left Right Valid Data Requested r2=DAC_Req_Left; Check Left REQ? r3=r1 request active jump bypass_left; means have request, move on*/ dm(Left_Channel_Out); channel output result lshift -16; back bits 0.15 SPORT dm(tx_buf LEFT) r15; output right result AD1819a Slot bypass_left: r2=DAC_Req_Right; r3=r1 jump bypass_right; dm(Right_Channel_Out); lshift -16; dm(tx_buf RIGHT) r15;
Check Right REQ? request active means have request, move on*/ channel output result back bits 0.15 SPORT output right result AD1819a Slot
6.3.3 Single (Master) AD1819A Valid Request Reference Charts Tables below used reference inspecting Valid Bits, Request Bits audio data during debugging Single (Master) AD1819A Codec System:
Note: single codec systems, request bits zero'ed both Slave1 Slave2 locations. AD1819A Master Codec stuffs zeros these locations. cases below (which were observed with Target65L RS232 VDSP Debugger), Slot16 mode enabled, RegMx bits set, even though there only master. Status Address Slot Request Bits 'Active Low'. Status Data Slot Request Bits 'Active High'
Status Address Slot Single Codec System with requests, inactive bits slaves Dreq Dreq Slot3 Slot4 Status Data Slot Single Codec System with Left Right requests, inactive bits slaves Slot16 REGM2 REGM1 REGM0 DRQEN DLRQ0 DRRQ0 Table Comparison Valid Request Bits 'ADC Valid Bits' Method: Current Audio Frame (Read SPORT buffer) Valid Bits
0x9800 0x8800 0x9000 0x8000
Next Audio Frame (fill SPORT buffer) Right Timeslot
Valid Data Zero Fill Valid Data Zero Fill
Request Bits
0xXXXX 0xXXXX 0xXXXX 0xXXXX
Left Channel Timeslot
Valid Data Valid Data Data
Right Channel Slot Left Timeslot Timeslot
Valid Data Data Valid Data Data 0x9800 0x8800 0x9000 0x8000 Valid Data Valid Data Zero Fill Zero Fill
'DAC Request Bits' Method: Current Audio Frame (Read SPORT buffer) Valid Bits
0xF800 0xF800 0xF800 0xF800 0xF000 0xF000 0xF000 0xF000 0xE800 0xE800 0xE800 0xE800 0xE000 0xE000 0xE000 0xE000
Next Audio Frame (fill SPORT buffer) Left Timeslot
Valid Data Valid Data Zero Fill Zero Fill Valid Data Valid Data Zero Fill Zero Fill Valid Data Valid Data Zero Fill Zero Fill Valid Data Valid Data Zero Fill Zero Fill
Request Bits (slots
0x7400 0x7440 0x7480 0x74c0 0x7400 0x7440 0x7480 0x74c0 0x7400 0x7440 0x7480 0x74c0 0x7400 0x7440 0x7480 0x74c0 0xF901 0xF900 0xF801 0xF800 0xF901 0xF900 0xF801 0xF800 0xF901 0xF900 0xF801 0xF800 0xF901 0xF900 0xF801 0xF800
Left Channel Right Channel Timeslot Timeslot Timeslot
Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Data Data Data Data Data Data Data Data Valid Data Valid Data Valid Data Valid Data Data Data Data Data Valid Data Valid Data Valid Data Valid Data Data Data Data Data 0x9800 0x9000 0x8800 0x8000 0x9800 0x9000 0x8800 0x8000 0x9800 0x9000 0x8800 0x8000 0x9800 0x9000 0x8800 0x8000
Right Timeslot
Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill Valid Data Zero Fill
Processing Data Fractional (Versus Integer) Variable Sample Rate Ratios 'DAC Request Bits' Method
would like offer thanks Clark, Danville Signal Processing, suggestions using ring buffers process AD1819A data fractional sample rate ratios) above methods work well slower sample rates that integer ratio values kHz. Methods described section 6.2, source code examples Appendix execute correctly processing data AD1819A sample rates kHz, kHz, kHz. example, when program AD1819A ADCs DACs sample rate kHz, expect receive sample once every frames required requested AD1819a request bit) transmit data once every audio frames. kHz, would expect transmit receive data once ever frames, kHz, once every audio frames. Normally these even spacing samples, would ever risk sample overruns underruns because data will evenly pipelined DSP. However, when running AD1819A fractional ratios using valid bits receive data request bits transmit data, occasional sample repeat sample miss occur. This because received valid data AD1819A requests random relative another ADCs DACs, sample rates say, 23456 8201 44100. When processing data interrupt service routine polling fetched Valid Bits from receive slot, only execute routine every time valid data. After processing current valid samples, would normally place results buffer DACs when ready. problem DACs have been requesting data AD1819A request bits next audio frame, risk occasionally drop processed sample. Also, valid bits given frame, processing done, same time, could consecutive 'DAC request bit' audio frames. This then would result repeating back output sample twice, since algorithm processed current interrupt service routine. Keep mind, this nothing with 'REPEAT ZERO FILL SAMPLE' that AD1819A's Miscellaneous Control Bits Register starved. That functionality controlling internal operation AD1819A DACs send requested sample given frame. course, input output sample rates different, would then expect some interpolation decimation samples occur, which repeating skipping processed samples back AD1819A output DACs from processing routine because DACs running different sample rate than ADCs. Here, only concerned about specific case where ADCs sample rate equivalent DACs, want ensure every sample processed processed samples sent back AD1819A. example, were look scenario (Figure where Valid Bits being non-integer ratios AD1819A, while same time, requests made AD1819A DACs keep data filled same noninteger sample rate ratio, something like this:
Figure Non-Periodic Valid Request Patterns
SYNC Pulse |-|_|-|_|-|_|-|_|-|_|-|_|-|_ Frame
Val. Req. Left Data Right DatNote:
Frame (N+1)
Val. Req. Left Data Right
Frame (N+2)
val. Req. 0x0000 0x0000
Frame (N+3)
Val. Req. Left Data Right
Frame (N+4)
val. Req. 0x0000 0x0000
Frame (N+5)
val. Req. 0x0000 0x0000
Frame (N+6)
Val. Req. Left Data Right
0x0000 Data left channel timeslot current audio frame 0x0000 Data right channel timeslot current audio frame AD1819A stuffs invalid slots with 'zeros'
Notice Figure above that consecutive audio frames, valid bits back-to-back, while request will made same audio frames. Another possible scenario that occur that consecutive audio frames, valid bits while same time while consecutive requests made same audio frames. exactly these cases that occur when sample rates ADCs DACs fractional ratios, such 12345 This cause problems:
process consecutive samples, place result holding register case driver, these variables memory) waiting AD1819A request does make request, then there possibility that that processed sample will overwritten next audio processing interrupt routine. receive samples samples given frame, however AD1819A DACs make consecutive requests processed audio data waiting DSP's holding register variable memory). this case there possibility that processed sample will transmitted DACs twice, before able replace with updated processed sample.
solution this 'equal ADC/DAC fractional sample rate ratio case' when using 'DAC Request Bits' method ring buffer. ring buffer piece allocated memory that designed that it's addressing data periodically allowed overflow underflow) certain predetermined number locations. Ring buffers often used prevent sampling jitter sampling clocks, which affect quality audio signal. With insertion ring buffer, unpredictability valid requested data given audio frame between ADCs DACs longer affected. memory buffer increases DSP's capturing data because sample frequency variations ADCs DACs absorbed buffer. Valid AD1919A Left/Right DATA AD1819A request variations fractional sample rates cause input output data rate vary independent audio frames. ensure have smooth flow data running fractional ratios kHz, programmer implement small ring buffer (Figure left right channel prevent occasional sample repeat miss when running fractional rates. recommended scheme that been found work create (depending performing mono stereo processing) small 4-word 8-word) ring buffers 'FETCH DATA' 'SEND DATA' sections AD1819A processing routine (see figure below). small circular ring buffers initialized such that output pointer offset input pointer locations memory. This would least guarantee, applications where AD1819A ADCs same fractional sample rate DACs, that input pointer would never pass output pointer, vary samples ahead from output pointer. effective delay will always samples, which means would always between '48-kHz' audio frames behind getting input sample into DSP, sending result back out. This delay, course, real-time processing negligible affect listener real-time audio applications.
Figure AD1819A Left Right Channel Ring Buffers
0x7FEB0110
0x7A122112
0xAB12F127
0xA648BD12
Input Pointer Left Channel Ring Buffer
AD1819A Left Output From Buffer
Input Pointer Right Channel Ring Buffer
AD1819A Right Output From Buffer
Below example ring buffer implementation left right channels. Note that this code optimized. intermediate pointer states input output restored saved using same index register that using separate index registers implement these ring buffers input output taps. With some additional overhead only need index register. programmer dedicated index register each input output pointer there enough available their application then remove memory pointer save restore instructions. Appendix also includes ring buffer source code with 'DAC Request Bits' Method.
.segment/dm dm_data; .var Lchan_ring_buff[4] .var Rchan_ring_buff[4] .var L_input_ptr; .var L_DAC_output_ptr; temporary storage Index register .var R_input_ptr; this saves from using DAGs .var R_DAC_output_ptr; .endseg; -.segment/pm pm_code; initialize ring buffer input output pointers Lchan_ring_buff; DM(L_input_ptr) Lchan_ring_buff DM(L_DAC_output_ptr)
start output middle buffer
Rchan_ring_buff; DM(R_input_ptr) Rchan_ring_buff start output middle buffer DM(R_DAC_output_ptr) both ring buffers words deep these instruction added AD1819A Interrupt Service Routines where codec data received, processed transmitted input output ring buffers words deep left_ring_buffer_input: DM(rx_buf LEFT_CHANNEL); Lchan_ring_buff; DM(L_input_ptr); DM(I0,M1) DM(L_input_ptr) right_ring_buffer_input: DM(rx_buf RIGHT_CHANNEL); Rchan_ring_buff; DM(R_input_ptr); DM(I0,M1) DM(R_input_ptr) left_ring_buffer_output: Lchan_ring_buff; DM(L_DAC_output_ptr); DM(I0,M1); DM(L_DAC_output_ptr) DM(tx_buf LEFT_CHANNEL) right_ring_buffer_output: DM(R_DAC_output_ptr); DM(I0,M1); DM(R_DAC_output_ptr) DM(tx_buf RIGHT_CHANNEL) .endseg;
NOTE:
Based Applications Group's 'loopback' listening tests distortion (i.e. clean audio) fractional sample rate ratios using 'ADC Valid Bits transmission' Method, determined that Ring Buffers really required. With this method transmission, Left/Right sample only transmitted next audio frame whenever receive Left/Right sample. This appears properly pipeline input samples from SPORT into 21065L's algorithm back SPORT without dropping rarely dropping) samples, because AD1819A's Left Right 'conversion hold' register will never overwritten with value received through AD1819A's serial interface while waiting convert previous sample back analog signal. With this alternate method, 'valid' sample timeslots received previous frame with always ensure that will transmit 'valid' timeslots AD1819A next audio frame. Thus, 'ADC Valid Bits' Method does require ring buffers when sample rate equivalent sample rate both channels. When sample rates same given channel, this results valid patterns being identical valid bits which following frame. Since these Bits phase', never really into situation where processed sample skipped repeated conversion.
Using Valid Flag Valid Flag Variables Processing Audio Data Variable Sample Rates
certain applications, user want process codec data elsewhere. example, C-based applications, C-runtime routines placed main program 'while' loop waiting SPORT interrupts. codec interrupt service routine's responsibility would receive transmit codec data, while processing data done elsewhere. slower sample rates, processing routine would need know which SPORT interrupt actually received valid data. processing routine would also responsible notifying codec transmit routine that valid processed data that transmitted back DACs. order implement such scheme, user define variables that used transmit receive request flags that when data ready, cleared after data been transferred. example, 21065L demo examples (Figure dual buffer scheme, which allows user copy data into temporary buffer when Request variable been codec receive interrupt routine, while buffers currently being filled, user processed data from alternate background buffers. After audio data processed, information copied transmit user buffer, request variable set. codec processing routine detects that valid data transferred into user output buffer, copied data into SPORT transmit buffer transmission AD1819. responsibility processing routine clear flags after data been processed flags when there processed data available codec ISR. responsibility codec interrupt service routine flag valid data received from buffer, clear flag after transmit data been copied buffer.
Figure 21065L/AD1819A Flag-Set-Clear Transfer Scheme
Request
User Buffer
Buffer
SPORT1
AD1819A Codec
User Buffer Buffer
Request
Scheme Used with 21065L RS232 Monitor Demonstration Programs When SPORT1 transmit empties transmit buffer, SPORT1 transmit interrupt occurs. routine that executed elsewhere would Request data available. variable Request then SPORT1 interrupt service routine loads data from processed User Buffer into TXDMA Buffer; otherwise, Buffer loaded with After Buffer loaded, automatically re-initialized transmit data Buffer. With this structure place, user needs only data User Buffer, then Request send data CODEC. receive portion CODEC interface designed similar way. SPORT1's receive register configured load Buffer. When Buffer full, SPORT interrupt forced Request variable there valid data. routine conditionally called Request variable set. variable then contents Buffer written into User Buffer, Request cleared. reinitialized fill Buffer again
Assembly Language Ready Flag Code Example ADC/DAC Sample Rate, with Frame Rate
following example shows routine Codec interrupt service routine would only process data whenever there data available. Codec sets flags whenever data available. routine clears flags after that data been processed. Since running kHz, routine would only executed once every interrupts, since:
Audio Frame Rate Sample Rate AC'97 Audio Frames Sample
.VAR RX_left_flag; algorithm only processed when these bits .VAR RX_right_flag; SPORT1 Interrupt Service Routine section where data received check_AD1819_ADC_left: BTST M_Left_ADC; Check Master left valid JUMP check_AD1819_ADC_right; valid data then save sample dm(rx_buf LEFT); Master 1819 left channel input sample lshift shift MSBs preserve sign 1.31 format dm(Left_Channel_In) save data holder processing dm(RX_left_flag) have left sample, routine know check_AD1819_ADC_right: BTST M_Right_ADC; Check Master right valid jump user_applic; valid data then save sample dm(rx_buf RIGHT); Master 1819 right channel input sample lshift shift MSBs preserve sign 1.31 format dm(Right_Channel_In) save data holder processing dm(RX_right_flag) have right sample, routine know routine section where flag variables cleared Echo: process both channel inputs input samples from data holders dm(Left_Channel_In); left input sample dm(Right_Channel_In); right input sample ashift scale signal equal ashift scale signal equal 1/2xL(n) xR(n) dm(delay_time); output circular delay line dm(i6, point d-th data register fetch address with update delayed signal together with original signal ashift scale input signal equal ashift scale delayed signal equal 1/2xL(n) xR(n) write output samples AD1819 ashift dm(Left_Channel_Out) dm(Right_Channel_Out) Master Codec channels turn volume little left output sample right output sample
input sample into tap-0 delay line,post-modify address after storage input dm(i6, value from register into delay line decrement address dm(RX_left_flag) clear RX_left_flag since have processed incoming data*/ dm(RX_right_flag) clear RX_rightflag since have processed incoming data*/ rts; Return from Subroutine
Processing 16-bit Data 1.31 Fractional Format IEEE Floating Point Format
Data that received transmitted SPORT1 binary, complement format. interprets data fractional format, where between 0.9999999. Initially, serial port places data into internal memory data bits D15. order process fractional data 1.31 format, processing routine first shifts data bits that left-justified upper data bits D31. This necessary take advantage fixed-point multiply/accumulator's fractional 1.31 mode, well offer easy reference converting from 1.31 fractional floating point formats. This also guarantees that quantization errors resulting from computations will remain well below result thus below AD1819A Noise Floor. After processing data, shifts 1.31 result down 16-bits that data truncated 1.15 number. This 1.15 fractional result then sent AD1819A. Below example instructions demonstrate shifting data before after processing data Master AD1819 left channel: 32-bit Fixed Point Processing
dm(rx_buf lshift dm(Left_Channel)=r1; AD1819A left channel input sample shift MSBs preserve sign save data holder processing
Process data here, data processed 1.31 format channel output result back bits 0.15 SPORT output left result AD1819A Slot
dm(Left_Cha
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