Bill Winderweedle ABSTRACT Texas Instruments (TI) TMS320VC5471 TMS320V

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Bill Winderweedle ABSTRACT Texas Instruments (TI) TMS320VC5471 TMS320V

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Using Boundary Scan TMS320VC5471/VC5470 DSPs
Bill Winderweedle ABSTRACT Texas Instruments (TI) TMS320VC5471 TMS320VC5470 DSPs (hereafter referred VC547x) dual-core processor devices implementing standard IEEE 1149.1 boundary scan capability. This application report contains description VC547x boundary scan implementation information about with other boundary scan tools devices. material covered this application report assumes reader familiar with boundary scan concepts defined IEEE Standard 1149.1. overview these concepts presented IEEE 1149.1 (JTAG) Testability Primer (literature number SSYA002). detailed information operation requirement boundary scan, refer IEEE standard itself. Copies standard available from IEEE 1-800-678-IEEE. C5000 Applications Team
Contents VC547x Boundary Scan Implementation VC547x Silicon Revision Requirements Observe Control Capability VC547x Hardware Requirements Boundary Scan Test VC547x Boundary Scan Coverage VC547x Boundary Scan Description Language (BSDL) Implementation VC547x Boundary Scan Instruction Implementation List Figures Figure Figure Figure Initialization Boundary Scan Test Mode Using TRST, EMU0 EMU1/OFF Boundary Scan Structure VC547x VC547x Subsystems Modeled "Module" Scan Chain List Tables Table Device Pins Testable Through Boundary Scan
IEEE Standard 1149.1-1990 Standard Test-Access Port Boundary Scan Architecture
trademarks property their respective owners.
SPRA379
VC547x Boundary Scan Implementation
VC547x Silicon Revision Requirements
VC547x boundary scan implementation described this document applies silicon revisions.
Observe Control Capability
VC547x implements standard observe control capability with respect IEEE Standard 1149.1. This means pins with input functions (input pins) have observe capability pins with output functions (outputs pins) have control capability.
VC547x Hardware Requirements Boundary Scan Test
Boundary scan test requires control five test-access port signals (TMS, TCK, TDI, TRST) described IEEE standard 1149.1. additional signals, EMU0 EMU1/OFF, used DSPs provide emulation debug capability through JTAG test-access port. Also, uses these signals scan-based factory tests. During boundary scan tests, EMU0 EMU1/OFF must held high while TRST transitioned from high. This operation sets correct internal test mode boundary scan test performed. EMU0 EMU1/OFF should pulled high through 4.7-k pullup resistors each pin. pullup resistors connected DVDD power supply VC547x. Boundary scan automatic test pattern generation (ATPG) tools should configured cycle TRST prior beginning boundary scan tests ensure that device proper test mode.
TRST
EMU0
EMU1/OFF
Test Mode Boundary Scan
Figure Initialization Boundary Scan Test Mode Using TRST, EMU0 EMU1/OFF
VC547x Boundary Scan Coverage
digital pins VC547x have boundary scan cells test with following exceptions. device pins testable through boundary scan shown Table
Using Boundary Scan TMS320VC5471/VC5470 DSPs
SPRA379
Table Device Pins Testable Through Boundary Scan
DVDD, CVDD, TMS, TCK, TDI, TDO, TRST EMU0, EMU1/OFF Power supply pins JTAG test access pins Emulation test pins Function
VC547x Boundary Scan Description Language (BSDL) Implementation
representation internal structure VC547x with respect boundary scan shown Figure VC547x composed internal processor [general-purpose processor (GPP) digital signal processor (DSP)] subsystems internal ASIC logic. Each subsystems ASIC logic have independent controllers provide boundary scan test emulation capability. device signals TMS, TCK, TRST connected each parallel. device connected subsystem. internal equivalent subsystem connected internal subsystem. internal equivalent subsystem connected internal ASIC TAP. output chain from ASIC connected device TDO. boundary scan test system, this structure equivalent treating subsystems independent devices.
VC547x
Subsystem Subsystem ASIC
Controller
Controller
Controller
TRST
Figure Boundary Scan Structure VC547x
registered trademark Advanced RISC Machines (ARM) Limited.
Using Boundary Scan TMS320VC5471/VC5470 DSPs
SPRA379
Although ATPG tools vary they describe system-level structure, tools provide method describe order devices scan chain. BSDL description VC547x implemented three BSDL files, each subsystem ASIC TAP. These three boundary scan objects must always used together described ATPG tools proper order. ASIC must described subsystem closest TDO, with subsystem middle, subsystem closest TDI. order reversed, tests generated ATPG tools will incorrect. connection between scan chains subsystems internal device. Similarly, subsystem ASIC internally connected. Some ATPG tools issue warning error indicating that TDO-TDI connections between subsystems ASIC objects present. this case, device modeled multichip module using hierarchical capabilities ATPG tool. Many boundary scan systems have hierarchical scan chain descriptions where, example, plug-in module described sub-chain main boundary scan chain. model sub-chain generated separately, then referenced description main boundary scan chain. same approach used model VC547x single object necessary. device modeled sub-chain composed subsystem, subsystem, ASIC, shown Figure Then, VC547x referenced main description scan chain single device "module". Since methods describe hierarchical modular systems tool-dependent, single method cannot described here. will necessary contact ATPG tool vendor regarding this procedure done their particular tool. Given BSDL files each information this document, model generated.
VC547x described module ATPG tools allowing referenced single object.
VC547x
Internal TDO-TDI Connections Upstream Devices Scan Chain Subsystem Subsystem Downstream Devices Scan Chain
System
ASIC
System
System System System TRST
Figure VC547x Subsystems Modeled "Module" Scan Chain Separate BSDL files provided subsystem, subsystem, ASIC TAP. Current VC547x BSDL files information available
Using Boundary Scan TMS320VC5471/VC5470 DSPs
SPRA379
ASIC ability capture control pins device during boundary scan test. subsystems control device pins purpose boundary scan testing bypassed. Section 1.6, VC547x Boundary Scan Instruction Implementation, BSDL files more details.
VC547x Boundary Scan Instruction Implementation
VC547x implements following instructions boundary scan:
SAMPLE/PRELOAD EXTEST BYPASS HIGHZ
IEEE standard 1149.1 specifies that SAMPLE/PRELOAD instruction samples inputs preloads does drive outputs. During SAMPLE/PRELOAD instruction, device pins maintain their normal functional behavior. behavior VC547x during execution this instruction consistent with specification standard. ASIC supports this instruction. IEEE standard 1149.1 specifies that EXTEST instruction samples inputs, loads drives outputs. behavior VC547x during execution this instruction consistent with specification standard. ASIC supports this instruction. IEEE standard 1149.1 specifies that BYPASS instruction maps 1-bit bypass register between minimize chain length when device being tested) device pins operate their normal functional (non-test) mode. behavior VC547x during execution this instruction consistent with specification standard. Note that VC547x bypass each subsystem (since there controller each subsystem) total three bits between device TDO. This behavior accounted (and maintains compliance with IEEE standard 1149.1) through separate BSDL files each subsystem. ASIC both subsystem TAPs support this instruction IEEE standard 1149.1 specifies that HIGHZ instruction places bypass register scan chain causes output pins (either dedicated outputs pins) enter high-impedance state. behavior VC547x during execution this instruction consistent with specification standard. ASIC supports this instruction. None other boundary scan instructions specified optional IEEE standard 1149.1 implemented VC547x.
Using Boundary Scan TMS320VC5471/VC5470 DSPs
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Bill Winderweedle ABSTRACT Texas Instruments (TI) TMS320VC5471 TMS320V

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