Bill Winderweedle Jack Rosenzweig Denise Ombres ABSTRACT TMS320VC547x
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TMS320VC5470/5471 Bootloader
Bill Winderweedle Jack Rosenzweig Denise Ombres ABSTRACT TMS320VC547x devices, TMS320VC5470 TMS320VC5471, have master TMS470R1x (ARM7TDMIE) microcontroller (MCU) central processing unit (CPU) with slave TMS320C54x digital signal processor (DSP) CPU. Bootload accomplished through while held reset. Since resides these devices, bootloader code transferred on-chip through several interfaces sent through internal memory interface DSP. This document describes method boot loading through external memory interface. Catalog, C5000 Hardware Applications Software Development Systems Software Development Systems
Contents TMS320VC5470/TMS320VC5471 Bootloader Supported Configurations Bootloading Process 1.2.1 Bootloader Phase 1.2.2 Bootloader Phase 1.2.3 Bootloader Phase 1.2.4 Bootloader Execution Flow Chart 1.2.5 Converting COFF Files Into C-Language Header Files Bootloader Example 1.3.1 Building Bootloader Example 1.3.2 Executing Bootloader Example External Flash External SRAM Considerations References
Appendix Registers List Figures Figure Sub-System Memory Port Interface Boot Mode (APIBN ABMDIS Figure Sub-System Memory Normal Boot Mode (APIBN ABMDIS Figure Bootloader Execution Flow Chart Figure OUT2BOOT Format Code Data Figure Bootloader Build Flowchart
TMS470R1x TMS320C54x trademarks Texas Instruments. Trademarks property their respective owners.
SPRA376
Figure Figure Figure Figure Figure
Bank-Switching Control Register (BSCR) Control Register (APIC) Port Interface Wait-State Configuration Register (API_REG) Reset Control Register (CLKM_CNTL_RESET) Phase-Locked Loop Register (DSP_REG) List Tables
Table Software Handshake Memory Locations
TMS320VC5470/TMS320VC5471 Bootloader
This document describes process which TMS470R1x (ARM7TDMIE) master processor loads code into C54x slave processor after power-on reset.
Supported Configurations
Both little- big-endian loading supported. Supports loading into flash memory Spectrum Digital TMS320VC5470/5471 board Code Composer Studio OMAP Visual Studio v6.0 (optional)
Bootloading Process
responsible setting memory register bits (MP/MC, OVLY, DROM APIBN), copying bootloader into internal memory shared port interface, before releasing from reset. clock, clock, port interface internal-memory wait states must initialized before bootload process run. Manipulating memory must done carefully, because possible swap memory that currently executing from. With this consideration, bootloader program three distinct phases, each with memory configuration. Following description these phases.
1.2.1
Bootloader Phase
Phase starts with MP/MC OVLY DROM port interface boot mode (see Figure When OVLY DROM cleared, expects find external program memory space. arm-port-interface boot mode, shadows 0x3F80 0x3FFF into normal reset vector space 0xFF80 0xFFFF. following steps executed from code shadowed reset vector, starting 0x3F80:
Write 0xFFA8 PMST register OVLY DROM bits proper enabling internal program memory space. Branch address 0x3810, which start bootloader program phase
C54x, Code Composer Studio, OMAP trademarks Texas Instruments.
TMS320VC5470/5471 Bootloader
SPRA376 Page Program, MP/MC (Microprocessor Mode) OVLY Reserved 007F 0080 1FFF 2000 37FF 3800 3FFF 4000 5FFF 6000 On-Chip Data DARAM On-chip Data DARAM, DARAM Port InterfaceA Accessible On-Chip Data SARAM External Program Space Memory OVLY External Program Space Memory Page Program, MP/MC (Microcomputer Mode) OVLY Reserved 007F 0080 1FFF 2000 37FF 3800 3FFF 4000 5FFF 6000 On-Chip Data DARAM On-Chip Data DARAM, DARAM Port InterfaceA Accessible On-Chip Data SARAM External Program Space Memory OVLY External Program Space Memory
0000
0000
0000
Data
Memory-Mapped Registers, Scratch-Pad 007F 0080 1FFF 2000 37FF 3800 3FFF 4000 5FFF 6000 7FFF 8000 BFFF C000 On-Chip Data DARAM (8K-0x80 0x80 words) On-Chip Data DARAM, Port Interface-Accessible Interface Accessible words) (Shadowed portion) On-Chip Data SARAM words, data only) On-Chip Data SARAM words) External Data Space Memory DROM=1 On-Chip Program SARAM words) On-Chip Program SARAM words) DROM=0
External Program Space Memory
External Program Space Memory DFFF E000
External Data Space Memory
F7FF F800 FFFF Shadowed Port Interface DARAM (2K)
F7FF F800 FFFF Shadowed Port Interface DARAM (2K)
F7FF F800 FFFF
External Data Space Memory
NOTE: When APIBN ABMDIS words port interface DARAM re-mapped program-space. other internal program-space RAMs disabled program space. Data-space RAMs dual-mapped program-space OVLY.
Figure Sub-System Memory Port Interface Boot Mode (APIBN ABMDIS
1.2.2
Bootloader Phase
Phase starts with MP/MC OVLY DROM port interface boot mode (see Figure When OVLY DROM set, expects find internal program memory space. port interface boot mode, shadows 0x3F80-0x3FFF into normal reset vector space 0xFF80-0xFFFF. following step executed from code port interface-accessible memory starting 0x3810.
Write 0x0010 BSCR register clear port interface boot mode bit. This takes port interface boot mode places into normal boot mode, which allows access C54x reset vector program space address range 0xFF80-0xFFFF.
TMS320VC5470/5471 Bootloader
SPRA376 Page Program, MP/MC (Microprocessor Mode) OVLY Reserved 007F 0080 On-Chip Data DARAM 1FFF 2000 On-Chip Data DARAM, Port InterfaceAccessible On-Chip Data SARAM 5FFF 6000 7FFF 8000 OVLY External Program Space Memory External Program Space Memory External Program Space Memory External Program Space Memory Page Program, MP/MC (Microcomputer Mode) OVLY Reserved 007F 0080 On-Chip Data DARAM 1FFF 2000 On-Chip Data DARAM, Port InterfaceAccessible On-Chip Data SARAM 5FFF 6000 7FFF 8000 9FFF A000 External Program Space Memory BFFF C000 DFFF E000 FFFF FFFF OVLY External Program Space Memory External Program Space Memory External Program Space Memory External Program Space Memory
0000
0000
0000
Data
Memory-Mapped Registers, Scratch-Pad 007F 0080 On-Chip Data DARAM (8K-0x80 words) 1FFF 2000 On-Chip Data DARAM, Port Interface-Accessible Interface Accessible Words)
3FFF 4000
3FFF 4000
3FFF 4000
On-Chip Data SARAM words) 5FFF 6000 7FFF 8000 External Data Space Memory BFFF C000 DROM=1 On-Chi On-Chip Program SARAM DROM=0 External Data-Space Memory On-Chip Data SARAM, words, data only) words
External Program Space Memory
On-Chip Program SARAM words, program only) words On-Chip Program SARAM words, program only) On-Chip Program SARAM words, program only) On-Chip Program SARAM Words) On-Chip Program SARAM words)
FFFF
Figure Sub-System Memory Normal Boot Mode (APIBN ABMDIS
1.2.3
Bootloader Phase
Phase starts with MP/MC OVLY DROM normal boot mode. expects program memory space internal. normal boot mode reset vector space from 0xFF80-0xFFFF accessible. Currently, none program data memory space been initialized, except that bootloader program been loaded into port interface-accessible memory space from 0x3810-0x3900. There four handshake variables held port interface memory from 0x3800 0x3803 used boot-copy process. Also, PMST value used written location 0x3804. Table summarizes software handshake memory locations.
TMS320VC5470/5471 Bootloader
SPRA376
Table Software Handshake Memory Locations
Address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3900 0x3F80 Handshake DSP_Ready Prog_Buf_Ready Data_Buf_Ready Copy_Done PMST_VAL API_BUF_START API_BUF_END Description When set, signals that normal boot mode. When set, signals that transferred code port interface memory. This code ready transferred runtime memory. When set, signals that transferred data port interface memory. This data ready transferred runtime memory. When set, signals that completed transfer code data port interface memory. boot from reset vector 0xFF80. PMST value used proper configuration memory Starting address port interface buffer written temporary storage code/data transferred DSP. Starting address port interface memory shadowed reset vector 0xFF80 when port interface boot mode.
following steps executed Bootloader, which resides port interface-accessible memory starting 0x3810:
sets DSP_Ready word value 0x0001, which tells that normal boot mode ready start boot-copy process. copies code sections program into port interface transfer buffer. When buffer becomes full, moves buffer contents into program memory space. synchronize their access port interface buffer Prog_Buf_Ready handshake flag. process repeated until last section program code copied, which indicated section zero length. Using same algorithm, data sections program loaded. Data_Buf_Ready handshake flag used synchronization between DSP. will Copy_Done word value `0x0001', which signals that boot-copy process completed. Once sees Copy_Done word equal 0x0001, will branch reset vector 0xFF80 begin normal execution.
NOTE: reset vector will valid since initialized during program memory boot-copy process.
1.2.4
Bootloader Execution Flow Chart
Figure shows order actions each processor, well synchronization that needs occur between them control timing execution. NOTE: following items have been simplified better readability flow chart:
Some configuration steps shown. separate loadings program data sections shown single loop flow chart; however, reality these done consecutive loops. "arm port interface buffer ready" handshake flag shown flow chart represents separate flags: Prog_Buf_Ready, Data_Buf_Ready.
TMS320VC5470/5471 Bootloader
SPRA376
Port Interface Boot Mode Copy Loader Port Interface Branch Bootloader Disable Port Interface Boot Mode
Release From Reset
"DSP Ready" Flag "DSP Ready" Flag
Copy Next Section Bits Port Interface Buffer
"Arm Port Interface Buffer Ready" Copy Port Interface Buffer Run-Time Destination
Port Interface Buffer Full, Last Section "Arm Port Interface Buffer Ready" Flag
Port Interface Buffer Ready" Flag Cleared Clear "Arm Port Interface Buffer Ready" Flag
"Copy Done"?
Last Section Bits?
"Copy Done" Flag Start Main Application
Branch Application
Figure Bootloader Execution Flow Chart
TMS320VC5470/5471 Bootloader
SPRA376
1.2.5
Converting COFF Files Into C-Language Header Files
Since different types processors, code needs converted into format usable MCU. this, COFF file output converted into language header files, which declare arrays initialized with contents COFF file. This conversion accomplished using converter program OUT2BOOT. This converter uses assembly language tool HEX500 extract code from COFF file. TMS320C54x Assembly Language Tools User's Guide (SPRU102) information common object file format (COFF) HEX500 conversion utility. OUT2BOOT program calls HEX500 convert COFF file into binary output files: program memory code other data memory contents. Then, OUT2BOOT converts these binary files into language header files, which used include files with code. combined code then placed into flash accessed from external memory interface. header file consists array that holds sections code/data (see Figure record consisting following fields represents each section:
section length 16-bit words destination run-time address section. code/data words section.
Array length, address, length, address, length, address, line signifies program code data
data, data, data, final
Figure OUT2BOOT Format Code Data
Bootloader Example
Included with this application report example load program into processor from MCU. This application continuously toggles pin, which flashes LED. Listed below VC++ Studio Code Composer Studio projects, which build individual components this example. NOTE: compressed file which accompanies this application report, c547x_bootloader.zip, should copied Code Composer Studio <drive>:\ti\myprojects directory extracted there into directories referenced below following build example relative c547x_bootloader directory.
.\out2boot: VC++ Studio project which builds out2boot.exe conversion utility. This tool converts COFF File into C-language header. source code provided, well executable, .\out2boot\out2boot.exe. .\dsp_proj: Code Composer Studio project which builds simple application toggle pin. application modified replaced include code. .\dsp_boot: Code Composer Studio project which builds C54x-side bootloader program, dsp_boot.out. This program copies application from port interface memory runtime location memory. This project should modified.
TMS320VC5470/5471 Bootloader
SPRA376
.\arm_boot: Code Composer Studio project which builds ARM-side bootloader program, arm_boot_le_flash.out little-endian arm_boot_be_flash.out big-endian. program initializes device copies bootloader application into port interface memory. Once this completed, main program simply loops indefinitely, while application continuously flashes LED. This project modified include other code modified out2boot) loaded MCU.
1.3.1
Building Bootloader Example
build bootloader example, follow these steps (Figure needed, VC++ Studio workspace file, .\out2boot\out2boot.dsw, build conversion utility .\out2boot\out2boot.exe. Otherwise, just existing executable skip this step. Configure Code Composer Studio using provided configuration files:
Code Composer Studio Setup program Choose File->Import menu option. Click Advanced button. Browse .\config directory, select .Code Composer Studio file that appropriate your memory setup. Different configuration files provided support various memory layouts. example, choose c5471_le_ramlow.ccs little-endian, RAM-low memory.
Using C54x Code Composer Studio project file, .\dsp_proj\dsp_proj.prj, build sample application .\dsp_proj\dsp_proj.out. post-link step this project will invoke out2boot utility dsp_proj.out image, copy resulting C-header files, dsp_proj_code.h dsp_proj_data.h, into the. \arm_boot directory. Using C54x Code Composer Studio project file, .\dsp_boot\dsp_boot.prj, build bootloader program .\dsp_boot\dsp_boot.out. post-link step this project will invoke out2boot utility dsp_boot.out image, copy resulting C-header file, dsp_boot_code.h into the. \arm_boot directory. Choose Code Composer Studio project file appropriate your memory byte ordering, .\arm_boot\arm_boot_le.prj .\arm_boot\arm_boot_be.prj, build bootloader program, little-endian big-endian. When switching between big- little-endian modes, Project->Rebuild within Code Composer Studio because most files within each project same will re-compiled with Project->Build.
TMS320VC5470/5471 Bootloader
SPRA376
dsp_proj project files
dsp_boot project files
Project Build
Project Build
dsp_proj.out
dsp_boot.out
out2boot
out2boot
dsp_proj_code.h dsp_proj_data.h
arm_boot project files
dsp_boot_code.h
Project Build arm_boot_le arm_boot_be
arm_boot_le_flash.out arm_boot_be_flash.out
Figure Bootloader Build Flowchart
TMS320VC5470/5471 Bootloader
SPRA376
1.3.2
Executing Bootloader Example
execute bootloader example, follow these steps (NOTE: directories referenced below relative Code Composer Studio root installation directory project sub-directory): C5471 board, configure JP19 big-endian (1-2) little-endian (2-3) mode. Also, ensure that JP20 32-bit (Flash) Size (1-2). arm_boot code examples included with bootloader 32-BIS. chosen byte ordering instruction must match those followed during build bootloader example. Start Code Composer Studio. This should Parallel Debug Manager. From Parallel Debug Manager open Code Composer Studio. From Parallel Debug Manager open C54x Code Composer Studio. C54x Code Composer Studio debug window, make sure that running state. This will indicated bottom window. not, then execute Debug->Reset CPU, followed Debug->Run Free. Code Composer Studio debug window, load executable: little-endian big-endian. Code Composer Studio debug window, execute Debug->Run. should begin blink.
External Flash External SRAM Considerations
Debug difficult within flash EPROM devices because lack support breakpoints inability instantaneous writes these types memories. Writes flash must performed through custom algorithms developed with 547x devices other means. Spectrum Digital created algorithms with their Flash utility program flash memories their 5470/5471 boards. bootloader example code some modifications allow booting from external flash devices compatibility with debug within external SRAM. These special modifications form embedded assembly code instructions within boot vector program file, big-endian little-endian, properly configure MEMINT, API_REG, DSP. This code linked reset vector 0x0000:0000. Similar code replicated within Code Composer Studio file, .\gel\c5471_be_ramlow_mcu.gel big-endian .\gel\c5471_le_ramlow_mcu.gel little-endian, allow proper setup when debugging from external SRAM mapped reset vector. executable produced from Code Composer Studio project build compatible both external SRAM loading external flash image building booting. Within Code Composer Studio external SRAM debug session, bootloader COFF will loaded entry point label "c_int00". When executing bootloader from external flash, boot vector program will take care necessary device configuration, previously mentioned, before branching entry point.
TMS320VC5470/5471 Bootloader
SPRA376
References
TMS320C54x Assembly Language Tools User's Guide (SPRU102). TMS320C54x Peripherals Reference Volume (SPRU131). TMS320VC547x Peripherals Reference Guide (SPRU038). TMS320VC5471 Fixed-Point Data Manual (SPRS180). TMS320VC5470 Fixed-Point Digital Signal Processor (SPRS017). TMS470R1x 32-Bit RISC Microcontroller Family User's Guide (SPNU134). TMS470R1x Assembly Language Tools User's Guide (SPNU118). TMS320VC5470/5471 Evaluation Module Technical Reference (SPRU135). Spectrum Digital Flash Utility
TMS320VC5470/5471 Bootloader
SPRA376
Appendix
BNKCMP R/W-1111 reserved R/W-0 Legend: Read/Write ABMDIS R/W-0
Registers
PS-DS R/W-1 HINT R/W-0 APIMODE R/W-0 reserved R/W-0 reserved R/W-0 EXIO R/W-0
Figure A-1. Bank-Switching Control Register (BSCR)
reserved reserved Legend: Read only; Write only HINT DSPINT APIMODE reserved
Figure A-2. Control Register (APIC)
reserved reserved Legend: Read only; Write only APICS APIBS APIWS
Figure A-3. Port Interface Wait-State Configuration Register (API_REG)
TMS320VC5470/5471 Bootloader
SPRA376
reserved reserved reserved Legend: Read only; Read/Write EXTERNAL RESET R/W-0 RESET R/W-1
Figure A-4. Reset Control Register (CLKM_CNTL_RESET)
reserved reserved reserved DSPPLL FRRSN R/W-0 DSPPLL FRPLLDIVN R/W-0 DSPPLL FRPLLONOFF R/W-0 DSPPLL FRDIV0 R/W-0 DSPPLL FRDIV1 R/W-0 MPNMC R/W-0 DSPPLL FRDIV2 R/W-0 APIBN R/W-0 DSPPLL FRDIV3 R/W-0
DSPPLL SHUTOFF R/W-0 DSPPLL FRDIVN R/W-0
Legend: Read only; Read/Write
Figure A-5. Phase-Locked Loop Register (DSP_REG)
TMS320VC5470/5471 Bootloader
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