Clay Turner Digital Signal Processoring Solutions Abstract T

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Sequential Addressing Ports TMS320C54x
Clay Turner Digital Signal Processoring Solutions
Abstract
Texas Instruments TMS320C54x, port addresses hard-coded opcodes PORTW (I/O port write) PORTR (I/O port read) instructions. This document discusses tables data transferred using sequential port addresses. fact that port addresses PORTR PORTW instruction hard-coded makes reading writing table data sequential addresses space difficult. simplest method would have sequence PORTx instructions with each address specified explicitly. Although this method will work, consumes many instructions there entries table program memory words PORTx instruction). alternative method takes advantage ability overlay on-chip DARAM C54x. code listing included.
Contents
Design Problem Solution
Examples
Example Sequential addressing PORTW instruction
Digital Signal Processing Solutions
December 1998
Design Problem
TMS320C54x, port addresses hard-coded opcodes PORTW (I/O port write) PORTR (I/O port read) instructions. tables data transferred using sequential port addresses?
Solution
fact that port addresses PORTR PORTW instruction hardcoded makes reading writing table data sequential addresses space difficult. simplest method have sequence PORTx instructions with each address specified explicitly. Although this method will work, consumes many instructions there entries table program memory words PORTx instruction). alternative method shown Example takes advantage ability overlay on-chip DARAM C54x. When on-chip DARAM block "overlaid" (due OVLY being this block memory accessible from both program space data space mapped same addresses both memory spaces. given memory address program memory physically same location address data memory. Consequently, access data memory used modify program memory. This capability utilized dynamically change address coded PORTx instruction that each pass loop, address different. example this implementation shown below Example
Example Sequential Addressing PORTW Instruction
start: ;set OVLY=1 ;pointer data memory address ;pointer port address ;update PORTW instruction with address S#table_length,BRC ;initialize RPTB end_block-1 PORTW *ar2+,0h ;copy word from data space space increment data memory address *ar3+ increment memory address MVMD ar3,(portloc+1) ;update PORTW instruction ;with address ;wait MVMD pipeline latency ;wait MVMD pipeline latency ;(portloc+1) updated SSMVMD #00020h,pmst #01000h,ar2 #02000h,ar3 ar3,(portloc+1)
portloc:
end_block:
this example, used pointers tables data space space, respectively. source table located address 01000h data space. destination table located address 02000h space. MVMD instruction used modify port address PORTW instruction. port address second word instruction indicated address higher than location PORTW instruction using label (portloc+1).
Sequential Addressing Ports TMS320C54x
each pass loop, data copied from data memory address (pointed AR2) port address that currently loaded PORTW opcode. instruction increments AR3, which keeps track desired port address. MVMD copies that address into second word PORTW instruction. result block locations data memory being copied block locations space. two-cycle latency between MVMD instruction modifies port address PORTx instruction. This occurs because MVMD instruction writes change (portloc+1) execute phase pipeline, PORTx instruction will read port address during second cycle fetch phase pipeline. least cycles must exist between MVMD instruction PORTx instruction that follows make sure that address been modified before fetched. instructions example serve this latency, useful one-cycle instructions single two-cycle instruction could replace them. instruction could even replace instructions starting address corrected accordingly. port address indicated PORTx instruction this example) irrelevant because gets modified anyway. approach similar Example used with PORTR instruction. operands PORTR instruction will simply reversed. this implementation, each pass loop will require minimum cycles execute (assuming external memory wait states minimized). this code successfully, OVLY must this code must stored on-chip DARAM. addresses data tables limited.
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Sequential Addressing Ports TMS320C54x

Clay Turner Digital Signal Processoring Solutions Abstract T

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