Erich Vogel Technical Staff, Jose Wireline Communications Abstrac
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Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Erich Vogel Technical Staff, Jose Wireline Communications
Abstract
transmission voice over data networks long been dismissed unfeasible incompatibility voice traffic data traffic resulting unacceptable voice quality. market such systems, however, witnessing surprising growth potential advantages system cost infrastructure rise alternative networking options, such Aand frame relay. Market requirements practical cost-effective solutions driving Voice-over-Network (VoN) systems process increasing numbers voice channels smaller platforms. This paper discusses hardware software issues involved designing such system using Texas Instruments TMS320C54x digital signal processor (DSP). Specifically, discussion centers system architectural issues multiprocessor-based approach process multiple voice streams. Topics include voice network interfaces DSP, common software algorithms, system control, hardware architectures.
Contents
Introduction Voice Interface System Control Interface Application Software Network Interface Conclusion
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure System Block Diagram Voice Interface.3 Transceiver Serial Port Interface System Control Voice Encoder Block Diagram (Ingress) Voice Decoder Block Diagram (Egress) Distributed Software Configuration AInterface Block Diagram.13 Host/HPI Interface
Digital Signal Processing Solutions
March 1999
Introduction
products have recently witnessed unforeseen growth form single-user Internet-based telephony larger scale concentrators equipment routing telephone calls over private network trunks. This growth attributed primarily economic practical advantages combining voice data services over common medium. voice-over-network systems, bears responsibility converting continuous voice streams into forms suitable reliably transmitting over packet- cell-based network. tasks this process include
Packetization Voice processing compression Network delay concealment Line echo cancellation Efficient bandwidth utilization
Creating cost-effective solution, major goal most designs, often requires that boards process many channels possible. solution this problem twofold: Increasing number channels processed each Increasing number DSPs board
Each solution presents individual design challenges. number voice channels that each manage function algorithms, speed DSP, available memory. Packing multiple DSPs board involves other issues, such board area constraints, communication bandwidth, routing, power dissipation. This paper introduces system-level design considerations such voice-overnetwork solution based multiple TMS320C54x platform. C54x well suited such applications software availability, power dissipation, appropriate peripherals memory. Topics covered this discussion include hardware architectures, system control options, application software requirements design integration voice-over-network system. However, this report intended provide complete reference design, rather outline framework which base such design. block diagram Figure provides general system overview required voiceover-network solution. block diagram divided into following areas: voice interface, array (including software), system control, packet (network) interface. Each will discussed individually with emphasis centered DSPs their contribution.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Figure System Block Diagram
System Controller
Voice Interface
Network Interface
Network
Voice Interface
voice interface provides mechanism transmit receive digital voice between telephone system DSP. details this process depend source voice data. simple single-channel case could consist digital telephone connected serial link DSP. This discussion, however, will center aggregate voice streams such those from PBX, requiring service multiple processors. most common mediums transmitting such multi-channel digital voice traffic (US) (Europe) lines, employing time-division access scheme. Figure shows block diagram major components involved such interface including line interface, framer, channel distribution, serial interface.
Figure Voice Interface
Serial Port
Line Interface
Framer
Channel Distribution Serial Port Interface
Serial Port
Serial Port
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Line Interface Framer
front-end element interfacing T1/E1 line transceiver, which contains several components, including line interface, framer, often buffer. line interface serves physical connection twisted pair transmitting receiving analog signal waveforms recovering clocking information used synchronization. Connecting transceiver line also requires several additional components, including transformers line filters. Next, framer buffer detect frame, multiframe, channel boundaries data stream, monitoring error conditions alarms, buffer blocks data connection processor. Multiple channels digital data transmitted over lines time-division multiplexed (TDM) fashion. Each timeslot, DS0, consists signaling information eight bits data. Timeslots further grouped into elements called frames, DS1s. Both standards adopt different channel attributes, such timeslots frame base clock rate which bits transmitted. stream employs channels frame operates rate 1.544 Mbps (1.536 which available data). data transmitted 2.048 Mbps contains channels. both systems, channels contain eight bits data transmitted kbps. Each channel also contains associated signaling consisting information about state call, whether on-hook, off-hook, otherwise. When transmitting voice over channels, voice usually digitized transmitted companded voice stream. Companding perceptual compression technique which linear data converted non-linear logarithmic form. common standards u-law a-law.
Channel Distribution Serial Interface
Channel distribution refers relaying each channel frame appropriate responsible processing. Framers generally provide this data serial stream that transmitted serial port peripheral C54x. This interface require small amount glue logic provide appropriate clocking interfacing signals. Interfacing framer chip facilitated using Multi-Channel Buffered Serial Port (McBSP) peripheral available TMS320C5410 DSP. This peripheral allows extract given channel channels) from frame programming peripheral with appropriate timeslot framing information. This allows channels broadcast DSPs offers advantage requiring channel distribution logic selective routing. McBSP also allows this broadcast approach used serial transmit direction. During transmit, McBSP only transmits data during responsible channels; otherwise, remains high impedance state. This solves collision problem multiple DSPs writing same time, assuming each programmed appropriately with non-overlapping channels. alternative solution channel distribution more complex logic distribute channels among DSPs using dedicated serial lines. This more complex less flexible alternative.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Using aforementioned approach, host processor manages channel allocation task informing each individual responsible timeslots initialization time. Channels also allocated dynamically appropriately informing each assigned channels during operation. This could employed circumvent problems such nonfunctioning reallocate channels among DSPs optimal resource management. framer provides signaling data each channel separate data stream. manage this signaling data, several methods suggested. Since DSPs generally have direct need process signaling data, signaling lines from/to framer directly routed host serial port, alleviating burden from DSP. Another solution route signaling DSPs same manner data. Since each C54x McBSPs, other serial port allocated signaling data. details depend method used framer chip. Physically connecting C54x serial port framer requires little overhead terms external connections. Three lines required both transmit receive operations:
Bit-rate clock signal Frame sync Serial data line
clock frame sync must synchronized with T1/E1 line clock generally extracted from transceiver chip. Assuming adequate current drive, both transmit receive lines distributed amongst chips bus. further details interfacing C54x serial ports, TMS320C54x Reference Set. diagram transceiver/DSP serial interface shown below Figure
Figure Transceiver Serial Port Interface
Data (Rx/Tx) Glue logic needed) Transciever Clock/Frame Sync
Sigaling (Rx/Tx)
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
System Control
DSP-based systems generally function that host processor (such microcontroller) provides control over subordinate slave DSPs. With respect control, host's responsibilities divided into tasks:
First, host manages system initialization, which downloads code, distributes parameters, allocates resources each processor. Second, during normal operation, host maintains proper functioning system regularly monitoring performance each DSP.
During system initialization, host processor boots first, then prepares initialize DSPs. control DSPs either initialization steady-state system monitoring, host requires mechanism communicate with each individually. peripheral called Host Port Interface (HPI) facilitates this communication link. allows host processor access block internal memory read write accesses. details operation Host Port Interface, TMS320C54x Reference Set. Another requirement host that control reset operation each DSP. This allows host initiate boot process each gives host mechanism restart non-functioning DSP. overview required host/DSP interconnections shown Figure
Figure System Control
Reset Lines
Host Processor
Control (CS,
Address/Data
Several possible methods used efficiently boot initialize multiple DSPs, each with advantages disadvantages. method uses host transfer code each individually. This allows host complete control code distributed each DSP, thus increasing design flexibility. code would reside EPROM which only host would require access.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Another solution provides either EPROM each central EPROM which each access. host would thus initiate control boot process each from appropriate EPROM. boot HPI, host must first download code HPI. This done while reset state. some processors, host only access block memory DSP. Since almost applications larger than boot manager first downloaded. Once removed from reset state, runs from factory-installed boot ROM, which subsequently branches accessible memory (0x1000). host must then transfer application code boot manager HPI. This accessibility limitation will exist future versions peripheral. During both initialization steady state operation, mechanism must provided allow message transfer between host DSPs. also serves this need well. important requirement message transfer deciding efficient well suited protocols, handshaking, message formats. Since used both transmit data packets message traffic, overhead information packet allows packet processor differentiate packets intended data transfer those intended messaging. Details such protocols often proprietary, many based common data transfer protocols such HDLC. handshaking mechanism must also provided indicate packet transfers acknowledgements. C54x several interrupt mechanism this purpose. interrupt initiated host indicates that packet been written memory block. Once read processed packet, acknowledgement must sent indicating that another packet transmitted. must also have mechanism request data message packet transfer host. interrupt host polling mechanism used such service request. Once each been successfully started, role host switches that monitoring proper operation each DSP. This easily accomplished requiring each regularly provide updates system performance host. system problem indicated either ceasing transmit status messages transmitting message indicating poor performance. this point, host either reset restart leave down reallocate resources other DSPs.
Interface Application Software
primary role voice-over-network system bidirectionally convert voice data between continuous data stream packetized data stream. Associated functions this process
Data compression Echo cancellation Network packet delay concealment
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
most optimal solution this system also requires that each multiple-DSP environment also process multiple streams voice. number streams determined primarily speed signal processing algorithms associated overhead, speed processor. example, given that compression algorithm, echo cancellation, overhead processing only require MIPS processing bandwidth, 100-MHz C5410 could process four channels voice with MIPS left overhead, error margin, future expansion.
Operating System
crucial element system processing multiple data streams proper coordination management resources service data. This task management best suited Real Time Operating System (RTOS), such Spectron/TI BIOS. Spectron/TI BIOS provides firmware kernel task management, analysis, trace functions with very little memory overhead words). first step adapting software application BIOS structure application into various modules threads. example, echo canceller vocoder should allocated different threads. fact, vocoder further split into coding decoding functions. Depending processing time required block, further partitioning might necessary task scheduler optimally manage tasks. BIOS manages execution these threads prioritized, pre-emptive scheduling. This requires that programmer assign each thread appropriate priority such that task executing task higher priority scheduled execution, lower priority task interrupted preempted. application interfaces BIOS kernel functions BIOS API, which provides standard environment development integration. following list additional features offered BIOS environment
Periodic Functions-BIOS also allows tasks scheduled based system clock. This allows functions such watchdog tasks executed periodically. Stream Manager-DSP BIOS provides means data transfer, data pipes host transfers. Data pipes manage data transfers providing buffering, notification, software data structures. Transfers occur between threads mechanism transferring data on/off chip peripheral. host transfer form pipe which pipe managed host. This used send receive data streams from host computer. also aids simulations external (peripheral) data transfers during development sending data host. Instrumentation Manager-The instrumentation provided BIOS allows realtime monitoring system functions with minimal intrusion application. available instrumentation includes logging, statistics accumulation, event monitoring. Logging allows capturing information about events provides means programs send messages host. statistics accumulator captures information (count, max, total) variables. event monitor allows programmer trace execution threads during system run-time. This provides easy means find real-time bugs, such priority problems, MIPS issues. Configuration Tool-The Configuration tool provides visual editor creating system objects such signals, streams, event logs, etc. also allows programmer system properties.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
operating system also designed minimum system resources such processing time memory. instance, kernel only uses less than words program space, modularized only link libraries required applications, instrumentation data formatted host rather than DSP.
Signal Processing Algorithms
major goals application software voice-over-network system threefold:
compress data travelling across network minimize bandwidth maximize channels enhance voice quality transform data from continuous stream packets vice versa
Other possible tasks include those associated with handling data addition voice traffic, such modem transmissions. data transmissions, must switch voice coding echo cancellation since these perceptual voice algorithms would corrupt data. element this process detection traffic DSP. traffic delineated from voice stream specific tones protocols injected voice stream. Consequently, must constantly probe these signals. block diagram elements involved voice processing shown Figure Figure
Figure Voice Encoder Block Diagram (Ingress)
Echo Canceller Speech Coder
Silence Processor
Companded Linear Conversion
Packetizer
Figure Voice Decoder Block Diagram (Egress)
Decoder
Compander Comfort Noise Generator
Jitter Buffer
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Voice Coding
Voice coding, known vocoding, provides means increase call channel density system compressing voice data. Many vocoders vocoder implementations exist. Choosing appropriate depends trade-offs between compression, processing requirements, resultant voice quality. Table lists common vocoders used voice-over-network systems their characteristics.
Table Vocoder Formats
Vocoder Standard G.726 ADPCM G.728 LD-CELP G.729 CS-ACELP Rates (kbps) 12.8, Notes MIPS efficient, voice quality degrades rapidly lower rates Better voice quality lower rates higher compress, less MIPS efficient Best compression, least efficient
Another bandwidth optimization technique commonly used voice activity detection (VAD). This technique determines whether channel currently transmitting voice silence based energy input signal. Since speech, voice activity, only comprises approximately average voice call, remaining wastes bandwidth since useful information transferred. Consequently, when speech inactivity, silence, detected, algorithm only sends indication that current frame silent instead actual coded waveform representation. receiver subsequently inserts approximation background noise called comfort noise during these periods.
Echo Cancellation
Echoes voice network caused signal reflections, usually from several sources primarily from boundaries where hybrid circuits exist. These hybrid circuits convert from four-wire dual half-duplex systems two-wire full duplex, thus minimizing wire costs. resultant reflections take form audible copies speaker's voice delayed perceivable time. Echoes always exist voice networks-it only echoes delayed large amount time that become annoying. fact, most people find total absence echo somewhat annoying associate small amount echo with active telephone line. Echo cancellation process which these delayed echoes removed. most common technique used adaptive filtering, which processor determines characteristics waveform voice line, then uses this information configure adapt filter cancel same voice opposite direction (the echo). metric used compare these algorithms amount echo cancelled length filter, which impacts maximum echo delay that algorithm cancel.
Jitter Buffers
Network congestion cause variations delay between packets cells information transmitted over network. This delay variance known jitter. Since voice very delay sensitive, even small amounts jitter interrupt voice conversation. this reason, voice traffic historically never been accepted suitable transmission across highly congested connectionless data networks.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
common solution this variability create buffer that first primed certain amount data depending amount variation expected. voice rate dictates timely removal data from buffer, data input rate follows variable rate network. that data stored buffer absorbs variability input. However, tradeoff delay incurred buffering certain amount voice data. variables, such jitter buffer size, must determined statistical monitoring network channel. Monitoring buffer overrun underrun used dynamically reconfigure these parameters based current network delays.
Task Allocation
discussion assumed thus that each system performs same operations essentially interchangeable their roles. This solution both advantages disadvantages. primary advantage system design control. Since each performs identical roles, each loaded with same software interconnected with same configuration. system controller does need differentiate between different tasks different DSPs. major disadvantage, however, software size. Since each must perform system tasks including voice coding, voice decoding, echo cancellation, software each must reside memory. This optimal solution software does internal memory, resulting extra board space external time consuming offchip accesses. such distributed system, different DSPs would responsible different tasks data path. example, tasks could divided between dedicated echo canceller DSPs voice coding/decoding DSPs. purely dedicated approach would allocate processors echo cancellation, voice coding, voice decoding. This type configuration offers advantage allowing software reused each channel within processor. However, since processing stream data involves several DSPs, data must transferred between them. Consequently, this process requires longer delay additional overhead required interprocessor communication. Figure shows possible configuration such distributed approach.
Figure Distributed Software Configuration
Coder Decoder Echo cancelle
Network
Coder Decoder
efficiently optimize distributed system, processing blocks divided unevenly, shown Figure Since echo canceller algorithm generally requires less MIPS real-time processing than vocoder, echo canceller process more channels given time than vocoder. result, distribution tasks vary depending algorithm implementation speeds.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Network Interface
network interface block performs tasks sending packetized voice/data from network physical layer receiving data from network delivering DSP. details this process depend type network interface used. most common networks used such systems
A
AFrame Relay
Much work been done marriage voice traffic ATM. Several forums have been created, most notably VTOA (Voice Telephony Over ATM), address implementation interoperability requirements such systems. structure well suited transmission voice traffic small data packets, known cells. fact, Awas designed transmit voice data. Small uniformly sized cells provide advantage smaller, more predictable delays, which essential transmission voice traffic. Cell-based traffic also meshes well with bursty nature voice. However, advantages that small cells provide voice traffic result disadvantages data traffic, since smaller cells subsequently result higher overhead data ratio. layers network model applicable this discussion Aare Adaptation layer Physical layer. AAdaptation Layers (AAL) provide efficient transmission packets various types. Type specifically intended packet voice video applications designed efficiently support lowrate, short, variable length packets delay sensitive applications. layer also subdivided into parts:
Common Part Sublayer (CPS) Service Specific Convergence Sublayer (SSCS)
SSCS layer specifies packet formats procedures encode various types information streams efficient transport. other words, this layer cognizant type information being communicated. fact, voice/data system, viewed being part signal-processing block. Layer closer physical layer thus responsibility transmitting packet versus packet information. implementation Ainterface includes following tasks:
Packetization depacketization voice data into properly formatted data units (PDUs) Multiplexing these PDUs Segmentation Reassembly processor Physical layer Acell interface
These tasks also shown Figure
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Figure AInterface Block Diagram
Host Port Host Port Host Port
logic
Segmentation Reassembly
Physical Layer Network Interface
Network
Frame Relay
Frame relay another popular network switching technology used transmit voice data. Frame relay based X.25 protocol with several modifications resulting higher performance greater efficiency. example, frame relay does employ time-consuming data-correction techniques, does X.25, leaving this higher layers. voice communications, main differences between frame relay ATMbased transmissions data formatting service quality. Acommunication based small, fixed length packets known cells data transmission, whereas frame relay utilizes variable length packets. Since small packets provide several advantages when transmitting voice, frame relay systems generally fragment voice packets into small cell-like packets. Small packets statistically yield better network service reducing network jitter delay. Also, perceptual consequences dropping small packets smaller than larger packets. Another issue encountered transmitting voice over frame relay systems variable nature data packets sharing network. Since data transmissions generally utilize larger packet lengths efficiency, delays incurred voice packets vary widely. This impacts required real-time operation voice traffic. Consequently, Aprotocol created solve network issues related incompatibility frame relay various traffic types such voice video.
next task specifying multiprocessor system create mechanism which DSPs share access common logic device, such microprocessor ASIC. provides this shared communication link granting systems connected access based either master mutually understood access rules.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Each connects ultimately controller device Host Port Interface (HPI). Essentially, host buffers multiplexes data streams from each provides interface network controller. also format data packets affix additional header information routing error control. Several issues must addressed when creating bus, including device configuration issues, addressing arbitration, service requests, circuit loading issues. Figure shows overview general-purpose implementation such using HPI.
Figure Host/HPI Interface
data/addr
Host Port Select lines
Host Port
Host Controller
Host Port control
voice-over-packet system, most appropriate configuration assigns DSPs slaves controller device master. Since systems connected common physical line, each must transmit appropriate times avoid contentions. Efficiently distributing accesses among DSPs role master. First, host must employ either mechanism device addressing means which host controller selects communicates with each individual device bus. fastest solution connects controller with each individual select line. Chip Select line (HCS) serves this purpose. This allows specific DSPs accessed controller simply enabling line appropriate DSP. host data writes, this method allows controller target individual DSPs broadcast multiple DSPs. Such approach requires that host have access each select line. small numbers DSPs, either connecting select lines GPIO pins memory mapped register works well. number DSPs becomes large, number select lines render this approach unfeasible, which case address decode logic required. This method offers advantage software overhead required manage bus. disadvantage, however small, additional overhead physically supplying routing chip selects each DSP.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
Another solution device addressing leave address decodes DSP. host select communication, must first send address over select appropriate DSP. Each subsequently decodes address determines upcoming data intended then proceeds appropriate. disadvantage this method software complexity. Each must service these interrupts decode address every access, thus wasting MIPS. This method offers advantages versatility physical simplicity that none DSPs need have individual connections-all connections distributed. Adding additional DSPs this solution becomes trivial since hardware configuration required. quick versatile expandability requirement, this best solution. next issue arises when requests delivery packet host. Given that each expected regularly transmit packets with equal frequency would expected busy, evenly distributed system, appropriate solution host process DSPs round robin polling fashion. Each would indicate service request setting flag accessible host HPI, which host would routinely poll. packet exists transmit, host processes not, continues next processor. Another solution DSPs actively request service host controller, requiring dedicated interrupt line each DSP. This method more appropriate situation which only subset DSPs generally expected require service, thus requiring host waste time polling DSPs that normally idle. loading another issue note. Each device that connects creates capacitive current load. many devices connected, this load requires more time charge, thus causing significant delays transmissions. Each also limits current drive, limiting this charging time. Consequently, devices added bus, drivers transceivers required depending individual loading characteristics number devices present bus. This presents trade-off decision since additional logic such drivers transceivers also create delays.
Conclusion
Designing multiprocessor platform presents many challenges including, limited system control, data path architectures, software design. With large software base, tools, flexible peripheral options C54x family, these challenges become tractable ultimately superior solutions.
Designing Multiprocessor C54x Platform Voice-Over-Network Applications
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Designing Multiprocessor C54x Platform Voice-Over-Network Applications
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Designing Multiprocessor C54x Platform Voice-Over-Network Applications
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