Veikko Koivumaa Digital Signal Processoring Solutions Abstract

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Interfacing TMS320C57S Host Port Interface 80386EX Host Processor
Veikko Koivumaa Digital Signal Processoring Solutions
Abstract
This document discusses connect Intel 80386EX processor Texas Instruments TMS320C57S Host Port Interface. TMS320C57S Host Port Interface (HPI) 8-bit parallel port used interface host processor 16-bit word structure 'C5x DSP. Using this port, host must always read/write consecutive bytes. 386EX processor input signal BS8_ indicate that external device 8-bit device. signal this line allows 16-bit accesses from 8-bit processor executed consecutive bytes through data bits D7:D0.
Contents
Design Problem.2 Solution.2
Figures
Figure Block Diagram Hardware Interface
Digital Signal Processing Solutions
December 1998
Design Problem
connect Intel 80386EX processor TMS320C57S Host Port Interface?
Solution
Host Port Interface (HPI) 8-bit parallel port used interface host processor 16-bit word structure 'C5x DSP. Using this port, host must always read/write consecutive bytes. 386EX processor input signal BS8_ indicate that external device 8-bit device. signal this line allows 16-bit accesses from 8-bit processor executed consecutive bytes through data bits D7:D0. From 386EX address space need only lines (A2, specify where access HPI: Control Register, Address Register, Data Register (with automatic address modify not). 386EX internal decoder place external devices address space. Here CS0_ used decoded addresses. also space 386EX. block diagram hardware interface shown Figure external clock 386EX 50MHz (CLK2). This divided internally 25MHz (40ns) CPU. make external read/write cycles 80ns. speed `C57S Host Only Mode (HOM) cycles cycles Shared Access Mode (SAM). This means access times 50ns 125ns with 80MHz external clock (40MHz/25ns). operation, must READY_ line insert Wait State 386EX (one means 40ns).
Figure Block Diagram Hardware Interface
80386EX-25
TMS320C57S-80
D7:0
BLE_ W/R_ CS0_ READY_ INT0 BS8_
HD7:0
HCNTL1 HCNTL0 HBIL HRW_ HDS2_ HDS1_ HCS_ HRDY HINT_
HAS_
Interfacing TMS320C57S Host Port Interface 80386EX Host Processor
Software Considerations
When host accessing first time, must perform following sequence: Write HPIC register `BOB' (upper lower bytes must same) Write address HPIA -registers
After this host read write data registers. When RESET mode, automatically mode. This makes flexible enough take control reset line (RS_) host. Also, want save power, host should take control clock. (These options included Figure mode host must synchronize clock. This means maximum delay clock cycle. Host priority memory accessing block same cycle. want boot from HPI, connect HINT_ INT3_ DSP. bootloader program will verify this done transfer then program control start address (8800h program space). Host interrupt vector address 0018h. location IMR/IFR register control register (HPIC) address 500h data memory. memory block following addresses: program space data space 8800h 8FFFh 1000h 17FFh (disabled RAM=0) (disabled OVLY=0).
must take care following:
OVLY bits must after reset. When SMODE written from HOM, next instruction must NOP. When SMODE written from SAM, next instruction allowed read block
host processor execute pre-programmed tasks remapping interrupt vector table program space memory block (8800h). host needs write task address address 0019h memory before interrupt DSP.
Interfacing TMS320C57S Host Port Interface 80386EX Host Processor
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Interfacing TMS320C57S Host Port Interface 80386EX Host Processor

Veikko Koivumaa Digital Signal Processoring Solutions Abstract

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