Jacqui Jackson Mark Mattson ABSTRACT TMS320VC5410 high perfo

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Jacqui Jackson Mark Mattson ABSTRACT TMS320VC5410 high perfo

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Introduction TMS320VC5410
Jacqui Jackson Mark Mattson
ABSTRACT
TMS320VC5410 high performance, highly integrated member TI's growing 'C54x product line. 'VC5410 delivers MIPS performance with 2.5V core power supply (I/O voltage remains 3.3V). 'VC5410 devices provide words on-chip SRAM, words on-chip ROM, multi-channel buffered serial ports, host port interface, timer. 'C5410 developed service variety end-equipment wireless wireline communications market that require high performance, very power dissipation, small physical size.
Contents
TMS320C54x Architectural Overview TMS320C54x Applications. Power Dissipation
Figures
Figure Figure Figure Figure Figure Figure TMS320C5410 Increasing 0n-chip Integration. TMS320VC5410 On-chip Memory TMS320VC5410 On-chip Memory Peripherals: McBSP Peripherals: Receive Data Sort
Digital Signal Processing Solutions
July 1998
TMS320C54x Architectural Overview
TMS320C54x offers some most efficient MIPS industry with higher quality MIPS relation other 16-bit DSPs comparable MIPS efficiency 24-bit instruction DSPs. There several reasons behind this. combination enhanced Harvard architecture, parallel structure, optimized core empowers sophisticated instruction set, with many single cycle parallel instructions. Parallelism readily evident inspection 'C54x internal hardware. employs non-pipelined (multiply accumulate) unit with 17x17 multiplier dedicated adder. addition, 40-bit perform various arithmetic manipulation functions with output connected dual 40-bit accumulators. general, multiple accumulators contribute improved coding efficiency avoiding storage intermediate results memory. More importantly though, particular advantage this feature made several signal processing instructions which accumulators function destination registers concurrent operations. example, square distance instruction (SQDST) uses accumulator destination vector difference calculation while accumulator keeps running prior differences. Equally important parallelism having bandwidth support multiple memory operands. 'C54x sets internal buses which support program fetch, data memory reads, data memory write single cycle. Other core highlights include: Split mode which facilitates single cycle dual 16-bit sums (this feature extremely useful Viterbi decoder butterfly calculations). exponent detector which allows single cycle exponent encoding single cycle mantissa normalization (this feature useful many vocoder applications). Non-pipelined unit supporting single cycle 17-bit unsigned 16-bit signed multiplication with without rounding (rounding feature advantageous applications). General purpose Compare, Select Store Unit facilitate Viterbi channel decode MLSE equalization butterfly calculations Software stack implemented Stack Pointer register (SP) Industry's most efficient fixed-point Compiler used speed development less time critical functions. Extensive interrupt support form prioritized external interrupts, non-maskable interrupt, reset interrupt. Interrupt processing
Introduction TMS320VC5410
directed software interrupt vector table interrupts nested depth.
Figure shows block diagram TMS320VC5410
'C5410: Increasing on-chip integration
TMS320VC5410
Memory
Program Prog /Data
Peripherals
JTAG TEST/EMU Multi-Channel Buffered Serial Ports
TMS320C54x MIPS Core Voltage: 2.5V Single Access On-chip with boot code words on-chip SRAM consisting Dual Access On-chip
17*17 Adder RND,
CMPS Operator (Viterbi Encoder
Serial Port
Timer
Shifter
Barrel [-16,
Accumulators
Software Programmable Waitstate Generator
Addressing Unit
Auxilliary Registers Addressing Units Host Port Interface
Program/Data Single Access On-chip Program/Data Multi-Channel Buffered Serial Ports Host Port Interface controller Timer Extended Program Addressing Software Programmable Active Mode Power Dissipation JTAG with Boundary Scan 144-pin TQFP u*BGA; footprint compatible with (with 144-pin TQFP)
'VC5410 2.5V very high performance 16-bit DSPs with large integration on-chip memory peripherals. from figure 'VC5410 words on-chip RAM. words this dual-access (broken into four word blocks) words single-access (broken into seven word blocks). This memory integration, conjunction with advanced busing structure, allows accesses cycle. following diagrams display just couple numerous possibilities 'C5410 architecture. Blocks 1,2,3, each support accesses single instruction cycle. Blocks 5,6, word blocks that allow access instruction cycle.
Introduction TMS320VC5410
Figure
'VC5410 On-chip Memory
accesses cycle
Example Dual-Access Single-Access
Block
Busing structure program bus, data buses, write bus)
Figure
words total on-chip program fetch from block data reads from block data write into block
'VC5410 On-chip Memory
accesses cycle
Example Dual-Access Single-Access
Block
Busing structure program bus, data buses, write bus)
words total on-chip program fetch from block data read from block data read from block data write into block
previous examples only couple possibilities utilizing onchip memory 'VC5410. important note from busing memory examples above that 'VC5410 does suffer from bandwidth problems that would affect many other architectures. this point, this document shown core architecture 'C54x, busing structure, large on-chip memory collaborate enable '5410's high quality MIPS. discussion MIPS quality would
Introduction TMS320VC5410
complete without inclusion peripheral set. 'VC5410 peripherals also greatly enhance MIPS quality.
Figure
Peripherals: McBSP
CLKX CLKR CLKS
EXPAND
COMPRESS
SPCR
CLOCK FRAME SYNC CONTROL
SRGR
MULTI-CHANNEL SELECTION
RINT XINT REVT XEVT
TMS320VC5410 three multi-channel buffered serial ports (McBSPs). diagram above describes components three McBSPs. Each McBSP provides direct communication with T1/E1 framers, serial converters, codecs, other serial devices with minimal hardware requirements. McBSP high speed, full-duplex, serial port interface that offers programmable frame generation, internal clock, polarity both frame synchronization data clocks. Multichannel selection gives McBSP capability transmit receive channels. Because McBSP access data, program, memory spaces, data directly written read from memory. This provides increased flexibility, improved data rates, unburdened CPU. McBSP contains on-chip companding hardware feature that allows compression expansion data either A-law u-law formats. result, code size reduced having reference look-up tables perform companding equations software. throughput McBSP Mbits/sec 'VC5410 running MIPS. Because McBSP operates independently CPU, actually placed into IDLE mode while McBSP continues operate spool data into on-chip memory.
Introduction TMS320VC5410
PERIPHERAL
INTERRUPTS SYNCRONIZATION EVENTS
Peripherals:
DMPRE DMSBA DMSAI DMSRC DMDST DMCTR DMSEFC DMMCR DMSRCP DMDSTP DMIDX DMFRI DMGSB DMGDA DMGCR DMGFR
Figure
'LC5410 Direct Memory Access (DMA) controller allows movements data between internal program data memory, internal peripherals (e.g. McBSP), external memory devices occur without intervention CPU. With independent programmable channels, ability keep track contexts independent block transfers. Host Port Interface (HPI) line parallel that used interface host processor (for example microcontroller). allows information exchanged between device host processor throughout entire on-chip memory. extended on-chip program memory also accessible host DSP. operate modes: shared access mode (SAM) host-only mode (HOM). mode, both host 'VC5410 access memory with asynchronous host accesses being resynchronized internally. conflict occurs, will wait. this mode, transfer rate Mbits/sec Mbytes/sec). mode, transfer rate Mbits/sec Mbytes/sec). Other peripherals 'VC5410: Standard 16-bit timer
Introduction TMS320VC5410
Wait State Generator: extends external cycles fully software programmable order interface slower external memories Phase Locked Loop (PLL): allows 'VC5410 operate high on-chip frequency with lower external frequency clock. software programmable different multiplier options ranging from x1/4 x15.
Applications:
useful segmenting applications 'VC5410 look three basic types:
'C54x Application Types
Single channel //high performance: Single channel high performance: single high performance algorithm single high performance algorithm application (e.g. 40-50 MIPS algo application (e.g. 40-50 MIPS algorithm MIPS DSP) MIPS DSP) Channel stacking: ability Channel stacking: ability more "channels" particular algorithm more "channels" particular algorithm (e.g. channels DTMF) (e.g. channels DTMF) Function stacking: ability absorb Function stacking: ability absorb functionality multiple dedicated functionality multiple dedicated processors ASICs into (e.g. processors ASICs into (e.g. does fax, data modem, telephony, does fax, data modem, telephony, audio algorithms simultaneously) audio algorithms simultaneously)
Often times, processor's MIPS numbers represent "peak" performance. This performance processor given that buses used adequately, instructions operands correct memory locations, slower off-chip accesses minimized. instances contention, memory bottlenecks, ineffectual external accesses serve decrease processor's quoted "peak" MIPS number. resulting MIPS number becomes more realistic measure processor's "sustained" performance. Because very high quality MIPS 'VC5410, "peak" performance MIPS numbers "sustained" performance MIPS numbers nearly identical. This makes 'VC5410 excellent performance enabling applications. These applications where increased MIPS, larger amounts on-chip memory, intelligent peripherals necessary handle high performance applications wireless wireline communications segments.
Introduction TMS320VC5410
Channel stacking concept adding more "channels" particular algorithm that previously performed multiple processors. Server line cards telecom switching equipment examples where many channels relatively simple algorithms (DTMF, echo cancellations, level fax/modem code, etc.) handled single 'VC5410. Function stacking system-cost reducing concept combining functionality algorithms performed multiple dedicated processors ASICs into single high performance, heavily integrated DSP, like 'VC5410. Some applications "fixed-function" processors that cost-effective handling dedicated function. However, when several these processors used conjunction with ASICs FPGAs, starts make sense integrate these into single, high-performance 'VC5410 that MIPS on-chip memory accommodate total application. end-result decrease board size, component cost, system power. `VC5410's added features makes tremendous difference applications. Because added on-chip memory, power consumption dramatically reduced. This additional memory decrease power will allow least channels G.723.1 VoIP media stream signal processing executed single MIPS `VC5410. 5410's McBSP A-bis interface that useful transporting data between Base station Transceiver Station (BTS) Base Station Controller (BSC) infrastructures. contains registers that handle data-sorting function data streams like T1/E1. figure below shows example data sorting data stream.
Introduction TMS320VC5410
Receive Data Sort
DARAM DARAM DARAM DARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM
MCBSP
FRAME CHANNELS 1-24
FRAME CHANNELS 1-24
CHANNEL FRAME CHANNEL FRAME
CLOCK FRAME SYNC
MULTICHANNEL SELECTION
SYNC EVENTS
CHANNEL FRAME
INTERRUPTS
Figure
'VC5410 address lines which allow address range program space. This enables many code modules algorithms stored low-cost, external, 8-bit EPROM. Different segments code stored into words on-chip SRAM executed full-speed processor. This "reconfigurable" concept useful applications that require multiple algorithms that must zero wait-state. Algorithms loaded into on-chip memory when needed discarded when becomes necessary next algorithm loaded on-chip.
Power Dissipation
important design considerations 'VC5410 power dissipation. result, there multiple power reducing features 'VC5410. Several these listed below:
Introduction TMS320VC5410
MECHANISMS LOWER POWER DISSIPATION 'C54x
Keepers Holders maintain state ext. External control disables external Static design lower clock IDLE modes drop into various power down modes options 'C5410)-use lower system clock MIPS efficiency fewer MIPS enables
Active Core Power 'LC54x devices average, mA/MIPS while mA/MIPS 'VC54x devices.
'C54x incorporates power down modes within architecture: IDLE1, IDLE2, IDLE3. These decrease power consumption when processing. power down modes have different degrees power savings: IDLE1: core shutdown, peripherals still active, 7.93 3V/66MIPS IDLE2: core peripherals shutdown, still active, 3V/66MIPS IDLE3: complete shutdown, 3V/66MIPS
graphic shows, 'VC5410 devices exhibit, average, mA/MIPS active core supply power. However, true measure power dissipation also takes into account processor's quality MIPS.
Introduction TMS320VC5410
algorith voltage
algorithm
typical power dissipation 'VC5410 using on-chip resources (CPU onchip memory) mA/MIPS MIPS 2.5V= 112.5 function more accurate measurement? mA/MIPS itself disregards processor's quality MIPS supply voltage DSP's power dissipation while performing actual application algorithm most accurate measurement complete given task fewer MIPS than another DSP, then into IDLE mode sooner, thus lowering power dissipation even further. 'VC5410 operates with dual power supply achieve superior power performance. internal logic, including peripheral logic, supplied with 2.5V, while external logic supplied with 3.3V. dual-power supply allows 'VC5410 maintain high performance MIPS, while achieving lowest power dissipation possible. Overall, 'VC5410 high performance, large on-chip memory, highly integrated peripheral meet needs wide variety wireless wireline, data voice, communications systems. addition, quality available MIPS ultra power dissipation make 'VC5410 compelling choice ever demanding requirements these systems.
Introduction TMS320VC5410
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IMPORTANT NOTICE
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain application using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. Copyright 1998, Texas Instruments Incorporated trademark Texas Instruments Incorporated. Other brands names property their respective owners.
Introduction TMS320VC5410

Jacqui Jackson Mark Mattson ABSTRACT TMS320VC5410 high perfo

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