Jacqui Jackson Mark Mattson ABSTRACT TMS320LC549 TMS320VC549
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Introduction TMS320LC549/TMS320VC549
Jacqui Jackson Mark Mattson
ABSTRACT
TMS320LC549 TMS320VC549 high performance, highly integrated members TI's growing 'C54x product line. 'LC549 delivers MIPS performance with 3.3V core power supply. 'VC549 offers MIPS performance with 2.5V core power supply (I/O voltage remains 3.3V). 'C5491 devices provide words on-chip SRAM, words on-chip ROM, serial ports, host port interface, timer. 'C549 developed service variety end-equipment wireless wireline communications market that require high performance, very power dissipation, small physical size.
Contents
TMS320C54x Architectural Overview Peripherals: Peripherals: HPI. TMS320C54x Application Types Power Dissipation
Figures
Figure Figure Figure Figure Figure Block Diagram TMS320LC549/TMS320VC549 TMS320LC549/TMS320VC549 On-chip Memory TMS320LC549/TMS320VC549 On-chip Memory Peripherals: Peripherals:
'C549 will designate reference both 'LC549 'VC549 DSPs. 'LC549 'VC549 will used only when specific reference each necessary.
Digital Signal Processing Solutions
July 1998
TMS320C54x Architectural Overview
TMS320C54x offers some most efficient MIPS industry with higher quality MIPS relation other 16-bit DSPs comparable MIPS efficiency 24-bit instruction DSPs. There several reasons behind this. combination enhanced Harvard architecture, parallel structure, optimized core empowers sophisticated instruction set, with many single cycle parallel instructions. Parallelism readily evident inspection 'C54x internal hardware. employs non-pipelined (multiply accumulate) unit with 17x17 multiplier dedicated adder. addition, 40-bit perform various arithmetic manipulation functions with output connected dual 40-bit accumulators. general, multiple accumulators contribute improved coding efficiency avoiding storage intermediate results memory. More importantly though, particular advantage this feature made several signal processing instructions which accumulators function destination registers concurrent operations. example, square distance instruction (SQDST) uses accumulator destination vector difference calculation while accumulator keeps running prior differences. Equally important parallelism having bandwidth support multiple memory operands. 'C54x sets internal buses which support program fetch, data memory reads, data memory write single cycle. Other core highlights include: Split mode which facilitates single cycle dual 16-bit sums (this feature extremely useful Viterbi decoder butterfly calculations). exponent detector which allows single cycle exponent encoding single cycle mantissa normalization (this feature useful many vocoder applications). Non-pipelined unit supporting single cycle 17-bit unsigned 16-bit signed multiplication with without rounding (rounding feature advantageous applications). General purpose Compare, Select Store Unit facilitate Viterbi channel decode MLSE equalization buttefly calculations. Software stack implemented Stack Pointer register (SP). Industry's most efficient fixed-point Compiler used speed development less time critical functions. Extensive interrupt support form prioritized external interrupts, non-maskable interrupt, reset interrupt. Interrupt processing
Introduction TMS320LC549/TMS320VC549
directed software interrupt vector table interrupts nested depth.
Figure shows block diagram TMS320LC549/VC549.
'C549: Power Efficient Performance
TMS320LC549 VC549
Memory
Program Prog/Data
Peripherals
JTAG TEST/EMU Buffered Serial Port Serial Port Timer Waitstate Generator Clock Generator Software Programmable Host Port Interface
17*17 Adder RND,
CMPS Operator (Viterbi Encoder
Shifter
Barrel [-16,
Accumulators
Addressing Unit
Auxilliary Registers Addressing Units
TMS320C54x 66/80/100 MIPS 66/80 MIPS performance 3.3V ('LC549) MIPS performance 2.5V ('VC549) words on-chip SRAM consisting Dual Access On-chip Program/Data Single Access On-chip Program/Data Single Access On-chip with boot code Auto-Buffered Serial Ports Serial Port Host Port Interface Timer Extended Addressing Software programmable Active Power Dissipation JTAG with Boundary Scan TQFP (Thin Quad Flat Pack) 144BGA (Ball Grid Array) ;footprint compatible with 'C542 'C548
'LC549 3.3V 'VC549 2.5V very high performance 16-bit DSPs with large integration on-chip memory peripherals. from figure 'LC549 words on-chip RAM. words on-chip dual-access (broken into four word blocks) words single-access (broken into three word blocks). This memory integration, conjunction with advanced busing structure, allow accesses cycle. following diagrams display just couple numerous possibilities 'C549 architecture. Blocks 1,2,3, each support accesses single instruction cycle. Blocks 5,6, word blocks which allow access instruction cycle.
Introduction TMS320LC549/TMS320VC549
Figure
'LC549/'VC549 On-chip Memory
accesses cycle
Example Dual-Access Single-Access
Block
Busing structure program bus, data buses, write bus)
Figure
words total on-chip program fetch from block data reads from block data write into block
'LC549/'VC549 On-chip Memory
accesses cycle
Example Dual-Access Single-Access
Block
Busing structure program bus, data buses, write bus)
words total on-chip program fetch from block data read from block data read from block data write into block
previous examples only couple possibilities utilizing onchip memory 'C549. important note from busing memory examples above that 'C549 does suffer from bandwidth problems that would affect many other architectures. this point, this document shown core architecture 'C54x, busing structure, large on-chip memory collaborate enable 'C549 high quality MIPS. discussion MIPS quality would complete
Introduction TMS320LC549/TMS320VC549
without inclusion peripheral set. 'C549 peripherals also greatly enhance MIPS quality.
Figure
Peripherals:
Auto-Buffered Serial Port
P/C/D/E BUSES
CLKX
Read
Write
CLKR
Superset serial port High speed data transfers Reduced interrupt latencies Read Write words burdened
'LC549/'VC549
TMS320C549 buffered serial ports (BSPs). diagram above demonstrates operation BSPs. Each provides direct communication with serial converters, codecs, other serial devices with minimal hardware requirements. acts like dedicated channel. Both 'C549 BSPs have extra feature which allows detection word misalignment buffers. full-duplex, double-buffered serial port interface with autobuffering unit (ABU). autobuffering unit circular addressing registers with corresponding address generation units. word blocks on-chip dedicated shared with) BSP. result, data directly written ready from memory. This provides increased flexibility, improved data rates, unburdened CPU. word buffer accessed same time dual-access nature on-chip RAM. throughput Mbits/sec 'C549 running MIPS. Because operates independently CPU, actually placed into IDLE mode while continues operate spool data into on-chip memory.
Introduction TMS320LC549/TMS320VC549
Figure
Peripherals:
Host Port Interface
P/C/D/E BUSES
parallel port Interfacing
Read
Shared DARAM word memory
Write
mode: MBps mode: MBps IDLE2
control
'LC549/'VC549
Host Port Interface (HPI) used interface host processor (for example microcontroller). line parallel adjoining word memory block external device. Similar BSP, dedicated into on-chip memory operate independent CPU. this sense, another dedicated channel. operate modes: shared access mode (SAM) host-only mode (HOM). mode, both host 'C549 access memory with asynchronous host accesses being resynchronized internally. conflict occurs, will wait. this mode, transfer rate Mbits/sec Mbytes/sec). mode, host unimpeded access word memory block different block than used BSP) input data while IDLE state. transfer rate Mbits/sec Mbytes/sec). Other peripherals 'C549: (Time Division Multiplexed) serial port configured standard serial port where transfer rate clockout multi-processing mode. Multi-processing achieved splitting time frame into segments. This allows 'C549 interface many other 'C54x devices. Standard 16-bit timer Wait State Generator extends external cycles fully software programmable order interface slower external memories
Introduction TMS320LC549/TMS320VC549
Phase Locked Loop (PLL): allows 'C549 operate high onchip frequency with lower external frequency clock. software programmable different multiplier options ranging from x1/4 x15.
Applications:
useful segmenting applications 'C549 look three basic types:
'C54x Application Types
Single channel //high performance: Single channel high performance: single high performance algorithm single high performance algorithm application (e.g. 40-50 MIPS algo application (e.g. 40-50 MIPS algorithm MIPS DSP) MIPS DSP) Channel stacking: ability Channel stacking: ability more "channels" particular algorithm more "channels" particular algorithm (e.g. channels DTMF) (e.g. channels DTMF) Function stacking: ability absorb Function stacking: ability absorb functionality multiple dedicated functionality multiple dedicated processors ASICs into (e.g. processors ASICs into (e.g. does fax, data modem, telephony, does fax, data modem, telephony, audio algorithms simultaneously) audio algorithms simultaneously)
Often times, processor's MIPS numbers represent "peak" performance. This performance processor given that buses used adequately, instructions operands correct memory locations, slower off-chip accesses minimized. instances contention, memory bottlenecks, ineffectual external accesses serve decrease processor's quoted "peak" MIPS number. resulting number MIPS becomes more realistic measure processor's "sustained" performance. Because very high quality MIPS 'C549, "peak" performance MIPS numbers "sustained" performance MIPS numbers nearly identical. This makes 'C549 excellent performance-enabling applications. These applications where increased MIPS, larger amounts on-chip memory, intelligent peripherals necessary handle high performance applications wireless wireline communications segments. Channel stacking concept adding more "channels" particular algorithm that previously performed multiple processors. Server line cards
Introduction TMS320LC549/TMS320VC549
telecom switching equipment examples where many channels relatively simple algorithms (DTMF, echo cancellations, level fax/modem code, etc.) handled single 'C549. Function stacking system-cost reducing concept combining functionality algorithms performed multiple dedicated processors ASICs into single high performance, heavily integrated DSP, like 'C549. Some applications "fixed-function" processors that cost-effective handling dedicated function. However, when several these processors used conjunction with ASICs FPGAs, starts make sense integrate these into single, high-performance 'C549 that MIPS on-chip memory accommodate total application. end-result decrease board size, component cost, system power. 'C549 address lines which allow address range program space. This enables many code modules algorithms stored low-cost, external, 8-bit EPROM. Different segments code stored into words on-chip SRAM executed full-speed processor. This "reconfigurable" concept useful applications that require multiple algorithms that must zero wait-state. Algorithms loaded into on-chip memory when needed discarded when becomes necessary next algorithm loaded on-chip.
Power Dissipation:
important design considerations 'C549 power dissipation. result, there multiple power reducing features 'C549. Several these listed below:
Introduction TMS320LC549/TMS320VC549
MECHANISMS LOWER POWER DISSIPATION 'C54x
Keepers Holders maintain state ext. External control disables external Static design lower clock IDLE modes drop into various power down modes options C549)-use lower system clock MIPS efficiency fewer MIPS enables
Active Core Power LC54x devices average, mA/MIPS while mA/MIPS VC54x devices.
'C54x incorporates power down modes within architecture: IDLE1, IDLE2, IDLE3. These decrease power consumption when processing. power down modes have different degrees power savings: IDLE1: core shutdown, peripherals still active, 7.93 3V/66MIPS IDLE2: core peripherals shutdown, still active, 3V/66MIPS IDLE3: complete shutdown, 3V/66MIPS
Introduction TMS320LC549/TMS320VC549
graphic shows, 'C549 devices exhibit, average, mA/MIPS active core supply power. However, true measure power dissipation also takes into account processor's quality MIPS.
algorith oltag
algo rith
typical power dissipation 'C549 using on-chip resources (CPU onchip memory) mA/MIPS MIPS 2.5V= 112.5 function more accurate measurement? mA/MIPS itself disregards processor's quality MIPS supply voltage DSP's power dissipation while performing actual application algorithm most accurate measurement complete given task fewer MIPS than another DSP, then into IDLE mode sooner, thus lowering power dissipation even further. 'VC549 operates with dual power supply achieve superior power performance. internal logic, including peripheral logic, supplied with 2.5V, while external logic supplied with 3.3V. dual-power supply allows 'VC549 maintain high performance MIPS, while achieving lowest power dissipation possible. Overall, 'C549 high performance, large on-chip memory, highly integrated peripheral meet needs wide variety wireless wireline, data voice, communications systems. addition, quality available MIPS ultra power dissipation make 'C549 compelling choice ever demanding requirements these systems.
Introduction TMS320LC549/TMS320VC549
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Introduction TMS320LC549/TMS320VC549
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