Viekko Koivumaa Digital Signal Processing Solutions Abstract

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Implementing Shared Memory Interface with TMS320C54x
Viekko Koivumaa Digital Signal Processing Solutions
Abstract
This document describes share memory (SRAM, FIFO, Dual-Port RAM) between Texas Instruments (TI) TMS320C54x digital signal processor (DSP) Host other DSP.
Contents
Design Problem Design Solution
Figures
Figure Figure Figure Figure Figure LC54x DSPs Sharing 32Kx16 Memory Area.3 Using Bidirectional FIFO Share Memory between C54x Host Read Cycle Timing Diagram.5 Write Cycle Timing Diagram Using Dual Port Share Memory with C54x DSP.7
Digital Signal Processing Solutions
December 1998
Design Problem
share memory (SRAM, FIFO, Dual-Port RAM) between C54x Host other DSP?
Design Solution
There several ways implement this. simplest C54x with Host Port Interface, suitable design 2Kx16 block memory large enough. This internal memory area then available with glue logic required. need share external memory with Host HOLD mode, this situation similar that described Designer's Notebook (Shared Memory Interface with TMS320C5x DSP). HOLD mode, continue execution program from internal memory resetting Hold Mode (HM) bit. information HPI, section Texas Instruments TMS320C54x User's Guide, Reference Volume 1997. HOLD mode described section 10.6 same user's guide. also data sheet used this report, TMS320C54x, literature number SPRS039A. zero wait state access time C54x read from external memory 15ns (using MSTRB). required setup time read 5ns. writes uses external cycles. reads writes take cycles (using IOSTRB).
SRAM Used Global Memory Area without Using HOLD Mode
When SRAM shared without HOLD mode, buffers need used. Figure shows LC54x DSPs share 32Kx16 memory area.
Implementing Shared Memory Interface with TMS320C54x
Figure LC54x DSPs Sharing 32Kx16 Memory Area
TMS320LC541-40
READY MSTRB
CLKOUT
ATF22LV10C
TMS320LC541-40
READY MSTRB
CLKIN
SN74ALVCH16245
SN74ALVCH16245
A0-A14 D0-D15
A0-A14 D0-D15
BUFFER
BUFFER
A0A14 D0D15
IDT71V008S10
SRAM
DSPs synchronized with same clock CLKOUT from left corresponds CLKOUT from right DSP. SRAM located upper half 64KW Data space (DS). SRAM accesses arbitrated synchronized clock with Programmable Logic Device (PLD). Here DSPs have equal priority memory. Only access from allowed time with next memory cycle going other DSP, both asking memory within same arbitration period. Data Strobe DS_, Address A15, Memory Strobe MSTRB_ indicate valid memory request. These signals decoded Chip Select line SRAM. Write timing SRAM controlled. also controls access from buffers SRAM with Output Enable lines. READY indicates that memory cycle served. Note that will perform ready-detection only least software wait states programmed into Software Wait State Register (SWWRS) upper half data memory space. LC54x Address lines (A0-A14), Data lines (D0-D15), R/W_ line buffered SRAM. R/W_ line also controls direction buffer. Using buffers allows both DSPs also have local external program (64KW) data memory (32KW lower half data space).
Implementing Shared Memory Interface with TMS320C54x
FIFO Used Shared Memory
Figure shows bidirectional FIFO communication between TMS320C54x Host.
Figure Using Bidirectional FIFO Share Memory between C54x Host
TMS320C541-40
FIFO
PORT PORT
CLKOUT
CLKA
MSTRB
W/RA
RSTA
A0-A15 WENA RENA
INT0 INT1
D0-D15
PENA
SN74ABT7819-12
FIFO used SN74ABT7819-12, clocked bidirectional FIFO with 512x18x2 organization. data only bits, A16-A17 lines FIFO connected with resistors. control over port which means that writes FIFOA-B reads from FIFOB-A. first read takes cycles successive reads take only cycle. there interrupts, buffer will read empty. reads, first value needs discarded because valid data. However, after this initial state reads single cycle. Writing always takes cycles.
Implementing Shared Memory Interface with TMS320C54x
512x18x2
Almost-Full/Empty flag (AF/AEA) used indicate Half-Full state FIFOAB with line BIO_ input DSP. When FIFOA-B becomes full, Input-Ready port (IRA) goes low. interrupted with INT0_ line this disables writes FIFO. When FIFOB-A becomes empty, Output-Ready port A(ORA) goes low. interrupted with INT1_ line stop reads FIFO. also controls FIFOA-B reset line RSTA_ with output. FIFO located upper 32KW half data space with address line. Valid access FIFO indicated with valid address, Data Strobe DS_, Memory Strobe MSTRB_. critical FIFO timings consider read access time data setup time write. FIFO clocked with CLKA High transition. Setup time Chip Select CSA_ 6ns. Figure shows timing read cycle Figure shows timing write cycle. gate delay allowed minimum maximum 5.5ns. make handling gate delays easier, have faster gates, e.g., with min/max within range 4ns. savings 1.5ns maximum value then added maximum value NAND. This gives delay range -7.0ns NAND.
Figure Read Cycle Timing Diagram
CLKOUT MSTRB D15-D0 CLKA
DUMMY VALID VALID
Figure Write Cycle Timing Diagram
CLKOUT MSTRB D15-D0
18.5
23.5
VALID
CLKA
Implementing Shared Memory Interface with TMS320C54x
C54x read cycle activated with MSTRB_ going low, 0-5ns after CLKOUT goes low. MSTRB_ stays active long have successive reads. most critical timing with CLKA. transition occur earliest after CLKOUT eliminate extra clock, after stop reading. MSTRB_ timing -2/+3ns CLKOUT CLKA occur latest 11ns after CLKOUT This enables meeting maximum access time setup time C54x data read. C54x write cycle, MSTRB_ goes high every write cycle, which takes CLKOUT cycles. extra clock when CSA_ active needs eliminated. This done taking inverted MSTRB_ NAND input. Write data valid after 10ns from second CLKOUT plus data setup, after 13ns. Here CLKA occurs earliest 18.5ns latest 23.5ns after starting second CLKOUT cycle. Local external data memory exist with FIFO. want smaller area from data space, more address lines need decoded.
Dual-Port Used Shared Memory
This interface uses 32Kx16 Dual-Port SRAM (DPRAM) with external bank selects from IDT, IDT707278S/L. Figure shows interface. connected Left port Host sharing Right port. memory area consists four 8Kx16 banks, which multiple devices connect using bank select inputs BKSEL0-3.
Implementing Shared Memory Interface with TMS320C54x
Figure Using DPRam Share Memory between C54x Host
IDT707278S/L TMS320C541-40
MSTRB IOSTRB LEFT RIGHT
MBSEL
A0-A12 0-I/O15 BKSEL2 BKSEL0
INT0
A0-A12 D0-D15
BKSEL1
this design Host have their block used local memory. BKSEL0 used Left port BKSEL1 Right port. upper blocks used exchanging data between processors. control over BKSEL2 with line. Host must able control BKSEL3 toggling DPRAM located upper 32KW data space, address line works Chip Select. Memory Strobe MSTRB_ works second Chip Select CE0_. space used Mailbox control logic. Strobe IOSTRB_ connected MBSEL_ activate valid Mailbox access. Address lines A13-A14 used choose bank with Bank Addresses BA0-BA1. access time DPRAM 15ns from chip select, wait state needed with 40MIPS DSP. Access time from signal 9ns, have gate connect data spaces.
Implementing Shared Memory Interface with TMS320C54x
DUAL-PORT
When mailing (data BKSEL2 block) Right port ready, changes from give access Right port sends Mailbox2 interrupt. Host then changes BKSEL3 signal give this area Left port sends Mailbox3 interrupt. will interrupted INT0_ interrupt line. will clear Mailbox3 interrupt read data from Host processor. After reading data, writes data BKSEL3 RAM. When this access completed, sends Mailbox3 interrupt. Host quicker than reading writing data, will initiate change blocks sooner. response from should same Host's response interrupt from DSP. configuration shown allows external data memory lower 32KW data space. External program space also available. Here space used without decoding. timing decoder critical, with accesses cycles.
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Implementing Shared Memory Interface with TMS320C54x

Viekko Koivumaa Digital Signal Processing Solutions Abstract

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