George Elwell, Enterprises, Incorporated Rebecca Texas Instruments Inc

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TMS320C6000 Multichannel Communications System Interface
George Elwell, Enterprises, Incorporated Rebecca Texas Instruments Incorporated
ABSTRACT This document describes simple interface development multichannel telephony systems. Three interfaces provided: MVIP (Multi-Vendor Integration Protocol): Accomplished with MT90810, Flexible MVIP Interface Circuit (FMIC). T1/E1 interface: Accomplished with PEB2254, Framing Line Interface Component (FALC). Voice Band Analog Input Output: Accomplished through TMS320AC3x VoiceBand Audio Processors (VBAP). primary purpose VBAP T1/E1 MVIP environment record messages playback transmission monitor incoming outgoing voice. Each these devices modes that beyond scope this document. This application report addresses physical interfaces between DSP, FMIC, FALC, VBAP using serial interface voice data parallel interface control status. analog interfaces VBAP FALC, well T1/E1 MVIP protocols APIs, within scope this document. Application notes, reports, component data sheets should referenced further details. reference section this application report provides list some these documents. Contents Interface Overview Parallel Interfaces Parallel Interface Timing 2.1.1 Address Setup Requirements 2.1.2 Write Data Strobe Requirements 2.1.3 Read Data Strobe Requirements 2.1.4 Read Hold Requirements 2.1.5 Data Control Signals Hold Requirements 2.1.6 Other Requirements Serial Interfaces VBAP Serial Timing FMIC Frame Group Registers Serial Timing McBSP Registers 3.3.1 Serial Port Control Register (SPCR) 3.3.2 Control Register (PCR) 3.3.3 Sample Rate Generator Register (SRGR) FALC Serial Timing FALC Registers
Digital Signal Processing Solutions
SPRA637
References List Figures
Figure Figure Figure Figure Figure Figure Figure
TMS320C6000 Interface FMIC, FALC, VBAP Combined Parallel Interface Timing VBAP FMIC 2-MHz Mode Serial Timing FMIC 2-MHz Mode Serial Timing, With 8-MHz Clock Control Register (PCR) Sample Rate Generator Register (SRGR) FALC FMIC 2-MHz Mode Serial Timing, With 8-MHz Clock List Tables
Table Parallel Interface Parametric Timing
Interface Overview
Figure shows physical interfaces between TMS320C6000 DSP, MT90810 FMIC, PEB2254 FALC, between MT90810 FMIC TCM320AC36 VBAP. physical interface between FMIC, FALC, consists serial interface that connects FMIC DSP's McBSP0, parallel interface that connects FMIC FALC DSP's asynchronous EMIF. important note that FMIC FALC devices, signals that provided 3.3V must translated using devices such SN74CBTD3384 switches, SN74LVT16245 transceiver buffers. Signals originating from need translated since their values compatible with FMIC FALC.
TMS320C6000
ED[15:0] EA[17:2] /ARE EA[8:2]
SN74LVT16245
BD[15:0]
FALC PEB2254
D[15:0] A[6:0] LINE INTERFACE
/AWE
FMIC MT90810
LDI2 LDO2
/SYPX /SYPR SCLKR SCLKX
DECODER TRANSLATION
ARDY
16-Streams
BD[7:0]
D[7:0] A[1:0] SYNC CLKS
MVIP-90 Interface
SN74CBTD3384
McBSP0 FSR0 CLKS0 FRAME CLK8 LDO1 LDO0 LDI1 LDI0 CLK2 FGA0
VBAP TCM320AC3x
DOUT
HANDSET INTERFACE
Figure TMS320C6000 Interface FMIC, FALC, VBAP
TMS320C6000 Multichannel Communications System Interface
SPRA637
Parallel Interfaces
Both FALC FMIC have parallel interface control status that easily memory-mapped into DSP's external memory interface (EMIF), sharing signals except chip enables. Additionally, memory-mapped interface enables external processor control monitor FALC FMIC through DSP's host port interface (HPI). Direct access from host processor useful some applications. chip selects derived using simple address decoder circuit. This circuit implemented programmable logic device (PLD) with SN74LVT138. EMIF asynchronous control signals directly connected FMIC's FALC's read/write strobes since EMIF memory space control register programmed with timing characteristics that match requirements these devices. FALC parallel interface consists 16-bit data bus, 7-bit address bus, chip select, read strobe, write strobe. EMIF's lower sixteen bits (ED[15:0]) interface FALC's data using voltage translation buffer. DSP's EA[8:2] address signals mapped directly FALC's A[6:0] address signals. FALC registers mapped 32-bit word boundaries with only lower sixteen data bits being valid. FMIC parallel interface consists 8-bit data bus, 2-bit address bus, chip select, read strobe, write strobe. EMIF's lower eight bits (ED[7:0]) connected FMIC's data using voltage translation buffer. DSP's EA[3:2] address signals mapped directly FMIC's A[1:0] address signals. FMIC registers mapped 32-bit word boundaries with only lower eight data bits being valid.
Parallel Interface Timing
Since FALC FMIC share parallel interface, timing must match worse case two. Figure shows parallel interface timing. Table provides parametric timing indicated timing diagrams.
A[6:0] EA[8:2] /CE1 ARDY /ARE READ DATA ED[15:0] /AWE (FMIC) WRITE DATA ED[15:0] (FALC) (FMIC)
(FMIC)
Figure Combined Parallel Interface Timing
TMS320C6000 Multichannel Communications System Interface
SPRA637
2.1.1
Address Setup Requirements
start asynchronous EMIF access parallel interface begins with assertion chip enable (CE1). FALC FMIC require address setup respectively, prior strobe assertion. This shown Figure Since EMIF address signals transition same clock edge, worst-case setup time that the15 setup time FALC. This time period (15ns) plus delay decoder logic (assume 7ns) defines asynchronous setup time that should programmed memory space control register (minimum 22ns). Assuming clock (CPU clock period ns), read write setup fields memory space control register should give 25ns address setup time shown Table Table Parallel Interface Parametric Timing
Parameter Address setup strobe (FMIC/FALC requirement) Address hold from strobe (FMIC/FALC requirement) inactive from (FMIC delay) Data valid after (FMIC delay) Read strobe data valid (FMIC/FALC delay) Data hold from rising (FMIC/FALC output data hold) strobe width (FMIC/FALC requirement) Data setup asserted (FMIC requirement) Data setup de-asserted (FALC requirement) Data hold from strobe (FMIC/FALC requirement)
decoder delay added
Symbol
FMIC (ns)
FALC (ns)
FMIC FALC (ns)
programmed (Setup (Hold
(Hold (Write Strobe (Read Strobe
TMS320C6000 Multichannel Communications System Interface
SPRA637
2.1.2
Write Data Strobe Requirements
FALC FMIC require minimum data strobe period (t7) respectively. Thus, write strobe fields control register should (100 which covers both FALC FMIC minimums. This setting allows sufficient margin FMIC's signal control strobe width stalled accesses FMIC. During write access, FALC requires data setup least prior strobe de-assertion (t9). Since EMIF provides valid data beginning memory cycle writes beginning Address Setup), this requirement easily minimum setup time given 20-cycle (100ns) strobe width. FMIC, other hand, requires data setup least before write strobe assertion (t8). This requirement setup time described Address Setup section above.
2.1.3
Read Data Strobe Requirements
FALC strobe data valid time maximum (t5). FMIC strobe data valid time maximum (tACC tDAC 75ns FMIC data sheet), given microprocessor ready (RDY high). additional margin meet DSP's setup time, read strobe width cycles (105 set, even though FALC FMIC only require minimum combined data strobe period (t7) 100ns.
2.1.4
Read Hold Requirements
EMIF reads, FMIC FALC data hold times (t6) minimum, respectively, after rising edge read strobe. Since rising edge read strobe happens after clock edge that samples data, DSP's hold time requirement much smaller than FALC's minimum, this problem.
2.1.5
Data Control Signals Hold Requirements
FMIC requires data (t10) address (t2) hold time respectively. FALC requires data hold time (t10), address hold time (t2). FALC FMIC require chip selects held past rising edge read write data strobe. Therefore longest hold requirement FALC's data hold time (t10) plus decoder delay total). MHz, this means that write hold field memory space control register should meet requirement. read hold field meet decoder delay) requirement. extra margin, read hold field also ns), just write hold field.
2.1.6
Other Requirements
significant timing parameter shown timing diagrams, i.e. FALC requires least between rising edge read, write strobe next falling edge read write strobe. This means that FALC accesses need controlled, either hardware software, application would ever attempt perform sequential register accesses. hardware approach simple increasing setup strobe periods EMIF memory space.
TMS320C6000 Multichannel Communications System Interface
SPRA637
Serial Interfaces
FMIC's local serial streams interface directly C6000's McBSP (Multichannel buffered serial port), providing convenient interface T1/E1 serial data VBAP. This design uses just DSP's McBSP ports, leaving second available other interfaces, although VBAP FALC could alternatively interface directly another McBSP. Although FMIC FALC allow variety timing clock source configurations, this application report assumes that FMIC always sources serial data clock frame sync signals. After voltage translation, serial data clock connected DSP's McBSP0 CLKS. Similarly, FMIC frame sync signal connected FSR0, which also programmed input. This configuration means that both transmit receive data synchronized with phase alignment. FALC shares these FMIC frame clock signals, with frame being connected both /SYPR /SYPX, CLK8 being connected SCLKR SCLKX. VBAP slightly different timing requirement, therefore will have frame connected FMIC's programmable frame circuits, clock connected CLK2.
VBAP Serial Timing
compatible with T1/E1 requirements, VBAP used companding mode. Linear mode also selected instead certain applications. VBAP available µ-Law, TCM320AC36, applications; A-Law, TCM320AC37, combined T1/E1application, devices switched with relay. VBAP's serial timing directly compatible with FMIC using FMIC's programmable Frame Group. This feature allows Frame offset allow proper alignment clock data. VBAP operate timing modes: Fixed Variable. Since VBAP connected dedicated local stream FMIC, either mode could used appropriately programming FMIC. Fixed Data mode, VBAP provides signal that used gate output VBAP when sharing stream with another device. Fixed Data mode, VBAP uses master clock (CLK) frame synchronization clocks (FSX) (FSR). With FMIC's programmable frame, VBAP's clock data requirements directly compatible with FMIC, since they both receive falling edge transmit rising edge clock. only adjustment required alignment frame sync. Figure shows these timing relationships.
FRAME FMIC FGA0 FMIC FRAME VBAP CLK2 FMIC FSR/X VBAP FMIC VBAP FMIC DOUT VBAP
Figure VBAP FMIC 2-MHz Mode Serial Timing
TMS320C6000 Multichannel Communications System Interface
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FMIC Frame Group Registers
VBAP contains programmable features companding mode. FMIC provides groups independently programmable output framing signals: FGA[0:11] group output signals programmed frame start register (FRMA_STRT) frame mode register (FRMA_MODE). FGB[0:11] group output signals programmed frame start register (FRMB_STRT) frame mode register (FRMB_MODE). VBAP this application connected FGA[0]. FRMA_STRT register FMIC Control Register indirect address FRMA_MODE register FMIC Control Register indirect address upper bits FRMA_MODE register determine mode pins. Modes used programming these pins Frame signals. description other available modes, refer MT90810 Data Sheet (number section References. these modes, selects Frame Type, (1-bit 8-bit length); select rate bits upper three bits 11-bit quantity that determines start position FGA[0] relative Frame 8-MHz clock edge boundaries. offset represents rising edge clock after beginning FRAME FMIC. FRMA_STRT register then contains lower bits 11-bit quantity. proper alignment VBAP frame signal, frame needs begin 2-MHz clock before normal start. This achieved programming (2041 decimal) 11-bit quantity FRMA register. FRMA registers programmed with MODE bits, FRM_TYPE bit, BIT_RATE bits, 11-bit quantity. Furthermore FRMA_MODE register programmed with hex, FRMA_STRT register programmed with hex. Refer MT90810 Data Sheet, (number section References additional information.
Serial Timing McBSP Registers
FALC McBSP serial ports directly compatible with FMIC 2-MHz serial timing when properly programmed, therefore share frame clock signals from FMIC. Note that FMIC, FALC also capable operating 8-MHz data rates. However, 8-MHz mode, FMIC only local stream. These data rates useful certain applications. FALC requires working clock 8.192 data rates, thus FMIC's CLK8 used clock source. DSP's McBSP programmed divide down CLK8 2-MHz data rate. Figure shows timing relationships FMIC with 8-MHz clock, after proper programming McBSP registers.
TMS320C6000 Multichannel Communications System Interface
SPRA637
Beginning Frame
FRAME FMIC CLK8 FMIC CLK2 FMIC FMIC FMIC CLKG (DSP internal) CLKR/X (DSP) (DSP) (DSP)
FMIC Sample Point
Figure FMIC 2-MHz Mode Serial Timing, With 8-MHz Clock McBSP configuration registers need programmed accommodate FMIC 2-MHz data. McBSP takes FMIC CLK8 signal CLKS clock source internal sample rate generator, which then divides FMIC CLK8 input generate 2-MHz internal clock CLKG. CLKG synchronized input from FMIC. McBSP parameters need configured appropriately McBSP/FMIC interface. Figure Figure show setup McBSP registers. values shaded bit-fields "don't cares."
3.3.1
Serial Port Control Register (SPCR)
/FRST=/GRST=/RRST=/XRST=1. internal frame sync generator, internal sample rate generator, receiver, transmitter enabled. Refer application report TMS320C6000 McBSP Initialization (SPRA488), TMS320C6000 Peripherals Reference Guide (SPRU190C), Section 11.5.1.2, details McBSP initialization procedure. interrupt modes selected needed application.
3.3.2
Control Register (PCR)
FSXM Transmit frame synchronization signal generated internally sample rate generator. McBSP/FMIC interface, output used. FSRM Together with GSYNC Sample Rate Generator Register, receive frame synchronization signal input from FMIC McBSP. active transition marks beginning frame synchronizes internal sample rate generator clock CLKG FSR. CLKXM CLKRM CLKX CLKR generated internally sample rate generator. McBSP/FMIC interface, CLKX CLKR outputs used.
TMS320C6000 Multichannel Communications System Interface
SPRA637
FSXP FSRP Transmit receive frame synchronization polarity active low, consistent with active FRAME signal from FMIC. CLKXP CLKRP don't care. Since CLKX CLKR signals used McBSP/FMIC interface, they don't care values. Internally, data always transmitted rising edge CLKG sampled falling edge CLKG. desired, CLKXP CLKRP invert CLKG signal external CLKX CLKR pins.
0x0000 Reserved
XIOEN
RIOEN
FSXM
FSRM
CLKXM
CLKRM
CLKS_STAT
DX_STAT
DR_STAT
FSXP
FSRP
CLKXP
CLKRP
Figure Control Register (PCR)
3.3.3
GSYNC
Sample Rate Generator Register (SRGR)
GSYNC Together with FSRM=1 PCR, internal sample rate clock CLKG resynchronized input signal. CLKSP falling edge CLKS (CLK8 FMIC) generates internal clock CLKG internal frame sync FSG. CLKSM sample rate generator clock derived from CLKS (CLK8 FMIC). FSGM transmit frame sync signal driven sample rate generator frame sync signal FSG. FPER don't care. Since GSYNC=1, frame period dictated external frame sync pulse FSR. FWID Width internal frame sync pulse CLKG period. CLKGDV sample rate generator clock frequency CLKS MHz) divided give 2-MHz data rate.
CLKSP CLKSM FSGM FWID CLKGDV FPER
Figure Sample Rate Generator Register (SRGR) remaining McBSP register settings will vary with application.
TMS320C6000 Multichannel Communications System Interface
SPRA637
FALC Serial Timing FALC Registers
PEB2254 FALC also very flexible device must programmed compatible with FMIC data rate 8-MHz clock. Figure shows FALC MVIP Serial Timing.
Beginning frame (/SYPX/R latched active)
FRAME FMIC /SYPX/R FALC CLK8 FMIC SCLKX/R FALC CLK2 FMIC
FALC's XCO[2:0] FALC samples data falling edge SCLKX
FMIC FALC FMIC FALC
FMIC FALC Sample Point FALC's RCO[2:0] FALC shifts data without delay
Figure FALC FMIC 2-MHz Mode Serial Timing, With 8-MHz Clock FALC allows selection between with single MODE (PMOD) FRAMER MODE REGISTER (FRMR1) byte offset this (PCM (PCM 30). Additionally, FALC's local data rate must set, with IMOD same register. this 2-MHz operation. this application, FALC interfaces: external line interface, local system highway interface FMIC. This application report only discusses latter interface. FALC, term "transmit" refers transmission data from FALC external line interface. Before transmitting this data external line interface, FALC receives this transmit data from FMIC through Transmit Data (XDI) local system internal highway. This incoming local interface data sampled FALC second falling edge SCLKX (time after /SYPX latched active (time shown Figure achieve this, Transmit Offset needs programmed `010' XCO0 XCO2 bits Transmit Control Register (TC0) byte offset hex. Similarly, term "receive" refers reception data from external line interface FALC. FALC then transmits this receive data FMIC Receive Data (RDO) pin. FALC starts shifting data from soon /SYPR latched active time shown Figure Therefore RCO0 RCO2 bits Receive Control (RC0) register byte offset `000'.
TMS320C6000 Multichannel Communications System Interface
SPRA637
References
TMS320C6201 Fixed-Point Digital Signal Processor Data Sheet, SPRS051, Texas Instruments Incorporated. TMS320C6000 Peripherals Reference Guide, SPRU190, Texas Instruments Incorporated. TMS320C6x Multichannel Evaluation Module Reference Guide, SPRU308, Texas Instruments Incorporated. MT90810, Flexible MVIP Interface Circuit Data Sheet, Issue March 1997, Mitel Semiconductor. Introduction MVIP Details Implementation using MT90810 Application Note MSAN-148, Issue September 1994, Mitel Semiconductor. PEB2254, Framing Line Interface Component Data Sheet, T2254-XV13-D1-7600, 1996, Siemens Semiconductor Group. Designing Generic E1/T1 Platform, T2254-XVXX-A1-7600, June 1997, Siemens Semiconductor Group. TCM320AC36, TCM320AC37, Voice-Band Audio Processors (VBAPTM) Data Sheet, SLWS003, Texas Instruments Incorporated. TCM320AC3x/4x Voice-Band Audio Processors Application Report, SPRA146, Texas Instruments Incorporated. Designing with Voice-Band Audio Processor Application Report, SLWA001, Texas Instruments Incorporated. Internet Texas Instruments Incorporated: http://www.ti.com Mitel Semiconductor: Infineon: http://www.mitelsemi.com http://www.infineon.com
TMS320C6000 Multichannel Communications System Interface
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George Elwell, Enterprises, Incorporated Rebecca Texas Instruments Inc

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