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Implementing TMS320C6201/C6701/C6211 Boot Process
Eric Biscondi Digital Signal Processing Solutions
Abstract
Texas Instruments (TITM) TMS320C62x TMS320C67x digital signal processors (DSPs) provide variety boot configurations that determine which actions should perform prepare initialization after device reset. boot process determined latching boot configuration settings reset. various boot processes load code from external memory space from external host processor through host port interface (HPI). This document describes following:
connect host with host port interface boot process example source code host processor create boot code downloaded though
Contents
Overview Connecting C6201/C6701/C6211 Host Processor. Using Host Boot TMS320C6201/C6701/C6211. Boot Process. Host Program Boot Through Creating Boot Code Downloaded Host Appendix Host Source Code Boot Through Appendix Building Array Values From COFF File
Digital Signal Processing Solutions
January 1999
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Connecting TMS320C6201 DSPs Through Boot Process Description Function Used Store Word Memory Space Through Function Used Store Buffer Memory Space Through Command File Converter Utility (Four 8-Bit EEPROMs) Command File Linker Example Interrupt Vector Table (vector.asm) Command File Converter Utility Example Header File code.h Created hex2aray.exe Source Code hex2aray.c
Tables
Table Boot Configuration TMS320C6201/C6701. Table Control Signals Function Selection Description. Table Control Signals Function Selection Description With Host C6x.
Overview
TMS320C6000 uses various types boot configurations, including following:
starts direct execution address 32-bit word memory block automatically copied from memory space memory located address host processor (connected through host port interface) maintains core reset while initializing memory spaces, including external memory spaces.
When boot process selected, held reset while remainder device awakened from reset. This means that host processor connected TMS320C6201/C6701/C6211 through access initialize entire memory space well on-chip peripheral control registers. Once host initialized entire environment, writes DSPHINT control register. This document describes boot process using example which C6201 (host) talks another C6201 (slave).
Connecting C6201/C6701/C6211 Host Processor
Some systems require host processor that communicates with DSP. dedicated port available TMS320C6201/C6701/C6211. 16bit-wide parallel port through which host processor access memory space.
Figure Connecting TMS320C6201 DSPs Through
HOST C6201 EA[2] EA[4:3] /BE[1:0] ED[15:0] ARDY /CEn /AWE /ARE /EXT_INTm /EA[5]
C6201 HHWIL HCNTL[1:0] /HBE[1:0] HD[15:0] /HRDY /HCS /HDS1 /HDS2 /HINT HR/W
Implementing TMS320C6201/C6701/C6211 Boot Process
Using Host Boot TMS320C6201/C6701/C6211
Boot Process
host processor directly access C6201/C6701/C6211 address space through HPI. This peripheral allows host processor exchange information with DSP. also used host initialize load boot code DSP. boot configuration selected external pins BOOTMODE[4:0] C6201/C67001 HD[4:0] C6211.
Table Boot Configuration TMS320C6201/C6701
BOOTMODE[4:0] 00110 00111 Memory Memory Address External; default values Internal Boot
Driving RESET processor then high resets device. When boot process selected, core held reset while remainder device awakens from reset. that time, host processor (connected through HPI) access memory space, including internal, external, onchip peripheral registers. release from reset state, host writes DSPINT control register (HPIC). then starts program execution from address C6201/C6701, boot process operate memory MAP1 (the starts from internal program memory) memory MAP0. this case, starts from with default values, i.e., 32-bit asynchronous memory with maximum read/write setup, strobe, hold time. Therefore, host write memory mapped without initializing EMIF. C6211, external pull-up pull-down resistors connected HD[4:0] during reset configure device. C6211 operates memory only, with internal memory mapped address
Implementing TMS320C6201/C6701/C6211 Boot Process
Figure Boot Process Description
cycles min.
/RESET
Latches BOOTMODE[4:0] `C6201/'C6701 Latches HD[4:0] `C62111
C6000 device held reset. Host initializes memory spaces.
Host writes DSPINT control register.
begins executing code from address
Accessing Registers From Host
Depending connection used between host C6000 DSP, method used access registers from host differ. Typically, registers mapped host memory map. HCNTRL[1:0] HHWIL connected address lines host processors shown Table select which register accessed.
Table Control Signals Function Selection Description
HCNTL1 HCNTL0 HHWIL Register Accessed HPIC half-word HPIC half-word HPIA half-word HPIA half-word HPID half-word, HPIA post-incremented. HPID half-word, HPIA post-incremented. HPID half-word, HPIA affected. HPID half-word, HPIA affected.
Even 16-bit external interface, provides bits combining successive 16-bit transfers. HHWIL identifies first second halfword transfer HWOB determines halfword ordering.
Implementing TMS320C6201/C6701/C6211 Boot Process
Example
Consider example Figure which C6201 (host) connected another C6201 (slave). mapped into asynchronous memory space CE1. address lines EA[4:2] used control control lines HCNTL[1:0] HHWIL. access registers, host performs memory access space shown Table Using language, pointer used shown below:
Host address which mapped *hpi_ptr; define initialize pointer*/ hpi_ptr (int *)C6201_HPI; #define C6201_HPI 0x01400000
Then, following Table following piece code used access HPIA register:
Write dest_address HPIA, with HOB=1
ptr_hpi[2] (int)(dest_address 0x0ffff); ptr_hpi[3]
Table Control Signals Function Selection Description With Host
Address Generated Host Base address 0x00 Base address 0x04 Base address 0x08 Base address 0x0C Base address 0x10 Base address 0x14 Base address 0x18 Base address 0x1C Control Lines
HCNTL[1:0] HHWIL
Register Accessed HPIC halfword HPIC halfword HPIA halfword HPIA halfword HPID halfword, HPIA post-incremented. HPID halfword, HPIA post-incremented. HPID halfword, HPIA affected. HPID halfword, HPIA affected.
Host Program Boot Through
This section considers example shown Figure describe host program used boot C6201. This particular example considers EMIF host C6000 communicating with slave C6000 DSP. code presented Figure without modifications C6000.
Implementing TMS320C6201/C6701/C6211 Boot Process
control through minor modifications code presented example. main modification required port this code another host change registers accessed accordance with host memory map, host-specific data types.
Initializing TMS320C6000 Through
addition writing code into internal memory, host have download code data sections into external memory spaces. host must initialize EMIF registers prior accessing external memory spaces. Figure shows example code that host write single 32-bit value HPI. host first writes HPIC setting HWOB bit, then writes HPIA then HPID.
Figure Function Used Store Word Memory Space Through
void C6x_write_word(int *ptr_hpi, source_word, dest_address) Write HPIC with HWOB=1,1st halfword transferred least significant ptr_hpi[0] 0x0001; halfword ptr_hpi[1] 0x0001; halfword HCNTRL1 HCNTRL0 HHWIL
Write destination address HPIA, halfword least significant HCNTRL1 ptr_hpi[2] (int)(dest_address 0x0ffff);/* ptr_hpi[3] HCNTRL0 HHWIL
Write source_word HPID without address post-increment half-word transferred least significant HCNTRL1 ptr_hpi[6] (int)(source_word&0x0ffff); ptr_hpi[7] HCNTRL0 HHWIL
Appendix provides complete example. Lines correspond EMIF initialization performed host processor through HPI. During boot process, only maintained reset. peripherals active. accessing on-chip peripheral registers, host initialize start C6201 peripheral. example, depending system requirements, host have initialize start serial port transfer.
Transferring Code Data Sections
program composed initialized sections non-initialized sections. host processor must load sections C6000 correct address accordance with link command file. host must write complete section given address. Figure shows example function that reads length 32-bit words data from *source then writes through C6000 address, dest_addr.
Implementing TMS320C6201/C6701/C6211 Boot Process
Figure Function Used Store Buffer Memory Space Through
void C6x_write_section(int *ptr_hpi, short *source, dest_add, length) Write HPIC with HWOB=1,1st halfword transferred least significant ptr_hpi[0] 0x0001; halfword ptr_hpi[1] 0x0001; halfword HCNTRL1 HCNTRL0 HHWIL
Write destination address HPIA, halfword least significant HCNTRL1 ptr_hpi[2] (int)(dest_add 0x0ffff); ptr_hpi[3] HCNTRL0 HHWIL
for(i=0 length i++) Write source_word HPID with address post-increment half-word transferred least significant HCNTRL1 HCNTRL0 HHWIL ptr_hpi[4] (int) *source++; ptr_hpi[5] (int) *source++;
pointer *source points location where boot code slave C6000 stored. example, pointer might point
External mapped host memory containing boot code Data array (linked with host code) containing boot code slave C6000 Host peripheral that receive boot code slave C6000 (for example, serial port)
second option used complete example shown Appendix Lines give inclusion header files containing code (code.h) initialized data (initia.h). Notice that this solution requires recompilation host code each time code modified. also requires automatic create array (containing program initialized data) from COFF file. Please refer Appendix complete description this process.
Remove Slave TMS320C6000 From Reset State
Once host processor performed initialization loaded code data sections into C6201 memory spaces, must release C6201 from reset state writing DSPINT bit. example considering:
Implementing TMS320C6201/C6701/C6211 Boot Process
Write HPIC with DSPINT=1 halfword halfword HCNTRL1
HCNTRL0 HHWIL
ptr_hpi[0] 0x0002; halfword ptr_hpi[1] 0x0002; halfword
Once DSPINT written starts address
Creating Boot Code Downloaded Host
This section discusses built code downloaded from host through host port interface. shown previous sections, host processor write code sections initialized data sections through C6000 memory space. C6000 code linked with initialization variables load time invoking linker with option -cr), which enhances performance reducing boot time saving memory used initialized data sections. Figure shows example linker command file. (Figure shows beginning vector table example.) After linking code, stored memory accessible host processor. Basically, there main cases:
host reads code from external memory containing only code, user first program with code. Texas Instruments provides conversion utility that converts output linker COFF object file) into several standards suitable loading into EEPROM programmer. Figure shows example command file conversion utility that builds four files program four 8-bit EEPROMs (assuming host connected four 8-bit EEPROMs).
Figure Command File Converter Utility (Four 8-Bit EEPROMs)
main.out -byte -image -memwidth -romwidth -order ROMS EPROM: 0x0, length 0x20000 files {u22.int, u24.int, u23.int, u25.int}
Implementing TMS320C6201/C6701/C6211 Boot Process
host reads C6000 code from external memory that does contain only code, user include both host code code into same memory. this case, user link C6000 code host code together. have convert C6000 COFF file into suite data that linked with host program. most host applications written language, decided develop tool convert COFF file into array bytes. This typically option used example described Appendix which C6000 code sections included header file code.h C6000 initialized data sections included file initia.h. Appendix describes procedure build code.h initia.h. This method requires re-compilation host code each time code modified.
Figure Command File Linker
lnk.cmd Copyright 1996-1997 Texas Instruments Inc. vector.obj main.obj main.out -heap 0x0200 -stack 0x0200 rts6201.lib MEMORY VECS: PMEM: DMEM: CE0: CE1: CE2: CE3:
00000000h 00000200h 80000000h 00400000h 01400000h 02000000h 03000000h
0000200h 000FC00h 0010000h 1000000h 0010000h 1000000h 1000000h
SECTIONS vectors .text .far .stack .bss .sysmem .cinit .cio .const .data
VECS PMEM DMEM DMEM DMEM DMEM DMEM DMEM DMEM DMEM
Implementing TMS320C6201/C6701/C6211 Boot Process
Figure Example Interrupt Vector Table (vector.asm)
vector.asm Copyright 1996-1997 Texas Instruments Inc. .ref .ref .ref .ref _c_int14, _c_int15 .sect vectors RESET: _c_int00 NMI: _c_nmi01 RESV1: RESV1 RESV2: RESV2 INT4: _c_int04 INT5: _c_int05
Implementing TMS320C6201/C6701/C6211 Boot Process
Appendix Host Source Code Boot Through
Host.c: Host program boot load through HPI. This program example which assumes that host needs initialize first external memory configuration registers then needs download .text, .cint .const Author Eric Biscondi Date Modifications: Texas Instruments France #include <stdio.h> #include <stdlib.h> Header files containing code program into flash #include "code.h" contains initialized sections code #include "initia.h" contains initialized sections data
#define C6201_HPI 0x01600000 Address 'C6201 HPI*/ #define DEBUG Flag conditional DEBUG info
void C6x_write_section(int *ptr_hpi, short *source, dest_add, length); void C6x_write_word(int *ptr_hpi, source_word, dest_address); void init_host(void);
void main(void) *ptr_hpi; number_code, number_init; ptr_hpi (int *)C6201_HPI; init_host(); Initialization Host processor
Initialization 'C6201 EMIF C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, C6x_write_word(ptr_hpi, 0x0000377d, 0x00000040, 0x00000030, 0x00000030, 0xffffff23, 0x03166000, 0x00000aaa, Emif_global_control); Emif_CE1_control); Emif_CE0_control); Emif_CE2_control); Emif_CE3_control); Emif_SDRAM_control); Emif_SDRAM_refresh);
Determine number halfword contained code section number_code sizeof(code) sizeof(code[0]);
Implementing TMS320C6201/C6701/C6211 Boot Process
Write code sections into memory mapped C6x_write_section(ptr_hpi, (short *)&code 0x0, number_code);
Determine number halfword contained data section number_init sizeof(initia) sizeof(initia[0]); Write cinit sections into internal data memory number_init);
DEBUG printf("TMS320C6201 boot code loaded\n"); #endif Wake TMS320C6201 ptr_hpi[0] 0x0003; Writes half HPIC 0x01600000 ptr_hpi[1] 0x0003; Writes half HPIC 0x01600004
DEBUG printf("TMS320C6201 running \n"); #endif
void init_host(void) Initialize Asynchronous memory space *(int *)0x01800004 0x00e20322;
C6x_write_word This routine downloading data from source address dest_address through Host Port Interface. This routine accesses HPID without automatic address increment Inputs: ptr_hpi: pointer vase address source_word: address data transfer dest_address: destination address write HPIA
Texas Instruments France void C6x_write_word(int *ptr_hpi, source_word, dest_address)
Write HPIC with HWOB=1,1st halfword transferred least significant
ptr_hpi[0] 0x0001; halfword ptr_hpi[1] 0x0001; halfword
HCNTRL1
HCNTRL0
HHWIL
Write destination address HPIA, halfword least significant
HCNTRL1 ptr_hpi[2] (int)(dest_address 0x0ffff);/* ptr_hpi[3] HCNTRL0 HHWIL
Implementing TMS320C6201/C6701/C6211 Boot Process
Write source_word HPID without address post-increment half-word transferred least significant HHWIL
HCNTRL1 ptr_hpi[6] (int)(source_word&0x0ffff); ptr_hpi[7]
HCNTRL0
C6x_write_section This routine downloading data from source address dest_address through Host Port Interface. This routine accesses HPID with automatic address increment Inputs: ptr_hpi: pointer vase address source_word: address data transfer dest_address: destination address write HPIA length: number data transfer Texas Instruments France void C6x_write_section(int *ptr_hpi, short *source, dest_add, length) Write HPIC with HWOB=1,1st halfword transferred least significant
ptr_hpi[0] 0x0001; halfword ptr_hpi[1] 0x0001; halfword
HCNTRL1
HCNTRL0
HHWIL
Write destination address HPIA, halfword least significant
HCNTRL1 ptr_hpi[2] (int)(dest_add 0x0ffff); ptr_hpi[3] HCNTRL0 HHWIL
for(i=0 length i++) Write source_word HPID with address post-increment half-word transferred least significant HCNTRL1 HCNTRL0 HHWIL ptr_hpi[4] (int) *source++; ptr_hpi[5] (int) *source++;
Implementing TMS320C6201/C6701/C6211 Boot Process
Appendix Building Array Values From COFF File
build array values from COFF file, first step conversion utility convert COFF file into hexadecimal files. Figure shows example command file converter utility convert COFF file C6201code.out into files: code sections another initialized data sections. code section included file called C6201code.a00. initialized data sections included file called C6201code.a01.
Figure Command File Converter Utility
C6201code.out -byte -image -memwidth -romwidth -order ROMS Size internal memory PGM: 0x00000000, length 0x10000 Size internal data memory DATA: 0x80000000, length 0x10000
Then developed tool (hex2aray.exe) that takes hexadecimal file input produces array data included into header file.
hex2aray <hex_input_file_name> <header_file_name>
example, must invoke hex2aray build code.h from C6201code.a00 initia.h from C6201code.a01. Figure gives example header file created
hex2aray C6201code.a00 code.h
Implementing TMS320C6201/C6701/C6211 Boot Process
Figure Example Header File code.h Created hex2aray.exe
Header file containing code generated from HEX2ARAY.EXE Date/Time created: 02/23/1998 15:40:16 Copyright Texas Instruments const char
CAUT ION:
Note that name array same file name. source code hex2aray.exe shown Figure
Implementing TMS320C6201/C6701/C6211 Boot Process
Figure Source Code hex2aray.c
//File hex2aray.c //Take ASCII file generated hex6x converter convert //in array byte language. //Date November 1997 //Author Eric Biscondi //Modification Copyright Texas Instruments France #include #include #include #include #include <stdlib.h> <stdio.h> <dos.h> <conio.h> <string.h>
extern directvideo; void main(int argc,char *argv[]) FILE *out_file,*in_file; char chn_fileo[32],chn_filei[32], name_array[32], charac; zero_count, zero; struct time struct date zero 0x30; /*arguments coming from shell printf ("dspc6x <file_in>] <file_out>]\n"); /*initialisation with shell's arguments-*/ (i=1; i<(argc); i++) (!strcmp(strlwr(argv[i]),"-i")) (++i<=argc) strcpy(chn_filei,argv[i]); else (!strcmp(strlwr(argv[i]),"-o")) (++i<=argc) strcpy(chn_fileo,argv[i]); else printf ("dspc6x <file_in>] <file_out>]\n"); /*open file-*/ ((in_file fopen(chn_filei,"rb")) NULL) printf("Unable open input file \n"); exit (1); ((out_file fopen(chn_fileo,"wb")) NULL) printf("Unable open output file \n"); exit (1); gettime(&t); getdate(&d);
Implementing TMS320C6201/C6701/C6211 Boot Process
fprintf(out_file,"/* fprintf(out_file,"/* fprintf(out_file,"/* fprintf(out_file,"/* Header file containing code generated from HEX2ARAY.EXE */\n"); */\n"); */\n"); Date/Time created: %02d/%02d/%02d %2d:%02d:%02d */\n", d.da_mon, d.da_day, d.da_year, t.ti_hour, t.ti_min, t.ti_sec); fprintf(out_file,"/* */\n"); fprintf(out_file,"/* Copyright Texas Instruments*/\n"); Suppress file name extension i=0; sscanf(chn_fileo,"%1s %s", &name_array[i], &chn_fileo); }while( name_array[i++] '.'); name_array[i-1]='\0'; fprintf(out_file, "\n\n\nconst char %s[]={",name_array); line_count zero_count while((in fgetc(in_file)) EOF) in&0x0ff; switch(i) case(0x02): break; case(0x20): break; case(0x0d): break; case(0x0a): break; case(0x24): Case while( (in=fgetc(in_file)) 0x0a); break; default: fgetc(in_file)) EOF) break; in&0x0ff; (i==0x30) (i1==0x30) Zero detection zero_count++; else if(zero_count for(j=0 zero_count j++) line_count++; fprintf(out_file,"0x"); fputc(zero, out_file); fputc(zero, out_file); fprintf(out_file,","); Printf (line_count>10) line_count fprintf(out_file,"\n zero_count=0; line_count++; fprintf(out_file,"0x"); fputc(i, out_file); fputc(i1, out_file); fprintf(out_file,","); Printf (line_count>10) line_count fprintf(out_file,"\n fprintf(out_file,"0x00};"); fcloseall();
Implementing TMS320C6201/C6701/C6211 Boot Process
References
TMS320C62xx Peripherals Reference Guide, Texas Instruments 1997, Literature number SPRU190. TMS320C6x Optimizing Compiler User's Guide, Texas Instruments 1997, Literature number SPRA187. TMS320C6x Assembly Language Tools-User's Guide, Texas Instruments 1997, Literature number SPRU186.
Implementing TMS320C6201/C6701/C6211 Boot Process
Contact Numbers
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Implementing TMS320C6201/C6701/C6211 Boot Process
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Implementing TMS320C6201/C6701/C6211 Boot Process
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