C6000 Hardware Applications ABSTRACT This document describes migration

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C6000 Hardware Applications ABSTRACT This document describes migration

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TMS320C6211 TMS320C6211B Migration Guide
C6000 Hardware Applications ABSTRACT This document describes migration from TMS320C6211 TMS320C6211B. objective this document indicate differences between devices show handle these differences. Depending board layout system level timing assumptions, migration require changes. changes required, some systems able implement necessary timing changes through software control, whereas others require hardware changes. Contents Introduction Asynchronous Memory Table Parameters EDx, Input Hold Time Increased Table Parameter AWE, Output Hold Reduced ARDY Performance Improvement Synchronous-Burst Memory Synchronous DRAM Memory Host Port Interface Cycle Performance Differences Conclusion List Tables Table Table Table Asynchronous Memory Timing Changes Synchronous-Burst Memory Synchronous DRAM Timing Changes Host Port Interface Timing Changes
Introduction
TMS320C6211B slightly differs from TMS320C6211. differences timing signal pins changes. Specifically, changes confined external memory interface (EMIF) host port interface (HPI). other device parameters identical between devices. Thus, board-level changes necessary move from TMS320C6211 TMS320C6211B. appropriately consider impact these timings changes, necessary understand current interface timings given system. timing analysis affected signals should done calculate amount available margin affected interfaces. Previously implemented workarounds C6211 errata need undone when migrating C6211B. Revision C6211B compatible with recommended workarounds shown TMS320C6211/TMS320C6211B Digital Signal Processors Silicon Errata (SPRZ154)
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SPRA393
Asynchronous Memory
Table lists asynchronous memory timing parameters that changed from C6211 C6211B. input hold requirement data ARDY increase from output hold time decreased from there available margin current setup absorb timing change, programmable settings changed accommodate timing parameters. Table Asynchronous Memory Timing Changes
Parameter th(AREH-EDV) Hold time, valid after high th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high td(EKOH-AWEV) Delay time, ECLKOUT high valid C6211 C6211B Unit
Table Parameters EDx, Input Hold Time Increased timing analysis shows there least extra hold time provided C6211, then
change required C6211B.
this extra hold time available, then asynchronous read hold period should extended. This adjusted appropriate Space Control Register (CExCTL). Note that this assumes memory continues assert valid data long remains asserted
Table Parameter AWE, Output Hold Reduced timing analysis shows interface exceeds memory's write strobe length
requirement more, then change required.
this extra strobe time available, then programmed write strobe length should extended. This adjusted appropriate Space Control Register (CExCTL). Note that asynchronous setup time measured from address/control/data valid same C6211 C6211B. Therefore, changes programmed write setup time necessary, despite change timing.
ARDY Performance Improvement
ARDY input hold time, change required. timing change alter cycle which recognizes ARDY assertion. valid data driven before ARDY asserted, this timing change will impact data sampled DSP, cause asynchronous cycle C6211B complete clock earlier than C6211.
Synchronous-Burst Memory Synchronous DRAM Memory
Table lists synchronous-burst memory Synchronous DRAM timing parameters that changed from C6211 C6211B. Synchronous-burst synchronous DRAM memory cycles programmable. timing analysis shows extra input hold provided 0.3ns memory, then changes necessary. timing analysis shows system tolerant timing changes, then board level changes necessary support correct operation. most SDRAM systems unlikely that these will cause issue because:
TMS320C6211 TMS320C6211B Migration Guide
SPRA393
output hold from (Table parameters 8-12), typical systems SBSRAM SDRAM will require less input hold than provides. input hold from (Table Parameter typical systems output hold from SBSRAM SDRAM plus round trip delay from DSP's ECLKOUT return data from SBSRAM SDRAM will meet this requirement. general, system more heavily loaded easier this requirement met. Table Synchronous-Burst Memory Synchronous DRAM Timing Changes
Parameter th(EKOH-EDV) Hold time, valid after ECLKOUT high C6211 C6211B Unit
1-5, 8-12 td(EKOH-xxxx) Delay time, ECLKOUT high signals valid
Host Port Interface
Table lists timing parameters that changed from C6211 C6211B. These host port timing changes should impact systems. Only maximum output hold C6211B reduced compared C6211. Since output hold timing verification must calculated from worst-case (minimum) time, this change does alter that timing analysis. Also, delay time changes represent improvement when compared C6211. Therefore, changes required handle timing differences. Table Host Port Interface Timing Changes
Parameter toh(HSTBH-HDV) Output hold time, valid after HSTROBE high Td(HCS-HRDY) Delay time, HSTROBE HRDY C6211 C6211B Unit
6-7, 15-17 Td(HSTBx-xxxx) Delay time, HSTROBE signals valid Td(HASL-HRDYH) Delay time, HRDY high
Cycle Performance Differences
While these timing changes impact functionality, should noted that cycles identical C6211 C6211B. Performance improvements fixes cause data presented different time different burst lengths supported. Both C6211 C6211B adhere same behavioral specification (with exceptions noted silicon errata). Therefore, host interface does depend cycles appearing certain way, this change will adversely impact interface.
Conclusion
When migrating from TMS320C6211 TMS320C6211B, only changes consider timing changes EMIF HPI. With interface timing analysis these ports, impact timing changes considered. case where conflicts created, changes necessary migrate. changes cause timing violations, then system software hardware will need altered address violation.
TMS320C6211 TMS320C6211B Migration Guide
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