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Telecommunications Applications With TMS320C5x DSPs
1994
Digital Signal Processing Products
Printed U.S.A., October 1994
SPRA033
1994
Telecommunications Applications With TMS320C5x DSPs
Telecommunications Applications With TMS320C5x DSPs
Edited Mansoor Chishtie Digital Signal Processing Applications Semiconductor Group Texas Instruments Incorporated
SPRA033 October 1994
Printed Recycled Paper
Part Introduction
Part Digital Cellular Systems
Part Speech Synthesis
Part Error-Correction Coding
Part Baseband Modulation Demodulation
Part Equalization Channel Estimation
Part Speech Character Recognition Algorithms
Part VIII System Design Considerations
Part Bibliography
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1994, Texas Instruments Incorporated
Preface
This book belongs growing series digital signal processing application books that Texas Instruments published over years. Some these books broad content cover wide variety DSP-related technologies applications. Others more focused concentrate application area. also published many individual application reports. This particular collection application reports focuses primarily variety applications that related field telecommunications implemented 'C5x generation TMS320 family. This book divided into nine parts, including introduction bibliography: Part Introduction Part Digital Cellular Systems Part Speech Synthesis Part Error-Correction Coding Part Baseband Modulation Demodulation Part Equalization Channel Estimation Part Speech Character Recognition Algorithms Part VIII System Design Considerations Part Bibliography Part introduces TMS320 family TMS320C5x generation; also summarizes various telecommunications applications that TMS320C5x DSPs. Parts VIII discuss major application topics. Most papers presented here application reports written either engineering staff digital signal processing department (including factory field personnel summer students) third parties. Some papers were contributed other departments within generally assumed that reader literate some exposure TMS320 family. application reports presented this book represent practical implementations algorithms. Source code associated with these reports listed this book because space constraints. However, most papers have associated source code that publicly available from TMS320 Bulletin Board System (BBS) 713-274-2323. contents this also mirrored Internet anonymous site ti.com. Some technical papers included here present commercial implementations that licensable from respective organizations. technical data sheets these implementations will also included future update TMS320 Software Cooperative Library. editor would like thank contributors reviewers this book. particular, special note appreciation goes Gene Frantz, Reimer, Chirayil, Paul Buenaflor their encouragement helpful suggestions improving overall structure this book. hope that this book will help making transition DSP-based telecommunication applications. Lastly, editor would like acknowledge untiring efforts Katie Delbridge planning coordinating this project. Mansoor Chishtie Telecom Applications Digital Signal Processing Semiconductor Group Texas Instruments Incorporated
Contents
Title Page
Part Introduction
Introduction Overview Programmable Versus Hard-Wired Solutions Fixed-Point Versus Floating-Point Solutions TMS320 Digital Signal Processors TMS320C5x Architecture Summary Telecom Applications Topics Bibliographies Other References
Part Digital Cellular Systems
Digital Cellular Phone: Functional Analysis Introduction Transmitter Receiver Summary References IS-54 Simulation Introduction Description Using Simulation Code Availability References
Part III: Speech Synthesis
Theory Implementation Digital Cellular Standard Voice Coder: VSELP TMS320C5x Introduction Overview VSELP Speech Decoder Features VSELP TMS320C5x Real-Time Implementation Typical Digital Cellular Vocoder Configuration Code Availability References
Contents
Title Page
Part Error-Correction Coding
U.S. Digital Cellular Error-Correction Coding Algorithm Implementation TMS320C5x Abstract Introduction VSELP Channel Format FACCH Channel Format Code Availability References
Viterbi Implementation TMS320C5x V.32 Modems Introduction Standard V.32 Encoder Viterbi Decoder Viterbi Decoder Implementation Performance Analysis Summary Code Availability References TMS320C53-Based Enhanced Forward Error-Correction Scheme U.S. Digital Cellular Radio Abstract Introduction Algorithm Description Implementation Details Results Conclusions References
Part Baseband Modulation Demodulation
IS-54 Digital Cellular Modem Implementation TMS320C5x Introduction Description p/4-QPSK Modulation Scheme Theory p/4-DQPSK Modem Modem Implementation TMS320C5x Performance Results Summary Code Availability References
Contents
Title Page GMSK Modem Mobitex Other Wireless Infrastructures Abstract Introduction Mobitex Modem Characteristics Modulator Design GMSK Demodulator Design Conclusions Code Availability References
Part Equalization Channel Estimation
Equalization Concepts: Tutorial Introduction What Intersymbol Interference? Equalization Equalization Code Availability References Channel Equalization IS-54 Digital Cellular System With TMS320C5x Introduction Design Considerations Equalizer Design Choosing Update Algorithm Code Availability References Digital Voice Echo Canceler Implementation TMS320C5x Introduction 'C5x Device Features Used This Implementation Conclusion Acknowledgements Code Availability References Appendix: Schematic Dual-Telephone Interface TMS320C51 SWDS
Contents
Title Page
Part VII: Speech Character Recognition Algorithms
DSP-Based Handprinted Character Recognition Introduction Architecture System-Level Software Results References Implementation HMM-Based, Speaker-Independent Speech Recognition System TMS320C2x TMS320C5x Abstract Background TMS320-Based Recognizer System Considerations Conclusion Automated Dialing Cellular Telephones Using Speech Recognition Introduction Technology Human Interface Implementation Accuracy Code Availability Summary
Part VIII: System Design Considerations
PCMCIA Card: All-in-One Communications System Introduction System Architecture Operation Conclusion Software Coding Guidelines 'C5x Developers Introduction Hardware Platform Overview Software Organization Memory Organization Programming Guidelines Source Code Documentation Appendix: Sample Linker Command File 'C5x Card
viii
Contents
Title Page TCM320AC3x/4x Voice-Band Audio Processors Introduction Principles Operation Transmit Channel Receive Channel Timing Clocking Fixed- Variable-Data-Rate Modes Application Information
Part Bibliography
Bibliography TMS320 Bibliography Mobile Radio Systems Modulation Demodulation Equalization, Channel Estimation, Adaptive Filtering Speech Recognition Speech Compression System Design Considerations
List Illustrations
Figure
Title
Page
Introduction
TMS320 Family Devices Features TMS320C5x Architecture Functional Components Dual Mode Cellular Phone Functional Blocks Digital Portion Dual Mode Phone Front Analog Section Converts Audio kbps Data Stream Full Rate Speech Coder (VSELP) Reduces kbps Data Stream kbps Data Stream Channel Coder Functional Components With Associated Data Rates Error Protection Convolutional Coding Computation Error Protection Adds Extra Bits Speech Frame Interleaving Adjacent Frames Error Protection Control Signal Multiplexing Burst Generator Level Modulator Groups Bits Form Symbol
Digital Cellular Phone: Functional Analysis
Differential Quaternary Modulator States DQPSK Modulator
Linear Amplifiers Needed Cellular Phone Portion Receiver Section Dual Mode Cellular Phone MLSE Adaptive Equalizer Channel Decoding Speech Decoding Simulation Processing Block Diagram Error Encoding Interleaving Convolutional Encoding Block Diagram Slot Formats
Simulation
Theory Implementation Digital Cellular Standard Voice Coder: VSELP TMS320C5x
Filter Coefficient Quantization Interpolation Adaptive Code Book Search Code Book Search Signal Flow Possible Digital Cellular System Configuration
U.S. Digital Cellular Error Correction Coding Algorithm Implementation TMS320C5x
Voice Control Channel Multiplexing Over Time Slot Error Protection VSELP Data Convolutional Encoder VSELP Data Representative Trellis Section VSELP Convolutional Encoder Transition Table Organization FACCH Rate Convolutional Encoder
List Illustrations
Figure
Title
Page
Viterbi Implementation TMS320C5x V.32 Modems
Modems Encoder Viterbi Encoder Viterbi Decoding Modem Viterbi Decoding Convolutional Encoding Scheme Output Tracking Cost Function Dynamic Programming Modem Trellis Diagram Signal Element Mapping
Encoder Program Flow Decoder Flowchart Delay State Linking Word Circular Buffers Format PAST_PATH PAST_DL Tables DIST Table Structure White Noise Impairment Simulation Results
TMS320C53-Based Enhanced Forward Error-Correction Scheme U.S. Digital Cellular Radio
Voice Channel Algorithm Simulated Error Rate Serial Versus State Path History Trace
IS-54 Digital Cellular Modem Implementation TMS320C5x
Shifted QPSK Signal Constellation
Modulator Block Diagram Demodulator Block Diagram Interrupt Organization Modem Test Configuration Versus Static AWGN Channel Typical Mobitex Terminal Architecture Error Rate Versus Eb/No Modem Performance Idealized GMSK.3 Generation Pattern kbps GMSK.3, 215-1 Length Pseudorandom Transmit Data GMSK Modulator Implementation GMSK Demodulator Implementation Mobitex Packet Structure Computer Simulated Pattern 19.2 kbps GMSK.5 (Amplitude Versus Time).
GMSK Modem Mobitex Other Wireless Infrastructures
List Illustrations
Figure
Title
Page
Equalization Concepts: Tutorial
Pulse Train Transmitted Component r(t) Contribution Contribution Shifted Pulse Responses Symmetry Spectral Response 1/(2T) Time Response Raised Cosine Signal Transmission Process With Example Pulse Responses Case Ideal Channel, Multipath Effects Case System With Single Unattenuated Multipath Channel Equalization Process Simulated Pulse Response Filter Coefficient Filter Output Computation Decision Directed Equalization Received Signal Including Additive Noise Effects Functional Block Diagram
Channel Equalization IS-54 Digital Cellular System With TMS320C5x
DQPSK
Multipath Interference Rayleigh Fading Intersymbol Interference: Interferer Level Block Diagram Decision Feedback Equalizer Equalizer Taps Responding Fade Prototype Platform With Input Card Memory Organization
DSP-Based Handprinted Character Recognition
Implementation HMM-Based, Speaker-Independent Speech Recognition System TMS320C2x TMS320C5x
Voice Dialer Sentence Hypothesizer Flow Chart Minimal TMS320C53 System Example Flow Block Diagram Recognizer Feature Extractor Example Q4/16 Notation SISR System Very Large Vocabulary
List Illustrations
Figure
Title
Page
Automated Dialing Cellular Telephones Using Speech Recognition
Flow Diagram Human Interface
PCMCIA Card: All-in-One Communications System
Card Block Diagram Card Architecture
Loading Executing Single Algorithm
Software Coding Guidelines 'C5x Developers
Categories Source Code Files
TCM320AC3x/4x Voice-Band Audio Processors
VBAP Functional Block Diagram VBAP Microphone Connection
VBAP Interfaced 'C5x
xiii
List Tables
Table Title Page Introduction
Benefits TMS320C5x Features
Digital Cellular Phone: Functional Analysis
Basic Parameters VSELP Speech Coder Allocations Within Frame Speech.
Detailed Allocations Parameters Within Frame Interleaving Adjacent Speech Frames,
Theory Implementation Digital Cellular Standard Voice Coder: VSELP TMS320C5x
Primary VSELP Parameters VSELP Frame Allocation
VSELP ocoder Processor Requirements VSELP ocoder Memory Requirements
Viterbi Implementation TMS320C5x V.32 Modems
Program Benchmarks Encoder Code Decoder Code
TMS320C53-Based Enhanced Forward Error-Correction Scheme U.S. Digital Cellular Radio
Algorithm Execution Time TMS320C53 Memory Requirement
IS-54 Digital Cellular Modem Implementation TMS320C5x
Phase Calculation Reduced Equations Symbol Look
Even Symbol Look Modulator Look Program Memory Speed Requirements Modulator Code Size Execution Time
Demodulator Code Size Execution Time
GMSK Modem Mobitex Other Wireless Infrastructures
Receiver Code Processor Power Requirements
Channel Equalization IS-54 Digital Cellular System With TMS320C5x
Complexity Comparison Update Algorithms
Digital Voice Echo Canceler Implementation TMS320C5x
User Defined System Parameters Program Module Requirements
Implementation Data ariables
Code Benchmarks
List Tables
Table
Title
Page
DSP-Based Handprinted Character Recognition
Application Command Table Subsystem
Implementation HMM-Based, Speaker-Independent Speech Recognition System TMS320C2x TMS320C5x
Current Vocabulary Words) Processor Loading TMS320C5x Examples Qn/m Notations (Fixed Point Representation) Card Registers
PCMCIA Card: All-in-One Communications System
TCM320AC3x/4x Voice-Band Audio Processors
Receive Channel Volume Control Bits VBAP Master Clock Frequencies Power Down Standby Procedures
List Examples
Example Title Page U.S. Digital Cellular Error-Correction Coding Algorithm Implementation TMS320C5x
Pseudocode rellis Expansion rellis Expansion Macro 'C5x Assembly Code race Back Function Pseudo Code
race Back Implementation 'C5x Assembly Code
Digital Voice Echo Canceler Implementation TMS320C5x
Zero Overhead Loops UPDATE.ASM Echo Estimation Routine FIR.ASM Coefficient Update Routine TAPINC.ASM
Near Speech Detection Routine NESPDET .ASM
Echo Simulation Filter EFILT .ASM Delayed Branches NESPDET .ASM Code Excerpt from MULAW .ASM Update Routine UPDATE.ASM
Serial Port ECHOISR.ASM
Introduction
Mansoor Chishtie Digital Signal Processing Applications Semiconductor Group Texas Instruments Incorporated
Overview
programmable digital signal processors (DSPs) growing rapidly telecommunication applications. Conventional wire-line telephony applications were among earliest adopters digital signal processing technologies. High-speed telephone-line modem products more general-purpose DSPs than most other industries, recent growth personal mobile communication services spurred interest high-performance DSPs. With ongoing integration mobile communication services portable computer applications, role programmable DSPs emerging products expanding. Today, digital signal processors moving from high-end, low-volume applications mainstream consumer applications. Telecommunication applications broadly categorized into classes: Core Applications. These applications essence telecommunication product include baseband signal processing algorithms, voice data compression, error correction techniques, equalization channel estimation. Enabler Applications. These applications provide necessary human interface, improve overall quality end-product, include speech character recognition, echo cancellation, noise cancellation.
Programmable Versus Hard-Wired Solutions
DSPs following path microprocessors terms performance on-chip integration. same time, users DSPs concerned about power consumption. communications industry improves portable applications, power high integration become design care-abouts. Generally speaking, product design constrained more following design goals, necessarily with equal importance:
Power consumption Product form factor Upgradability Cost product Cost design System integration
These design goals play roles selecting programmable versus function-specific hard-wired solution. Newer generation DSPs addressing these concerns. They support various low-power power-down modes along with clock control options help meet power goals. System integration form-factor goals often interrelated. With high on-chip integration peripherals memory, modern DSPs well-suited portable applications which product form factor extremely important. Part VIII, "The PCMCIA Card: All-in-One Communications System", page 237, describes system based Personal Computer Memory Card Interface Association (PCMCIA) type card specifications. Many DSPs available thin low-profile plastic packages, which ideal surface-mount applications.
today's evolving communications world, flexibility upgradability design factors longer product cycles. Many personal communication standards early stages development. Some these standards must maintain compatibility with older standards. Programmable DSPs especially suitable designs that require multiple modes operation future upgradability. U.S. digital cellular subscriber unit, programmable engine easily handle two-mode operation. Finally, traditional distinction between programmable function-specific designs fading because customizable (cDSP) solutions. Now, designers decide which section design best suited hard-wired approach. Code that must maintain upgradability downloaded into on-chip RAM. rest program masked on-chip ROM. Algorithm accelerators custom peripherals designed placed same die. These techniques implemented through standard cDSP cell design methodology through standard gate-array design flow TEC320 product line.
Fixed-Point Versus Floating-Point Solutions
Typically, floating-point DSPs used high-end, high-performance telecom applications such video conferencing, network packet switching, cellular base stations, etc. Floating-point DSPs offer large dynamic range, fast floating-point computation engine, large-memory addressability. wider instruction word size, they support more addressing modes higher execution unit parallelism well. Floating-point support large operand dynamic range result ease transition from simulation environment real-time implementation. more orthogonal instruction helps providing efficient high-level language code generation tools. other hand, fixed-point 16-bit DSPs very popular high-volume, low-power applications. Generally, they consume less power cost less because smaller size. They operated faster speeds because their relatively simple architecture fewer speed paths. Newer fixed-point DSPs provide application-specific instructions on-chip power management portable mobile communication applications. their prevalence mobile communications market, many upcoming industry standards fine-tuned 16-bit fixed-point implementations. such example voice compression specification U.S. Digital Cellular Standard, IS-54. This algorithm optimized 16-bit fixed-point engines. With improved compiler support more orthogonal instruction set, end-product development cycle also become shorter.
TMS320 Digital Signal Processors
TMS320 family consists five generations fixed-point floating-point devices (see Figure Members each generation object-code and, some cases, compatible. Each generation offers unique features capabilities, which optimized certain types applications. Figure TMS320 Family Devices
TMS320C1x TMS320C10 TMS320C10-14/-25 TMS320C14 TMS320E14/P14 TMS320C15/LC15 TMS320E15/P15 TMS320C15-25 TMS320E15-25 TMS320C16 TMS320C17/LC17 TMS320E17/P17
TMS320C25 TMS320E25 TMS320C25-33 TMS320C25-50 TMS320C26
Fixed-Point Generations
TMS320C4x TMS320C3x TMS320C30 TMS320C30-27 TMS320C30-40 TMS320C30-50 TMS320C31 TMS320C31-27 TMS320C31-40 TMS320C31PQA TMS320C31-50 TMS320LC31 TMS320C40 TMS320C40-40 TMS320C5x TMS320C2x TMS320C50/-50/-57/-80 TMS320LC50/-50/-80 TMS320C51/-57/-80 TMS320BC51/-57/-80 TMS320C52/-57/-80 TMS320C53/-57/-80 TMS320BC53/-57/-80 TMS320C56 TMS320C57
Performance (MIPS/MFLOPS)
Generation
Floating-Point Generations
TMS320 Fixed-Point DSPs three generations TMS320 fixed-point DSPs TMS320C1x, TMS320C2x, TMS320C5x have 16-bit architecture with 32-bit accumulator. They based Harvard architecture with separate buses program data, allowing instructions operands fetched parallel. They also feature 16-bit hardware multiplier single-cycle multiply operations, hardware stack fast interrupt response time. overflow saturation mode prevents wraparound. Most instructions executed single cycle. Performance currently ranges from MIPS (million instructions second). Even higher performance DSPs will become available near future.
TMS320C1x generation based first DSP, TMS32010, which introduced 1982. 'C1x devices include 144/256 words on-chip words on-chip ROM. Instruction cycle time Members this generation include TMS320C10, TMS320C14, TMS320E14 (the EPROM version TMS320C14), TMS320C15/E15, TMS320C16, TMS320C17/E17. TMS320C14/E14 been optimized control applications. TMS320C16 expanded memory address space words. Low-power versions also available 3-volt designs. TMS320C2x generation based TMS320C25, featuring words on-chip words on-chip ROM. Total address space expanded words both data program. instruction been considerably enhanced over TMS320C1x instruction set, reducing instruction cycle time 120/80 Other members 'C2x generation include TMS320E25 EPROM version TMS320C25), TMS320C26, TMS320C28, which expands on-chip ROM. TMS320C5x generation includes TMS320C50 (10K words on-chip RAM, words on-chip ROM), TMS320C51 words on-chip RAM, words on-chip ROM), TMS320C52 words on-chip RAM, words on-chip ROM), TMS320C53 words on-chip RAM, words on-chip ROM), TMS320C53SX words on-chip RAM, words on-chip ROM). devices except 'C52 have serial ports; 'C52 one. Most devices this generation available thin plastic (132- 100-pin) quad flatpack packages. With enhanced instruction set, TMS320C5x devices execute code rate instruction. architecture features include bit-manipulation unit, called (parallel logic unit), shadow registers fast context switch, JTAG serial scan emulation, zero-overhead loops. Low-power versions also available. TMS320 Floating-Point DSPs generations TMS320 floating-point DSPs TMS320C3x TMS320C4x (the first designed parallel processing) have 32-bit architecture with 40-bit extended-precision registers. They based Neuman architecture. Multiple buses have been added faster throughput. Features include hardware floating-point multiplier floating-point ALU. TMS320C3x generation based TMS320C30 features words on-chip RAM, words on-chip ROM, 64-word on-chip instruction cache. 'C3x devices include on-chip controller, serial ports, timers, external 32-bit data buses, 16M-word linear address space. Instruction cycle rates with peak performance MFLOPS (million floating-point operations second). low-power version TMS320C31 features special instructions power management.
TMS320C4x generation includes TMS320C40, parallel digital signal processor. includes communications ports, self-programmable six-channel coprocessor, developing/debugging analysis module, independent 32-bit memory interfaces, 16G-byte address space, timers. Other features includes 4K-byte blocks, 16K-byte block, 512-byte instruction
cache. This generation designed execute each instruction perform MOPS (million operations second), provide 320M-byte/second throughput.
TMS320C5x Architecture
TMS320C5x generation designed perform complex computation-intensive signal processing real time. high-performance pipelined architecture that enables execute each instruction maximum rate instruction. familiar 16/32-bit accumulator-based architecture with 16-bit wide external address hardware multiplier similar traditional architectures. includes bit-manipulation parallel logic unit, (PLU), which allows efficiently implement traditional microcontroller-type operations. Automatic interrupt context switch reduced interrupt latency made possible on-chip shadow registers 8-word deep hardware stack. On-chip peripherals include serial ports (one which used time division multiplex mode), timer, wait-state generator, phase-locked loop clock frequency multiplication. Figure page shows features TMS320C5x architecture. TMS320C5x architecture introduces several features make suitable telecommunication related applications. Traditional communication designs (such modems cellular radios) microcontroller more digital signal processors. Typical microcontroller tasks system control, general housekeeping, user interface. These tasks generally microcontroller because they require high-performance processor. Additionally, these functions often written involve manipulation. 'C5x manipulation unit (PLU), memory-mapped input-output ports, dynamic postscalers prescalers, language support enable these traditional microcontroller tasks efficiently implemented. Salient features benefits TMS320C5x architecture shown Table
Feature Benefit Harvard architecture Parallel logic unit Hardware stack Shadow registers Simultaneously accesses instructions data operands Allows direct manipulation memory operands Allow zero-overhead context switch interrupts Supports fast interrupt processing Reduce overhead looped code Repeat-block loops Circular buffers Memory-mapped ports Hardware multiplier Efficiently handle peripheral data transfer Implement queues, delay lines, circular convolution, etc. Reduce active idle power consumption Supports single-cycle signed unsigned integer multiplication Power-down modes High-speed, single-cycle instruction execution unit Helps implement advanced signal-processing algorithms real time
Table Benefits TMS320C5x Features
Figure Features TMS320C5x Architecture
Program
Program/Data
Program/Data Buses
16-Bit Preshift 32-Bit With Buffer 32-Bit
16-Bit Register
7-Bit Preshift 16-Bit Right-Shift Memory Mapped Registers Auxiliary TREGs Block/Repeat Circular Buffer
16-Bit Multiply
6-Bit Shift Context Switch Status Register Instruction Register
JTAG Test/Emulator Control Serial Ports Timer Software Wait States Ports Phase-Lock Loop
Multiplexer
Multiplexer
Peripheral
Summary Telecom Applications Topics
Digital Cellular Systems Digital cellular radio designs general-purpose DSPs perform speech synthesis, error-correction coding, baseband modem, system control applications. Where other parts this book concentrate these individual applications, Part focuses primarily overall system design highlights tasks suitable implementation. Speech Synthesis Speech compression coding earliest most widely used applications. both wireline wireless communications vocoders used compress speech signals limited bandwidth channels. application paper U.S. Digital Cellular vocoder implementation presented this section. Error-Correction Coding Forward error-correction (FEC) schemes widely used telecom applications reduce error rate (BER) noisy channels. need improved techniques becoming more prominent these days more data pumped through limited bandwidth channels. Cyclic redundancy check (CRC) parity check still used simple error detection. However, more complex forward error-correction schemes such convolutional encoding with Viterbi decoding Reed-Solomon (RS) codes often used detect correct multiple errors. Often, concatenated coding schemes used provide even more protection against errors than possible with single scheme. such example IS-54 voice channel specification, which Class bits protected both convolutional codes. This described paper that presented this part. Another conference paper schemes also included here, third describes implementation forward error-correction technique used V.32 modems. Baseband Modulation Demodulation Programmable digital signal processors provide necessary performance throughput implement baseband modem functions. These functions include symbol timing recovery, automatic gain frequency control, symbol detection, pulse-shaping, matched filters. Many these functions were formerly implemented hardware. With advent high-performance DSPs growing need multipurpose hardware designs, many these functions being implemented software. such example U.S. Digital Cellular IS-54 standard mobile phones, which every terminal required handle three modulation schemes: FSK, DQPSK. papers presented this book this subject. Equalization Channel Estimation Another computationally intensive task channel modeling estimation echo, noise, intersymbol interference. Line echo cancellation common wireline telephony application suitable implementation. Acoustic echo noise cancellation techniques equally important wireline wireless communication links. Equalization another channel estimation technique removal intersymbol interference caused channel delay spread. first paper this section presents tutorial equalization techniques. other papers present implementation details equalizer line echo canceller.
Speech Character Recognition Algorithms DSPs often called upon perform user-interface tasks addition core applications. This direct consequence very important feature DSP-based product: flexibility design. This flexibility allows system designers load additional tasks their DSPs better utilize spare MIPS. pertinent example that mobile phone; voice dialing feature easily implemented without additional horsepower. This because phone will on-hook off-air), will have many spare MIPS available when voice dialing feature enabled. With onset personal digital assistant (PDA) technology which computers communication applications merge, human interface designs gaining more importance. Three application papers presented this section. System Design Considerations Every system engineer deals with several design care-abouts. This part highlights some these general hardware software design considerations. paper "The PCMCIA Card: All-in-One Communications System" presents embedded hardware design example. second paper, "Software Coding Guidelines 'C5x Developers" outlines general programming guidelines TMS320C5x assembly language programmers. Finally, paper "TCM320AC3x/4x Voice-Band Audio Processors" describes applications with voice-band audio processors.
Bibliographies Other References
keep TMS320 designers aware applications developments related TMS320 DSPs, Texas Instruments published extensive bibliographies TMS320-related conference papers technical articles. Part this book serves extension previously published bibliographies. lists only those papers articles that generally related telecommunication applications. addition this collection telecommunications-related papers TMS320C5x digital signal processors, Texas Instruments published related application papers other digital signal processors. more information, refer Volumes Digital Signal Processing Applications with TMS320 Family: Theory, Algorithms, Implementations.
Digital Cellular Phone: Functional Analysis
(Raj) Pawate Mansoor Chishtie Digital Signal Processing Applications Semiconductor Group Texas Instruments Incorporated
Introduction
This document presents functional components dual-mode cellular phone specified CTIA IS-54 standard. each functional component, relevant algorithm, data structures, any, implementation details given. Functional View Dual-Mode Cellular Phone shown Figure dual-mode cellular phone consists following:
Transmitter Receiver Coordinator
Antenna assembly Control panel
dual-mode phone capable operating analog-only cell dual-mode cell. Both transmitter receiver support both analog digital time division multiple access (TDMA) schemes. Digital transmission preferred, when cellular system digital capability, mobile unit assigned digital channel first. digital channels available, cellular system will assign analog channel. transmitter converts audio signal radio frequency (RF), receiver converts signal audio signal. antenna focuses converts energy reception transmission into free space. control panel serves input/output mechanism user; supports keypad, display, microphone, speaker. coordinator synchronizes transmission receive functions mobile unit. Figure Functional Components Dual-Mode (IS-54) Cellular Phone
Transmitter
Analog-to-Digital Converter
Coder
Amplifier Phase Modulator
Transmit Audio Signal Processing
Modulator
Amplifier
Display
Control
Coordinator
Duplexer
Keyboard Antenna Assembly Digital-to-Analog Converter Decoder Amplifier Demodulator
Receive Audio Signal Processing Control Panel
Demodulator
Amplifier
Receiver
Figure shows functional components digital portion dual-mode cellular phone. Figure Functional Blocks Digital Portion Dual-Mode Phone
Speech Coder Channel Coder DQPSK Modulator Bandpass Filter Isolator
FACCH CDVCC
SACCH
Phase Shift
Detector 824-849 Control Bandpass Filter Bandpass Filter
Coordinator
Detector Phase Shift
864-904 CDVCC FACCH SACCH
Speech Decoder Channel Decoder Equalizer DQPSK Demodulator
CDVCC coded digital verification color code DQPSK differential quaternary phase-shift keying FACCH fast associated control channel SACCH slow associated control channel
Transmitter
transmitter converts low-level audio signals from microphone digitally coded signals audio processing, digital signal processing, modulation, amplification. transmitter converts 64-kbps pulse code modulation (PCM) data lower data rate, multiplexes control information, error-protects data, then passes data stream section modulation, amplification, transmission. coordinator inserts system control messages. Transmit Front-End Processing Speech signals from microphone first amplified, passed through antiliasing filter, sampled rate create digitized µ-law 64-kbps stream. Typically, pre-emphasis applied. Figure shows functional blocks front-end analog section. standard does propose specific echo canceler; however, recommends implementing one. front-end processing includes following:
amplifier. gain specified produce average signal energy, during frame, which down from full scale. bandpass filter avoid antialiasing. analog-to-digital converter. standard recommends that either directly convert analog signal uniform format with minimum resolution bits convert analog signal 8-bit µ-law codec sample.
Figure Front-End Analog Section Converts Audio 64-kbps Data Stream
Amplifier
Filter
kbps
Either linear with bits resolution 8-bit µ-law codec sampled
Speech Coder speech coder further reduces data rate compressing 64-kbps data stream input create 7.950-kbps data stream. IS-54 standard accepts full-rate speech coder called vector excited linear prediction (VSELP). This algorithm belongs class speech coders known code excited linear predictive coders (CELP). This class uses code books vector quantize excitation (residual) signal. VSELP variation CELP. incoming kbps data grouped into frames frame rate frames second. Hence, each frame contains samples represents duration Each frame coded into bits. Hence, rate conversions 7950 bps, shown Figure
Figure Full-Rate Speech Coder (VSELP) Reduces 64-kbps Data Stream 8-kbps Data Stream
Speech Coder MIPS
64-kbps
7.950-kbps
speech decoder utilizes separate code books. Each code book independent gain. code-book excitations each multiplied their corresponding gains summed create combined code-book excitation. basic parameters shown Table
Parameter Notation Specification Sampling rate Frame length samples samples Subframe length Short-term predictor order Number taps long-term predictor Number bits code word (number basis vectors) Number bits code word (number basis vectors) bits bits
NOTE: Within frame, bits allocated shown Table detailed allocations shown Table
Table Basic Parameters VSELP Speech Coder
Gains beta, gamma1, gamma2 Code words, Lag, Frame energy, Short-term filter coefficients Parameter {GS, code fourth subframe {GS, code third subframe {GS, code second subframe {GS, code first subframe code book, fourth subframe code book, third subframe code book, second subframe code book, first subframe code book, third subframe code book, second subframe code book, first subframe fourth subframe third subframe second subframe first subframe 10th reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient reflection coefficient Frame energy Parameter
Table Detailed Allocations Parameters Within Frame
Table Allocations Within Frame Speech
Bits Allocated
GSP0_4 GSP0_3 GSP0_2 GSP0_1 LAG_4 LAG_3 LAG_2 LAG_1 LPC10 LPC9 LPC8 LPC7 LPC6 LPC5 LPC4 LPC3 LPC2 LPC1
CODE2_4
CODE2_3
CODE2_2
CODE2_1
CODE1_3
CODE1_2
CODE1_1
Parameter Name
Bits Allocated
Channel Coder main function channel coder protect data stream against noise fading that inherent radio channel. coder accomplishes this adding extra redundant bits. greater number redundant bits, higher immunity interference lower bit-error rate. tradeoff increased data rate. channel coder protects data stream four stages: Convolutional coding Cyclic redundancy check (CRC) generation Interleaving Burst generation first mathematical operations, whereas last heuristic approaches. receiver performs inverse operation determine whether errors have occurred during propagation. radio propagation, been found that fading occurs localized instances time space. result, interleaving spreads information data stream across frames, because unlikely that clustered error would occur successive frames. Finally, data propagated bursts. Between interleaving burst generation, channel coder multiplexes control information. Figure shows functional components channel coder. Figure Channel Coder Functional Components With Associated Data Rates
7.950-kbps Data Stream Channel Coder 48.6-kbps Data Burst
7.950 kbps
Error Protection
Interleaving kbps kbps
Control Signal Multiplexing
16.2 kbps
Burst Generator
48.6 kbps
Convolutional Coding Convolutional coding provides error-correction capability adding redundancy transmitted sequence. Convolutional encoding implemented linear feed-forward shift registers. convolutional coder described rate which data enters coder rate which data leaves coder. example, rate-1/2 convolutional coder implies that every data entering coder, bits leave coder. smaller ratio, greater redundancy. This improves error-protection capability. reduce rate, bits frame error-protected. Only these bits, called class bits, error-protected. remaining bits, called class bits, error-protected. This shown Figure
Figure Error Protection Convolutional Coding Computation
Most Perceptually Significant Bits 7-Bit Calc. Speech Coder Class Bits
Tail Bits Coded Class Bits Voice Cipher 2-Slot Interleaver
Rate Convolutional Encoder
Class Bits
Speech Frames
Speech Frames
Cyclic Redundancy Check bits that error-protected, been found that only perceptually significant. Hence these protected using 7-bit cyclic redundancy computation before they input convolutional coder. 7-bit computed dividing data specified constant transmitting remainder with data. receiver detects errors comparing received remainder with what calculated. following generator polynomial used CRC: gCRC(X)
parity polynomial, b(X), remainder division input polynomial generator polynomial shown below: a(X)*X7 gCRC(X) q(X) b(X)/gCRC(X)
where q(X) quotient division b(x) remainder. quotient discarded, only parity bits identified b(X) encoded transmission. facilitate convolutional coder, these parity bits placed into array class bits. Figure Error Protection Adds Extra Bits Speech Frame
Error Protection 7.950 kbps kbps
Error Protection Adds Bits/20
short, shown Figure error protection adds bits every additional 5050 bps.
Table shows data interleaved when current frame previous frame. Note that speech data entered into interleaving array columns.
explained earlier, data from each frame divided spread across transmit slots. This done because fading might destroy frame, unlikely that will destroy frames succession. result, bits from speech frame lost slot. Figure shows data interleaved when three speech frames succession.
Interleaving
Table Interleaving Adjacent Speech Frames,
Figure Interleaving Adjacent Frames Error Protection
Speech Frames
y103 x102
y129 x128 y117 x116 x106 y105 x104
Speech Frames
y155 x154 y143 x142 x132 y131 x130
y181 x180 y169 x168 x158 y157 x156
y207 x206 y195 x194 x184 y183 x182
y233 x232 y221 x220 x210 y209 x208
y259 x258 y247 x246 x236 y235 x234
bits from speech frame classified class class bits; data placed into interleaving array such that class bits intermixed with class bits. Class bits sequentially placed into array occupy following numbered locations:
Control Signal Multiplexing
Control signal information added interleaved data. Control information includes
Slow associated control channel (SACCH) Fast associated control channel (FACCH) Digital verification color code (DVCC) Synchronization word (SYNC)
Figure shows this control information multiplexed. Figure Control-Signal Multiplexing
FACCH Data
Speech Data SACCH Data
Slow associated control channel (SACCH) signaling channel parallel with speech path used transmission control supervisory messages between base station mobile unit. SACCH messages continuously mixed with channel data; bits allocated SACCH. Fast associated control channel (FACCH) signaling channel transmission control supervisory messages between base station mobile unit. FACCH messages mixed with user information bits; they replace user information block whenever necessary.
through 130, 156, 182, through
DVCC/SYNC Data kbps
16.2 kbps
Combined Data
Digital verification color code (DVCC) 8-bit code that sent base station mobile unit used generate coded digital verification color code (CDVCC). CDVCC 12-bit field that includes 8-bit DVCC; CDVCC sent each slot from base station mobile unit vice versa. CDVCC used receiver distinguish current traffic channel from traffic cochannels. Synchronization word (SYNC) 14-symbol field that used slot synchronization, equalizer training, time slot identification. Mobile Assisted Handoff Mobile Assisted Handoff (MAHO) feature IS-54. base station command mobile unit perform signal quality measurements current forward channel other forward channels. mobile unit measure quantities: Received signal strength indicator (RSSI), which measure signal strength expressed error rate (BER), which estimate error information obtained measuring correctness data stream input mobile unit's channel decoder.
These channel quality measurements (RSSI BER) sent base station assist handoff. This reduces overhead base station. RSSI usually sent SACCH, although they could sent FACCH during discontinuous transmission (DTX). mode operation which mobile unit transmitter autonomously switches between transmitter power levels while mobile unit conversation state analog voice channel digital traffic channel. Burst Generator After data been compressed error-protected, stream compressed time only) into burst format. Burst timing offsets applied facilitate dynamic time alignment. Figure shows data compressed time-aligned allow data sent using one-third 48.6-kbps channel. Figure Burst Generator
16.2 kbps Speech FACCH SACCH Temporary Storage 48.6 kbps Burst Modulator
6.67-ms Pulse 48.6 kbps Delay 29-44 Symbols Receive Burst
Transmitter DQPSK Modulator Amplifier 48.6-kbps data input differential quaternary phase-shift keying (DQPSK) modulator. This phase modulator groups bits time create symbol. This results four levels modulation, shown Figure Hence, name quaternary. term differential used because symbols transmitted relative phase changes, rather than absolute phase values.
Figure 4-Level Modulator Groups Bits Form Symbol
cosct (0,1)
(-1,0)
(1,0)
sinct
(0,-1)
Figure shows that certain transitions, origin will have crossed. This implies that power envelope decoder will when origin crossed; this have undesired impact filters. alleviate this, scheme used. This shown Figure transitions this scheme either +/-45 degrees +/-135 degrees, origin never traversed transition from state another. This results eight points circle, shown Figure Figure Differential Quaternary Modulator States
Figure shows input serial data presented 2-bit parallel data supplied multipliers after digital-to-analog conversion. Since digital-to-analog converters (DACs) needed, they sometimes referred dual DACs. Binary signals vary phase-shifted signals multipliers. Filters limit impulse response binary signals ensure that carrier occupies allocated bandwidth. signals then summed together form final phase-shifted carrier. conversion from baseband (that frequency translation modulated carrier) typically carried several stages order reach 800-MHz range.
Figure DQPSK Modulator
Multiplier
cosct
Phase Shift
48.6 kbps
Multiplier
sinct
Amplifier amplifier boosts RF-modulated signal output levels, specified base station. Unlike analog transmission, which uses amplifier DQPSK carrier must linear. class push-pull nonlinear amplifiers used amplification purposes. These nonlinear amplifiers efficient (about 50%) order conserve power. However, nonlinear amplifiers cannot used DQPSK, because they would cause phase distortion. Linear amplifiers used DQPSK less efficient (30%). Figure shows amplifier. Figure Linear Amplifiers Needed IS-54 Cellular Phone
Linear Amplifier Efficient
Receiver
Switch
While duplexer required analog section dual-mode phone, required digital portion, because this case transmitter receiver operate simultaneously. simple switch enough isolate receiver from transmitter, allowing duplexer removed from digital portion. Removing duplexer added benefits: when DQPSK signals passed through
duplexer, phase distortion occurs because group delay; addition, there some power loss, which, turn, requires higher-rated power amplifier. Hence, removing duplexer reduces rating power amplifier, which extends battery life mobile unit.
Receiver
receiver functions following order: Amplifies received radio signal Superheterodynes signal lower workable frequency range Demodulates signal Equalizes compensates mitigate effects distortions introduced radio channel Detects errors Decodes speech signal Converts back into analog form eventually feeds speaker receiver consists several functional components: Receiver amplifier Mixer section Demodulator Channel decoder Speech decoder Receiver Amplifier This section receiver amplifies low-level DQPSK carrier, which could weak picowatts (116 dBm). amplifier increases this weak signal workable range before feeding mixer section. receiver amplifier broadband amplifier, which variable gain controlled automatic gain controller (AGC). compensates large dynamic range received signal, which approximately also reduces gain sensitive amplifier that input signal increases, distortions overdriving receiver occur. Figure shows portion receiver. Figure Portion Receiver Section Dual-Mode Cellular Phone
48.6-kbps Burst
Amplifier
DQPSK Demodulator
Equalizer
Mixer frequency received carrier range 869-894 MHz. cost-effective directly demodulate this signal this frequency range. Typically, received signal stepped down lower
frequency, called intermediate frequency (IF), mixing with local oscillator (refer Figure oscillator source varied that constant frequency, which simplifies amplifier design. Typically, second mixer superheterodynes first with another oscillator source produce much lower frequency than first lower frequency enables design narrow-band filters. Demodulator DQPSK demodulator extracts data from signal. Typically, local oscillator with 90-degree phase-shifted signal used. demodulator determines which decision point phase moved then determines which symbol transmitted calculating difference between current phase last phase (note that transmitter differential modulator). Once symbol been identified, next step decode bits. However, noise, Doppler effects, Rayleigh fading, signal must compensated equalized. Fading occurs when same signal arrives receiver different times because multiple paths caused reflections. Doppler effect caused motion transmitter relative received signal. Doppler effect causes received frequency vary proportion speed which mobile unit moving; this implies that equalizer section personal communication systems (PCS) unit need complex when traveling pedestrian speeds when travels higher vehicular speeds. Equalizer equalizer effectively inverse filter channel distortion. Since channel constant wireline channel assumed be), necessary track adapt changing channel. Hence name adaptive equalizer. IS-54 specification does recommend specific equalizer algorithm. present, classes equalizers popular:
decision feedback equalizer (DFE) maximum likelihood sequence estimator (MLSE)
Figure shows example MLSE adaptive equalizer [4]. operates adaptively training mode beginning each burst, well tracking mode during message detection. includes matched filter modified Viterbi processor. equalizer Figure used European system similar ones used North America.
Figure MLSE Adaptive Equalizer
cosct r(t) y(t) x(t) Matched Filter Phase Delay Time Delay Viterbi Processor
sinct
Phase Adaptation Signal Reconstruct
Coefficient Adaptation
Viterbi Adaptation
After demodulation low-pass filtering received signal, components x(t) y(t) sampled converted, with sampling frequency equal rate. Then signal samples filtered through digital N-tap transversal filter, which approximates matched filter (MF) shown. Theoretically, makes receiver insensitive carrier clock phases used demodulate sample received signal, provided that coefficients properly adjusted time span long enough include channel impulse responses. this end, must choose number taps, comply with maximum number echo delays that expect observe operational environment. Note that modulator output pulses spread over three periods. Typically, seems suffice. output samples finally processed according modified Viterbi processor, which operates number states complexity Viterbi processor varies exponentially with respect Channel Decoder channel decoder detects errors stream, demultiplexes control data, feeds data speech decoder. This shown Figure errors detected, masking strategy, explained Frame-Masking Strategy page applied.
Figure Channel Decoding Speech Decoding
48.6 kbps kbps 7.950 kbps 64-kbps
Control Signal Multiplexer CDVCC SACCH SYNC
Error Detection Discarded Speech Data FACCH Decoder
VSELP Decoder
Channel Decoder
FACCH Message
channel decoder works following stages: Control signal demultiplexer Error detector Control Signal Demultiplexer Speech, SACCH, FACCH, DVCC data signals from demodulator demultiplexed separate various signaling information. SACCH DVCC data simply demultiplexed directing dedicated bits from each burst their control-processing locations. Speech FACCH demultiplexing however, more challenging. Since FACCH data replace speech data time, FACCH data extracted first attempting detect errors speech data. appears correct decoded speech slot, data routed speech codec section. When error, data then decoded FACCH message. appears correct, this FACCH message routed call-processing location.
Error Detector DVCC words error-detected, compared assigned DVCC determine cochannel interference, sent transmit section echoed back base station. channel decoder provides information RSSI when commanded base station. This feature called MAHO, which discussed Mobile Assisted Handoff section page Frame-Masking Strategy frame-masking strategy based 6-state machine. every decode speech frame, state machine change states. State occurs most often implies that comparison successful. State implies that there were least consecutive frames that failed check. action taken each these states varies well. state action taken. States simple frame repeats. States repeat attenuate speech. State completely mutes speech. detailed description action corresponding each state follows:
State error detected. received decoded speech data used. State error detected. Parameter values R(0) bits from last frame that state repeated. remaining decoded bits frame passed speech decoder without modification. State Identical action state State Similar action state except that value R(0) modified. 4-dB attenuation applied R(0) parameter: that R(0) last state frame greater than then R(0) decremented repeated this lower level. State Similar state further attenuation applied R(0) that level much from original value R(0). State Similar R(0) further attenuated State frame repeated; this time R(0) cleared totally muting output speech. Alternatively, comfort noise could inserted place speech signal.
Speech Decoder speech decoder, VSELP, converts 7950-bps input data stream into 64-kbps data. poor radio conditions, performance VSELP been shown superior analog cellular. This primarily error-protection error-detection capabilities that made possible digital techniques. When speech frames lost because errors correctable, speech coder repeats previous frame information. number consecutive lost speech frames increases, gradual muting applied. Thus, gaps filled using characteristics human ear. When user data speech, computer facsimile data, then speech decoder bypassed. Adaptive Spectral Postfilter perceptual quality synthetic speech enhanced using adaptive spectral postfilter final processing step. form postfilter
Coefficient synthesis filter
Audio Interface output speech coder, 64-kbps stream, input audio interface, which consists following stages: Digital-to-analog conversion Reconstruction filter Receive-level adjustment reconstruction filter minimizes step transients caused converter. receive-level sensitivity defined that value field, frame energy, causes acoustic level least transducer when measured artificial ear. equal represents average frame energy during frame, which down from full scale.
Summary
This report presents brief functional overview digital cellular mobile station. Emphasis given algorithmic description implementation aspects each function. main purpose this paper provide general introduction various functional blocks. Refer other papers this book detailed implementation description individual functions.
References
Cellular System: Dual-Mode Mobile Station Base Station Compatibility Standard, IS-54 Project Number 2215, Electronics Industries Association, December 1989. Pawate, B.I., "Wireless Communication: Systems Perspective", Texas Instruments (internal document), 1992. Lin, al., Error Control Coding, Prentice-Hall, 1983. Avella, R.D., al., Adaptive MLSE Receiver TDMA Digital Mobile Radio", IEEE Journal Selected Areas Communications, Vol. 122-129, January 1989.
IS-54 Simulation
John Crockett Elliott Hoole Thomas Labno Stephen Popik Wireless Communications Systems Semiconductor Group Texas Instruments Incorporated
Introduction
This paper describes language simulation both transmit receive baseband processing digital cellular telephone that meets U.S. digital cellular standard (IS-54B). This simulation needed reasons: first, gain greater understanding IS-54 digital cellular standard associated digital signal processing required terminal that meets this standard with vision toward efficient implementation TMS320 DSPs; second, gain capability evaluate effect errors speech coder (vector excited linear prediction, VSELP) IS-54 control functions. This necessitated development simulation IS-54 processing channel. Figure IS-54 standard separates data bits into class bits class bits. class bits protected have less influence speech coder than class bits. class bits convolutionally encoded that errors detected corrected. addition, cyclic redundancy check (CRC) calculated class bits designated most perceptually significant. also convolutionally encoded error detection correction used signify noncorrectable errors most perceptually significant bits special error handling provisions. Consequently, evaluation effect errors voice coder must encompass IS-54 transmit receive processing functions.
Figure IS-54B Simulation Processing Block Diagram
Input Speech Samples
Interleave Storage
Transmitter
VSELP Encoder Class Bits Interleave Class Bits Generate Format Convolutional Encode Tail Bits Rayleigh Fading Filter DQPSK Modulate
Deinterleave Storage Deinterleave Delay Detector
White Gaussian Noise
Channel Equalizer Class Bits Class Bits
Filter
Sync
Convolutional Decode
VSELP Decoder
Output Speech Samples
Check
Last Good Slot
Pass Fail
Attenuator Receiver
Description
IS-54 simulation starts with input speech parameters that organized into 20-millisecond frames. Each frame processed through transmit path, channel simulation, receive path. Transmit Path block diagram IS-54 simulation shown Figure speech data read into simulation from input speech file. This file binary pulse-code-modulated 16-bit data. VSELP encoder Motorola standard, which available from TIA. VSELP encoder decoder incorporated into this simulation separate program. output from that program this simulation, whose output then used create final speech data. From output VSELP encoder, most perceptually significant bits encoded speech frame packed into binary word generation CRC. calculated first multiplying input word dividing polynomial given IS-54 gcrc(X) quotient discarded 7-bit remainder kept.
Figure IS-54 Error Encoding Interleaving
Most Perceptually Significant Bits 7-Bit Calc. Speech Coder Class Bits
Tail Bits Coded Class Bits Voice Cipher 2-Slot Interleaver
Rate Convolutional Encoder
Class Bits
Speech Frames
Speech Frames
CRC, along with other class bits (IS-54 Table 2.1.3.3.3.4-2) from VSELP data, packed into array encoded forward error correction. forward error correction rate convolutional encoder with initial state 0x00. This encoder produces output bits each input. last five bits into convolutional encoder tail bits state force encoder also return zero state. block diagram convolutional encoder show Figure
Figure IS-54 Convolutional Encoding Block Diagram
Convolutionally Coded Array Class Bits
Convolutionally Coded Array
output from convolutional encoder, arrays (IS-54 para. 2.1.3.3.3.4), then packed into 260-bit slot data array along with class bits (IS-54 Table 2.1.3.3.4-1). During this packing, bits shuffled around within slot minimize probability that burst error would affect more than same vocoder parameter. This shown Figure voice cipher. 260-bit slot data array then interleaved with data from previous frame that resultant transmitted burst consists bits from both current previous frames. This interleaving data across transmit slots designed randomize burst error across data bits, thus increasing probability that errors will detectable correctable. data, which consists speech redundant error correction information from frames, then formatted IS-54 slot format. Figure This consists inserting sync word, SACCH data, CDVCC field, reserved bits (the CDVCC reserved fields filled with this simulation). base-to-mobile format used order focus processing stream handheld terminal. IS-54 standard specifies modulation differential quadrature phase shift keying (DQPSK). input data paired into dibits, allowing four symbols that specify phase change from previous point complex plane. Each dibit corresponds multiple phase change resulting 8-point modulation constellation. These eight points also called maximum-effect points. next function transmit path square-root-raised-cosine (SRC) filter. This filter employed both transmit receive sections composite effect raised-cosine filter transfer function. This results filter response with nulls adjacent symbols order minimize intersymbol interference. transmit filter also includes interpolation. overall filter response split between transmit receive sections allow more efficient bandwidth partial response signaling.
Figure IS-54 Slot Formats
Data Sync Data Data
SACCH CDVCC
Sync
SACCH
Slot Format: Mobile Station Base Station Data CDVCC Data
RSVD
Slot Format: Base Station Mobile Station Guard Time Ramp Time Data User Information FACCH RSVD Reserved (Set SACCH Slow Associated Control Channel CDVCC Coded Digital Verification Color Code Sync Synchronization Training
Channel Model this point actual IS-54 handset, data would then input stage modulation carrier frequency. Because this simulation, chose substitute simulated fading noise generation transmit receive portions IS-54 processing chain. mobile radio environment, signals from many paths combine antenna. Depending relationship between phase angles signals, effect combination interference that constructive destructive. mobile radio moves, relationship between phase angles changes, causing signals combined randomly providing challenge receiver system designers. term this effect fading, because magnitude result occurs Rayleigh distribution about mean value, called Rayleigh fading. simulator generating Rayleigh fading proposed Jakes [4]: *(N/2 alpha 850.0E+6; lambda 3.0E+8 number simulated signals number oscillators vehicle speed carrier frequency carrier wavelength
lambda; xc(t) sqrt(2)*cos(alpha)*cos(wm*t); xs(t) sqrt(2)*sin(alpha)*cos(wm*t); n++) cos(2*PI*n/N); xc(t) 2*cos(PI*n/N0)*cos(wn*t); xs(t) 2*sin(PI*n/N0)*cos(wn*t); xc(t) in-phase (cosine) component, xs(t) quadrature (sine) component. This model provides very good approximation theoretical behavior excellent general use.
Another major impairment wireless communications within radio itself. received signal gets weaker, signal-to-noise ratio decreases, errors caused thermal noise radio receiver occur. This noise characterized zero-mean, Gaussian probability density function time domain. frequency domain, power spectral density thermal noise constant called white noise. real system, there filters that limit bandwidth noise, power spectral density noise still constant filter passband, still called white. receiver, noise added received signal therefore termed additive white Gaussian noise (AWGN). simulation, Gaussian noise generator used that generates noise unit variance then scaled variance required desired signal-to-noise ratio. Receive Path receive path (receiver) also shown Figure Raised-cosine-filtered samples into sync detector, which looks sync word that occurs beginning slot. sync detector looks this sync word over 4-symbol window, starting symbols prior expected sync point. When data matches proper slot sync word, data into filter. This filter same transmit chain filter described page except that receive filter performs decimation. After through filter, data input channel equalizer. shown Figure channel equalizer turned either under command cellular base station. channel equalizer included this simulation subject separate paper [9]. delay detection process, also called differential decoding, inverse differential encoding process transmitter. delay detector computes amount phase change between successive raised-cosine-filtered maximum-effect points. This shown easily with exponential notation complex numbers. A*exp( j*PI current point B*exp( j*PI previous point. multiply current point complex conjugate previous point: exp(j exp(-j exp(j result exponential whose angle phase change between previous current points. Because phase change that contains information bits, magnitude disregarded. deinterleave function recombines frame speech data from data received from consecutive receive slots. discussed transmit chain description, data interleaved minimize susceptibility burst errors. this time, data divided back into encoded class (cc0 cc1) bits unprotected class bits. class bits then into convolutional decoder while unprotected class bits held recombine with class bits once decoded. convolutional decode performed Viterbi algorithm. two-dimensional array built that (the number bits input encoder) columns wide (the possible number states encoder) rows high. This algorithm calculates probability possible paths through array (which represent sequence states through which encoder would have passed). This probability added cumulative probabilities each possible preceding states give cumulative probability given trellis position. Then, given that beginning ending states convolutional encoder initial state five tail bits force back state path maximum probability selected tracing through array from ending state beginning state. With path through trellis known, input bits easily obtained. path maximum probability should produce original encoded stream, even presence errors. value most perceptually significant bits extracted from decoded class bits. recalculated these bits compared against received CRC. This done detect
presence errors these bits. CRCs match, received VSELP speech parameters sent VSELP decoder. they match, state machine (IS-54 para. 2.2.2.2.3.2.) employed handling errors. This state machine stores last good speech parameters cases repeated errors. received speech parameters then into VSELP decoder speech synthesis.
Using Simulation
goals developing this simulation ensure that portable across different computing platforms. this end, every attempt made only ANSI-C compatible calls syntax. code originally developed using Borland running 486/33 PCs. tested modified make compatible with Microsoft Visual Zortech compilers, which support ANSI-C compliance. simulation, command file, IS54SIM.PRM, utilized pass required information program. Additionally, another file, SRC_FILT.DAT, required contains square-root cosine filter coefficients necessary simulation. These files simulation program must reside same working directory. format command file simple. ASCII file that contains four lines: desired assumed vehicle speed carrier frequency (used Fading model) filename input speech data that already been VSELP processed (This file should also working directory.)
SRC_FILT.DAT file also ASCII file, where each line coefficient used filter. After running simulation typing program name system command line), there seven output files produced, which reside current working directory. These files summarized below. IS54SIM.OUT RAWTXBIT.OUT CLTXBIT.OUT CLRXBITS.OUT ASCII-Hex version 193-bit VSELP data recovered each frame ASCII-Hex version 324-bit formatted TDMA slot prior transmission ASCII-Hex version class bits class bits transmit slot ASCII-Hex version class bits class bits recovered receive slot. Each line receive data (one slot) appended with current error state (0-7). ASCII-Hex version 324-bit formatted TDMA slot prior decoding. Each line receive data (one slot) appended with current error (0-7). state
RAWRXBITS.OUT
examining these output files, user determine performance IS-54 transmission under varying levels (degradation channel). This program also outputs number received frames with valid CRC, number frames with invalid CRC, error rates each field CRC-valid frames.
simulation compiled IBM-compatible using several compilers. simulation runs three slots second 486DX-33MHz
Code Availability
associated program files available from Texas Instruments TMS320 Bulletin Board System (BBS) (713) 274-2323. Internet users access anonymous ti.com.
References
Cellular System: Dual-Mode Mobile Station Base Station Compatibility Standard, IS-54B, Telecommunications Industry Association, April 1992. Chishtie, Mansoor "U.S. Digital Cellular Error-Correction Coding Algorithm Implementation TMS320C5x", Telecommunications Applications With TMS320C5x DSPs, Texas Instruments Incorporated, 1994, Choong, Yong Convolutional Decoder IS-54 Error Protected Speech Codes, Digital Signal Processing Branch, Semiconductor Process Development Center, Texas Instruments Incorporated, 1992. Jakes, William Jr., Microwave Mobile Communications, John Wiley Sons, York, York, 1974, 70-76. Proakis, John Digital Communications, McGraw Hill, York, York, 1989. Choong, Yong Chishtie, Mansoor Convolutional Encoder IS-54 Voice Channel program, Texas Instruments Incorporated, 1992. Chishtie, Mansoor Viterbi Decoder Algorithm IS-54 SACCH Control Channel program, Texas Instruments Incorporated, 1991. Hartman, Matt, Language Version VSELP Speech Coder, Systems Research Laboratories, Chicago Corporate Research Development Center, Motorola, Incorporated, 1990. Hoole, Elliot "Channel Equalization IS-54 Digital Cellular System With TMS320C5x", Telecommunications Applications With TMS320C5x DSPs, Texas Instruments Incorporated, 1994, -187.
Theory Implementation Digital Cellular Standard Voice Coder: VSELP TMS320C5x
Jason Victor Macres Software Engineering, Incorporated
Introduction
subcommittee TR45.3 adopted vector excited linear prediction (VSELP) voice coding standard U.S. digital cellular communications. Motorola responsible design development VSELP algorithm. Additionally, Motorola kept implementation details VSELP algorithm proprietary. This paper explains interoperable VSELP alternative algorithm implementation this algorithm TMS320C5x digital signal processor. interoperable algorithm developed using reference guideline. VSELP algorithm type code excited linear predictive coding (CELP) algorithm that been adopted standard digital cellular communications. VSELP vocoder encodes speech rate 7950 bits/second. additional 5050 bits/second utilized error protection synchronization, bringing total rate 13,000 bits/second. This paper describes only voice coding portion vocoder. brief overview VSELP algorithm presented background.
Overview VSELP
Structurally, VSELP algorithm closely resembles CELP algorithm. difference lies form structure code books. Whereas CELP uses stochastically overlapped code book (each entry shares samples with neighboring entries), VSELP utilizes sets basis vectors generate space candidate vectors. Thus, stochastic code book search CELP corresponds code book searches VSELP. There seven basis vectors each search. Each basis vector contains elements. selection basis vectors fundamental deriving fast code book search procedures. basis vectors chosen provide fast orthogonalization entire space. orthogonalizing each seven vectors with vector entire (27) space, defined seven basis vectors, also orthogonalized. open-loop analysis performed frame speech derive filter coefficients. These coefficients bandwidth expanded perceptual error weighting filters, H(z) W(z), where H(z) 1/A(z) W(z) A(z)/A(z/). input frame speech filtered through filter W(z) obtain perceptually weighted frame speech. analysis synthesis proceeds with three code books (unlike CELP, which proceeds with two). First, adaptive code book searched resulting best entry gain found. This entry multiplied gain factor orthogonalized with first seven basis vectors. Thus, second code book search performed independently first code book search. basis vectors used form code book second search. best entry gain found this code book orthogonalized with second basis vectors. Finally, third code book search performed. gains each three code book searches jointly quantized transmitted with three code book indices receiver. basic blocks VSELP coder are:
Tenth-order analysis (spectrum predictor) Long term (pitch) predictor Adaptive (pitch) code book search First basis vector code book search Second basis vector code book search Vector quantization code book gains
primary VSELP parameters outlined Table
Symbol Parameter Value Sampling rate Samples frame filter order Samples subframe basis vectors basis vectors BWEXP Bandwidth expansion Long term filter order LTFORD
Table Primary VSELP Parameters
VSELP algorithm been developed from references [2]. These references contain information pertaining high-level description algorithm provide actual implemented software (high-level assembly). Allocations
Table shows allocation VSELP frame. frame energy reflection coefficients LPC1-LPC10) sent once frame, while pitch (LAG1-LAG code book indices (CODE1_1-CODE1_4, CODE2_1-CODE2_ gain indices (GSP0_1-GSP0_ sent four times frame. total number bits 20-millisecond speech frame 159, yielding voice coder rate 7950.
GSP0_4 GSP0_3 GSP0_2 GSP0_1 CODE2_4 CODE2_3 CODE2_2 CODE2_1 CODE1_4 CODE1_3 CODE1_2 CODE1_1 LAG4 LAG3 LAG2 LAG1 LPC10 LPC9 LPC8 LPC7 LPC6 LPC5 LPC4 LPC3 LPC2 LPC1 Parameter
Table VSELP Frame Allocation
Bits
Gain index,
Gain index,
Gain index,
Gain index,
index,
index,
index,
index,
index,
index,
index,
index,
Lag,
Lag,
Lag,
Lag,
10th reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
reflection coefficient
Frame energy
Description
Perceptual Weighting Perceptual weighting input speech signal error signal) improves performance coder. high-energy formant regions speech spectrum mask noise better than lower energy portions spectrum. error signal generated each synthesizer pass weighted appropriately capitalize this perceptual effect. filter amplifies error signal spectrum nonformant regions speech spectrum attenuates error signal spectrum formant regions. Thus, error signal whose spectral energy concentrated formant regions speech considered better than whose spectral energy located under formants. Open-Loop Analysis Each incoming speech frame processed through open-loop analysis generate filter coefficients used remaining portions algorithm. input speech first windowed using Hamming window, then autocorrelaion performed result normalized based energy first coefficient autocorrelation. autocorrelation coefficients then windowed bandwidth expansion spectral smoothing using rectangular frequency) window. smoothed autocorrelations input Leroux-Guegan routine, which transforms autocorrelation parameters into reflection coefficients. Leroux-Guegan algorithm chosen because ideal fixed-point implementation very efficient. stability check performed Leroux-Guegan algorithm monitoring value. falls below Leroux-Guegan terminated, previous reflection coefficients used. This instability occur from ill-conditioned autocorrelation coefficients. Interpolation Because reflection coefficients generated analysis represent spectrum speech frame centered over fourth subframe, coefficients remaining subframes interpolated from current previous frame's coefficients. direct form-filter coefficients linearly interpolated. following table shows interpolation scheme: (0.75)ai(previous) (0.25)ai(current) (0.50)ai(previous) (0.50)ai(current (0.25)ai(previous) (0.75)ai(current ai(current) subframe formula subframe formula subframe formula subframe formula
Interpolating direct form coefficients result unstable filter; therefore, resulting coefficients must checked stability. first, second, third subframes, filter coefficients converted reflection coefficients. resulting reflection coefficients' magnitudes greater than then interpolation process produced unstable filter. remedy this instability, filter coefficients subframe replaced uninterpolated filter coefficients. first subframe, previous frame's uninterpolated filter coefficients used. third subframe, current frame's uninterpolated filter coefficients used. second subframe uses uninterpolated filter coefficients from frame (previous current) that higher energy. case when energies equal, subframe uses uninterpolated filter coefficients from previous frame.
following data flow illustrates procedure quantization interpolation filter coefficients. Figure Filter Coefficient Quantization Interpolation
Speech frame Quantized coeffs Quant Interpolated coeffs Stable interpolated coeffs
analysis
coeffs
Interpolate
Check stability
Long-Term Predictor long-term filtering operation (adaptive code book search) VSELP similar general CELP long-term filtering operation. long-term filter given B(z)
accommodate lags less than subframe size NSF), equation modified such that filter's output only function filter state start subframe. B(z)
-flr(
flr(x) function truncates fractional portion returning only integer portion NSF, equations identical. NSF, function will evaluate when depicted Figure
Figure Adaptive Code Book Search
Search Procedure Elements
Adaptive Code Book
Subvectors each extracted from adaptive code book
Update Procedure Best Subvector Adaptive Code Book
Discarded Samples
Adaptive Code Book
Figure portion adaptive code book utilized (call this subvector length starts index defined current value search procedure. NSF, this procedure straightforward because length fits (see Figure inside adaptive code book. VSELP algorithm supports lags from 147; therefore, special situation exists when less than NSF. this case, vector placed such that portion hangs over adaptive code book. These elements adaptive code book (long-term filter state) exist yet. function equation remedies this doubling (code book index value). This results copying first elements vector ending elements.
Figure Code Book Search Signal Flow
y(n) Input Speech bL(n) W(z) Zero Input Response H(z)
Adaptive Code Book
Code Book
excite(n) H(z) p'(n)
p(n) e(n) Calc
Code Code Book
Weighted Error
Code
each 146), vector called bL(n) length extracted from adaptive code book. This vector filtered through bandwidth-expanded filter H(z). resulting vector, b'L(n), compared input vector p(n). p(n) vector perceptually weighted input speech vector minus zero-input response H(z). zero-input response subtracted from input speech remove ringing H(z) filter caused previous subframe. vector that produces minimum mean square error (MSE) maximum match score) compared p(n) chosen best vector from adaptive code book. that produced this vector transmitted receiver. match score defined
where:
NSF-1
L(n))
NSF-
L(n)p(n)
digital cellular VSELP, restricted positive numbers; therefore, only lags with positive considered search procedure. with positive found, adaptive code book disabled. coded using seven bits, yielding possible values. Since only these values valid 146), value reserved disable adaptive code book search decoder. should noted that gain coefficient coded this time. After three code vectors determined, joint optimization performed three gain terms,
implementation precomputes correlations energies stores them. temporary storing these parameters strictly necessary; however, allows find scale factor search performed utilizing maximum dynamic range. Preserving dynamic range very important proper pitch search. Code Search Algorithm Each code books constructed from basis vectors. These vectors combined linearly form code book size code book vectors described
i(n)
m(n)
where basis vector code-book vector. value either formulated follows. Each code book vectors, indexed indices viewed binary form, bits required represent index space. index defined defined then defined (bit index then (bit index then following provides example trivial case when This defines code book size this case, only basis vectors required, namely Each four code book vectors developed below.
should noted that These called complementary code book vectors, this property exploited code book search reduce computational requirements. VSELP code book structure defined above static single code book. formula below expands notation describe VSELP structure with multiple static code books. From equation (6):
k,i(n)
k,m(n)
digital cellular VSELP, that static code books used. three code books searched sequentially. First, adaptive code book searched optimal vector assuming technique used searching adaptive code book described above. stochastic code book searches, necessary generate zero-state response each code vector H(z). This accomplished filtering each basis vectors each code book through H(z) with history H(z) prior filtering each vector. resulting code vectors defined equation (8):
k,I(n)
k,m(n)
where qk,m(n) zero-state response H(z) basis vector vk,m(n). result first search optimal value optimal bL(n) vector. bL(n) vector times gain, represents adaptive code book's contribution excitation signal. Next, first stochastic code book searched, given bL(n). This results optimal code vector corresponding index first code book, f1,I. Finally, second code book searched given bL(n) f1,I(n). This results optimal code vector corresponding index second code book, f2,H(n). searches this implementation take full advantage 'C5x instructions optimized speed. Orthogonalization Code Vectors error signal generated after each code vectors from each code book selected e(n) p(n) L(n) k,I(n) k,I(n)
NSF-1
Total weighted error
2(n)
(10)
Given bL(n) first code book search, optimal values f1,I(n) must found. This however, would computationally expensive real-time performance. vector each code vectors f1,I orthogonal, then code vector jointly optimized independent orthogonalizing each basis vectors b'L(n) vector, entire space code vectors orthogonalized. Grahm-Schmidt algorithm used perform this orthogonalization follows:
NSF-1
L(n))
(11)
NSF-1
L(n)q 1,m(n)
vmvM
(12)
orthogonalized, filtered basis vectors first code book defined 1,m(n) 1,m(n)
L(n)
(13)
orthogonalized, filtered code vectors first code book defined
1,i(n)
imq' 1,m(n)
(14)
expression total weighted error first code book search
(p(n) 1,i(n))
(15)
This expression independent also assumes contribution from second code book. value gain computed each code vector encoded yet. stated previously, value gains each vectors contributing excitation vector jointly optimized after searches complete. second stochastic code book search identical first except that basis vectors second code book orthogonalized both bL(n) vector optimum code vector from code book f'1,I(n). This orthogonalization performed sequentially. filter basis vectors, q2,m(n), first orthogonalized bL(n). resulting vectors then orthogonalized f'1,I(n). orthogonalized, filtered code vectors second code book defined
2,i(n)
imq' 2,m(n)
(16)
expression total weighted error second code book search
(p(n) 2,i(n))
(17)
implementation fixed-point VSELP, modified Grahm-Schmidt algorithm used. difference between this Grahm-Schmidt just presented that this scaled energy constant. This scale washes code book search, avoids expensive division preserves dynamic range. Gray Code Search this section, fast search procedure finding best code vector from stochastic code book developed. with adaptive code book search, vector that minimizes (that that maximizes match score) sought. Note that subscript denoting first second code book been dropped clarity. code search procedures identical each code book. match score defined
(18)
search procedure calculates match score each vector code book. best code vector (indexed will have highest match score code vectors code book. computational requirements subframe search code book multiply-accumulates (MACS). This results code book search computational requirement MACS code book codebooks subframe subframes frame frames (19)
6(MACS) reduce this complexity, structure VSELP code books exploited. Defining correlation between p(n) vector filtered code vector, f'i(n):
ip(n)
(20)
Expanding f'i(n) using equation yields:
NSF-1
imq' m(n)p(n)
(21)
Rearranging summations yields:
NSF-1
m(n)p(n)
(22)
Defining
NSF-1
q'm(n)p(n)
(23)
then substituting this back into yields:
(24)
Defining gain filtered code vector, f'i(n):
NSF-1
i(n))
(25)
Expanding f'i(n) using equation yields:
NSF-1
imq' m(n))(
(n))
(26)
Rearranging summations yields:
NSF-1
(n)q'
(27)
Defining
NSF-1
m(n)q' j(n)
(28)
substituting back into equation (27) yields:
(29)
Because:
and:
equation expanded
(30)
Given code words indexed such that differs from only (that position then:
correlations related
(31) (32)
uvRv
(33)
gains related
(34)
code book searched sequence such that code vector index changes only from previous code vector index, then previous equations leads very efficient method search code book. sequencing indices using Gray code, only will change indices generated. addition, only half each code book needs searched because other half complementary code vectors (differing only sign). sign checked determine which complementary code vectors yields positive gain resulting computational requirements reduced 2)]}
0.468 Gain Quantization
MACS
(35)
gain values each three code book contributions excitation vector jointly optimized using vector quantization table. development quantization procedure found [1]. parameters required joint vector quantization gain values are:
cc(j,
k(n)c' j(n)
(36)
where c'k(n) denotes [0.2]) excitation contribution vector filtered through H(z) synthesis filter. Therefore, upper triangular matrix crosscorrelation matrix three filtered code book excitation contributions.
pc(k)
(n)c' k(n)
(37)
where p(n) perceptually weighted speech minus ringing synthesis filter from previous frame. three-element vector crosscorrelation vector three filtered code book excitation contributions with p(n) vector. x(k)
k(n)
(38)
where ck(n) denotes [0.2]) excitation contribution vector (not filtered). Thus, vector Rx(k) denotes energy each three code book excitation contributions. Equation (39) defines parameter energy filter's residual signal.
q(0)
(39)
where R'q(0) average power current subframe speech product series normalized error power synthesis filter. R'q(0) interpolated from Rq(0) subframe rate using strategy Equations
q(0) q(0) previous frame q(0) q(0) current frame q(0) q(0) previous frameR q(0) current frame
subframe subframes
(40) (41)
subframe
(42)
error equation used searching quantization tables
P0(1 P1(1 (43)
(1-P0 -P1)
where fraction coder excitation energy adaptive code book contribution, fraction coder excitation energy first stochastic code book, energy tweak parameter RS). Note: fraction coder excitation energy second stochastic code book. definitions through follow: pc(0) x(0) (44)
pc(1)
x(1)
(45)
pc(2)
x(2)
(46)
cc(0, 1)RS x(0)R x(1) cc(0, 2)RS Rx(0)R x(2) cc(1, 2)RS x(1)R x(2) cc(0, 0)RS x(0)
(47)
(48)
(49)
(50)
cc(1, 1)RS x(1) cc(2, 2)RS x(2)
(51)
(52)
values vector quantized three-column table length 256. each subframe, index elements that minimize error equation (43) selected. resulting code book gains defined following equations, where subscript indicates index best table entry.
x(0)
(53)
x(1)
(54)
x(1)
(55)
fixed-point implementation, energies calculated converted front floating-point format. parameters then calculated floating point because wide dynamic range. These parameters then scaled back 16-bit integer domain according largest parameters (hence, ratios between parameters maintained.)
Speech Decoder
speech decoder resembles encoder with following exceptions:
coefficients synthesis filter bandwidth-expanded ones. They taken from coefficients bitstream. There closed-loop search procedure. There adaptive postfilter signal flow.
coefficients filter A(z) interpolated subframe rate from reflection coefficients received frame rate. each frame, quantized reflection coefficients specified bitstream converted direct form-filter coefficients. They then interpolated using same scheme defined interpolation section. three code book indices used look correct vector each code books. Each selected vector multiplied corresponding gain value calculated using equations (53), (54), (55). three scaled code book contributions then summed form excitation signal applied input synthesis filter A(z). addition, this excitation signal back into adaptive code book. output synthesis filter called nonpostfiltered speech vector. mask effects quantization coder, speech filtered through spectral postfilter.
Adaptive Postfilter adaptive postfilter shapes noise spectrum match speech spectrum, thus hiding effects quantization VSELP coder beneath formants speech signal [12]. Given speech synthesis filter, A(z), postfilter defined
H(z)
A(bwf1) A(bwf2)
(56)
where bwf1 bwf2 With bwf1 bwf2 defined bandwidth expansion factors (like bandwidth factors used perceptual-weighting filter), this filter boosts formants speech signal. Several methods exist implementation postfilter. methods outlined below. Postfilter problem with postfilter described above accentuation speech signal's spectral tilt. This results attenuation higher frequencies speech spectrum. method described requires Levinson-Durbin recursion after bandwidth expansion speech correlation coefficients. denominator coefficients converted autocorrelation coefficients then bandwidth expanded w(i) 0.923077(i Finally, these autocorrelation coefficients converted back filter coefficients Levinson-Durbin recursion. This proves computationally expensive provides quality improvement compared method described below. addition spectral shaping filter, brightness filter used boost high frequencies. speech, after passing through filter H(z), scaled remove gain introduced filter.
in(n)) Scale
(57) (n))
scale value then passed through first order low-pass filter remove discontinuities: Scale'(n) 0.9875 Scale'(n 0.125 Scale (58)
Modified Postfilter Rather than adjusting spectral tilt postfilter adjusted numerator coefficients, this method utilizes adaptive brightness filter. first reflection coefficient numerator filter used coefficient brightness filter. This method described [14]. This results same spectral effect specified method, computationally less expensive. This method used implementation.
Features VSELP
code book described above allows fast code book search conducted. Memory requirements also reduced since only basis vectors stored (not entire code book). selected code book index robust channel errors because error index changes only sign basis vectors. Most importantly, gains associated with each vectors contributing excitation vector jointly optimized quantized.
TMS320C5x Real-Time Implementation
DSPSE implementation VSELP TMS320C5x written entirely assembly code that 'C5x running MIPS. main functions, analysis synthesis, completely modular callable. memory MIPS requirements listed below. Processing Requirements table below lists processor utilization requirements TMS320C5x VSELP vocoder software. Table VSELP Vocoder Processor Requirements
MIPS Maximum 16.10 3.60 Utilization MIPS{
Memory Requirements
table below lists memory requirements TMS320C5x VSELP vocoder software. memory specifications units 16-bit words.
three on-chip memory blocks used follows:
Block special block that only segment that switched into program memory. This feature useful filtering operations such MACD instruction. Because this memory dynamically switched program data memory, static variables reside this block. However, this block used temporary memory code book searches. Block used ways. first locations used temporary scratch-pad memory. remaining locations used time-critical buffers such intermediate weighted excitation vectors stack.
Application Analysis MIPS Average 15.30 3.32 Utilization MIPS{ Synthesis
Values reflect execution from zero-wait-state external SRAM TMS320C5x internal RAM.
Function Analyzer 8.2K On-Chip 1.5K 1.1K External 0.23K 0.23K 0.42K Total 1.73K 1.33K 1.97K Synthesizer 3.32K 9.0K Full Duplex VSELP 1.55K
Table VSELP Vocoder Memory Requirements
Block used overlay local temporary variables. This strategy only saves memory also allows local variables placed fast dual-access maximum performance. Speech Coder Quality Quality measures were used compare speech output fixed point VSELP (TMS320C5x) with model reference synthesizer. input bitstream each five speakers (three male female) produced five reference files, both postfiltered nonpostfiltered. This same bitstream used input 'C5x implementations VSELP coder. resulting speech files were compared reference files using measure described below. Measurements track progress algorithmic modification, segmental measure used. segmental average each subframe's over some segment speech.
=L-1
i(n) 10(NSF
SegSNR
(59)
i(n) p(n))
where length speech segment subframes, input speech, synthetic speech. This measure used testing vocoder implementations against reference vocoder. five reference files, output synthesizer compared output reference vocoder's synthesizer. values fixed-point implementation were distributed between DTMF Performance VSELP algorithm must pass dual-tone multifrequency (DTMF) signals allow remote signaling dialing. Several DTMF files were recorded processed through algorithm. Fourier spectra were analyzed proper frequency content. addition, resulting files were used signal central office correctly initiate telephone connection.
Typical Digital Cellular Vocoder Configuration
Figure illustrates possible digital cellular system configuration. Analog speech sampled converter processed TMS320C51 digital signal processor produce VSELP coded bitstream. This bitstream passed through error-coding block protect data against channel errors. Finally, error-coded VSELP bitstream modulated transmitted cellular base station. Since digital cellular telephone full duplex, incoming data simultaneously processed reverse order produce speech. incoming signal demodulated error corrected before VSELP synthesis processing conversion.
Figure Possible Digital Cellular System Configuration
Analog Speech Cellular Signal
Serial Port
AD50 TLC32044 A/D/A Converter
TMS320C51
Port
Error Coding
Modem
Chip
Code Availability
associated software available licensing from Software Engineering Incorporated, Middlesex Turnpike, Suite 206, Bedford, 01730
References
"Vector Excited Linear Prediction (VSELP) 7950 Second Voice Coding Algorithm", Technical Description, Motorola, Inc., November 1989. Cellular System: Dual-Mode Mobile Station Base Station Compatibility Standard, IS-54 Project Number 2215, Electronic Industries Association, December 1989. Schroeder, M.R., Atal, B.S., "Code-Excited Linear Prediction (CELP): High Quality Speech Very Rates", Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, March 1985, 937-940. Davidson, Gersho, "Complexity Reduction Methods Vector Excitation Coding", Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, April 1986, 3055-3058. Gerson, I.A., Jasiuk, "Vector Excited Linear Prediction (VSELP)", IEEE Workshop Speech Coding Telecommunications, September 1989, 66-68. Gerson, I.A., "Method Means Determining Coefficients Linear Predictive Coding", U.S. Patent #4,544,919, October 1985. Cumani, Covariance-Lattice Algorithm Linear Prediction", Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, 1982, 651-654. Tohkura, Itakura, Hashimoto, "Spectral Smoothing Technique PARCOR Speech Analysis-Synthesis", IEEE Transactions Acoustics, Speech, Signal Processing, Volume ASSP-26, December 1978, 587-596. Atal, B.S., Schroeder, M.R., "Predictive Coding Speech Signals Subjective Error Criteria", IEEE Transactions Acoustics, Speech, Signal Processing, Volume ASSP-27, June 1979, 247-254.
Kroon, Deptrettere, Ed.F., Sluyter, R.J., "Regular-Pulse Excitation: Novel Approach Effective Efficient Multipulse Coding Speech", IEEE Transactions Acoustics, Speech, Signal Processing, Volume ASSP-34, October 1986, 1054-1063. Linde, Buzo, Gray, R.M., Algorithm Vector Quantizer Design", IEEE Transactions, Communications Volume COM-28, January 1980, 84-95. Chen, Juin-Hwey, Gersho, Allen, "Real-Time Vector Speech Coding 4800 With Adaptive Postfiltering", Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, April 1987, 51.3.1-51.3.4. Kemp, Sueda, Tremain, Evaluation 4800 Voice Coders", Proceedings IEEE International Conference Acoustics, Speech, Signal Processing (ICASSP), Glasgow, 1989, 200-203. Fenichel, Proposed "Federal Standard 1016 (Second Draft)", National Communications System, Office Technology Standards, Washington, 20305-2010, November 1989. Campbell, Welch, Tremain, Expandable Error Protected 4800 CELP Coder", Proceedings ICASSP, Glasgow, 1989, 735-738. Kroon, Atal, Improving Performance Pitch Predictors Speech Coding Systems", Abstracts IEEE Workshop Speech Coding Telecommunications, 1989, 49-50. Kroon, Atal, "Strategies Improving Performance CELP Coders Rates", Proceedings ICASSP, 1988, 151-154. Campbell, Tremain, Welch, "The kbps Standard (Proposed Federal Standard 1016) Advances Speech Coding", edited Atal, Cuperman, Gersho, submitted Kluwer Academic Publishers, 1990. Macres, "The First Real-Time Implementation U.S. Federal Standard 4800 CELP version 3.1", submitted Proceeding Speech Technology '90, 1990. Parsons, T.W., Voice Speech Processing, McGraw-Hill, York York, 1987. Kemp, Sueda, Tremain, "Processing Military Government Speech Technology '89", Media Dimensions, 1989, 86-90.
U.S. Digital Cellular Error-Correction Coding Algorithm Implementation TMS320C5x
Mansoor Chishtie Digital Signal Processing Applications Semiconductor Group Texas Instruments Incorporated
Abstract
Programmable digital signal processors commonly used U.S. digital cellular terminal designs. digital cellular transmitters employ convolutional codes protect against channel-induced errors. Receivers typically Viterbi decoders syndrome checks verify that decoded data contains errors. This paper presents selected implementation examples error-protection correction functions various cellular data channels using TMS320C5x digital signal processor family.
Introduction
Programmable DSPs widely used U.S. digital cellular (USDC) radio designs. primary function DSPs these designs baseband signal processing. However, many designs also using newer DSPs system coordinator radio, task typically performed microcontroller. This trend caused system care-abouts cost, power, small form factor, newer generations DSPs (such TMS320C5x family) that have architectures suitable microcontroller-type functions. several signal-processing-intensive tasks that digital cellular radio needs perform error protection correction. IS-54 voice channels transmit voice control information digital form. Although these radio links primarily used digital voice transmission (VSELP), portion channel capacity reserved control information. This relatively slow bit-rate link used background control information such broadcast messages, mobile-assisted handoffs, etc. This called slow associated control channel (SACCH) IS-54 terminology. Another type signaling channel called fast associated control channel (FACCH). However, FACCH messages sent simultaneously with voice data. They replace compressed voice data whenever necessary. Figure shows these messages multiplexed with voice data. Figure Voice Control-Channel Multiplexing Over Time Slot
DVCC/SYCH Data FACCH Data kbps Speech Data SACCH Data
16.2 kbps
These three digital data channels employ extensive error-protection correction mechanisms protect most transmitted information. Convolutional codes, codes, bit/frame interleaving techniques used this purpose. convolutional coding schemes used these three channels identical require slightly different decoding methods employed receivers. Despite these minor differences, basic decoding algorithm used three channels usually Viterbi algorithm. rest this paper, these channel formats explained separately, suitable decoding scheme presented, implementation details discussed.
VSELP Channel Format
VSELP encoder compresses digitized speech from kbps 7.950 kbps. Additional information added error protection increase total data transfer rate kbps. VSELP algorithm operates frame-by-frame basis which each speech frame duration. VSELP encoder generates bits compressed speech each speech frame. These bits grouped into classes: class-I bits that need error protection class-II bits that sent without error protection. Class-I bits protected from channel-induced errors applying convolutional encoding. Furthermore, error detection also provided applying 7-bit code most perceptually significant class-I bits. Finally, this 260-bit speech frame interleaved over time slots protect against burst errors. Figure Error Protection VSELP Data
VSELP Voice Encoder Systematic Generator 7-Bit Framed Convolutional Encoder Frame Interleaver
Rate-1/2
Class
Class
Figure Convolutional Encoder VSELP Data
Input
VSELP convolutional encoder rate-1/2 framed encoder with constraint length (denoted frame size bits (see Figure which consists class-I bits, 7-bit CRC, tail bits. Both initial final states trellis diagram this encoder consists states (that with each state symbol interval connected states next time interval basic building block this trellis shown Figure Figure Representative Trellis Section VSELP Convolutional Encoder
State State
State
State Time
rate-1/2 encoding scheme, each state linked states previous time interval, shown Figure Viterbi algorithm operates received data expanding trellis over frame length symbol intervals. Refer general Viterbi algorithm descriptions. 32-element accumulated cost metric where each element corresponds state. Each link from state
state transition cost associated with instance, transition cost from state state Figure These transition costs, which computed symbol rate, reflect current channel conditions. Each transition cost indicates probability state state transition over symbol interval. Consider Figure where state time interval reached from either state state time interval Viterbi algorithm selects more likely transition into state comparing total accumulated cost possible links. accumulated cost each link computed adding current transition cost previous accumulated cost. example, accumulated costs links entering state Figure are: new_acc_cost old_acc_cost new_acc_cost old_acc_cost +16]
smaller values selected corresponding link retained further processing next time interval. other candidate discarded. This process selecting transition entering state performed states each symbol interval. Path history every state maintained entire 89-symbol-long frame. When frame processed completely, state last time interval selected, associated path considered most likely received path. This path traced find most likely received sequence. shown Figure encoder pads five tail bits (all each message frame. This ensures that last encoder state always Additionally, initial state encoder also definition. This requires special consideration decoder during initialization accumulated cost metric beginning each frame. assure that state selected algorithm beginning each frame, initialized with lower cost value than that other states. This algorithm implemented more efficiently underlying symmetry trellis structure used considered. shown Figure pair states symbol interval connected another pair states next interval with other connections rest trellis. Therefore, state transitions during symbol interval uniquely broken down into butterfly-like structures similar Figure Furthermore, only transition cost values associated with four links each butterfly Figure some implementations, always equal -My, which leads further simplification structure). This symmetrical structure allows subroutine that will operate butterfly time, computing accumulated cost metrics, selecting best transition, storing path history. This subroutine macro) invoked times each symbol interval update state transitions. Example lists pseudocode this function.
Example Pseudocode Trellis Expansion
Acc_Metric1[n] Curr_M[x] AccB
Acc_Metric1[n+16] Curr_M[y] min(Acc,AccB) Acc_Metric2[m] (Acc AccB) then shift Trans_Tbl[i] else shift Trans_Tbl[i] Acc_Metric1[n] Curr_M[y] AccB Acc_Metric1[n+16] Curr_M[x] min(Acc,AccB) Acc_Metric2[m+1] (Acc AccB) then shift Trans_Tbl[i+1] else shift Trans_Tbl[i+1]
pseudocode shown above performs necessary computations states, similar butterfly structure shown Figure There accumulated cost metrics used code, Acc_Metric1[] Acc_Metric2[]. contains previous cost metrics other used store accumulated cost metrics. each symbol interval, roles arrays reversed. Only array elements need accessed subroutine. offsets between those elements always arrays, respectively. This allows simple indexing these arrays regardless which state currently being accessed. Similarly, only current metric values Curr_M[] accessed function. offset between these elements also made equal this array form circular buffer. Finally, since path history stored states time elements transition table Trans_Tbl[] that need accessed also offset Considerable coding efficiency gained taking into account these structural symmetries trellis butterfly. shown pseudocode above, accumulator accumulator buffer used hold total accumulated cost links. TMS320C5x DSPs support special instructions select smaller larger) values. CRLT instruction conditional-execute instruction (XC) used this implementation select lower cost link update accumulated cost array transition table. Since accumulated cost arrays accessed only steps indirect addressing modes postincrement postmodification index used step efficiently through table. current transition cost array, Curr_M[], consists four elements representing four symbols rate-1/2 encoder. circular buffers, each containing elements. Example code listing shows function implemented 'C5x assembly code. macro that invoked times update states time interval.
Example Trellis Expansion Macro 'C5x Assembly Code
Entry Conditions: INDX= AccMa[n] ;n=0.31 CurrMPtr CurrM[i] ;i=0.3 Circ.buffers: CurrM[0.1] CurrM[2.3] AccMb[m] ;m=0.31 Trn[k] ;k=0.(6*32) Exit Conditions: AccMa[n+1] CurrMPtr CurrM[i] AccMb[m+2] Trn[k+2] Texpand .macro CurrMPtr lacc *0+,CurrMPtr load AccM1[n] *+,ar1 CurrM[x] sacb lacc *0-,CurrMPtr load AccM1[n+16] *,ar3 CurrM[y] crlt change crgt correlation type metric sacl *+,ar4 min(path1,path2) AccM2[m] lacc load Trn[i] path1>path2 shift Trn[i] sacl *+,ar1 save Trn[i] lacc *0+,CurrMPtr load AccM1[n] *+,ar1 CurrM[y] sacb lacc *0-,CurrMPtr load
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