Kevin McCoy Enterprises Mansoor Chishtie Digital Signal Processing App

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Kevin McCoy Enterprises Mansoor Chishtie Digital Signal Processing App

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Digital Voice Echo Canceler Implementation TMS320C5x
Kevin McCoy Enterprises Mansoor Chishtie Digital Signal Processing Applications Semiconductor Group
SPRA142 October 1994
Printed Recycled Paper
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
Introduction
This voice echo canceler implementation TMS320C5x based similar implementation TMS320C2x [1]. This application report outlines differences between implementations highlights specific 'C5x features that support efficient echo canceler implementation. This application report extends 'C2x report with description 'C5x implementation algorithm. highly recommended that read both reports complete details theory algorithm used adaptive filtering echo cancellation. Although basic algorithm same, 'C5x implementation considerably different from that 'C2x take advantage 'C5x architecture. These performance improvement techniques discussed detail this application report. hardware platform used testing 'C5x echo canceler software consists 'C5x software development system (SWDS) analog front (AFE) board. SWDS plug-in card, which used debug 'C5x code real time. necessary hardware hooks allow efficient message-passing scheme between 'C5x host board acts analog interface 'C5x SWDS. made codecs, telephone hybrid transformers, clock generation logic near-end far-end line interfaces. Although software designed SWDS-AFE platform, very little modification required adapt program different target board1. current implementation simulates following functions software:
Near-end round-trip delay Far-end round-trip delay Near-end echo generation
near-end round-trip delay directly affects performance echo canceler. This time delay tail circuit (see Table details) simulated software order analyze echo canceler performance. far-end round trip delay delay forward circuit. echo generation implemented software. addition these simulations, message-passing scheme supported 'C5x interface host SWDS hardware. This allows monitor echo canceler performance real time. These features provided fine-tune software performance according each applications requirement. They turned using software switches (see Table page 197) during assembly time.
'C5x Device Features Used This Implementation
'C5x architecture based industry-standard TMS320C25 architecture. 'C5x assembly language superset TMS320C25 assembly language. However, 'C5x enhanced pipelined architecture that allows execute instructions more than twice speed 'C2x. addition, 'C5x more powerful instructions that allows highly efficient algorithm implementation. Many these enhanced features used this echo canceler implementation. rest this section highlights various features 'C5x architecture that distinguish from 'C2x family. code examples taken from echo canceler software, general comments equally applicable algorithm.
Editor's note: This necessary since 'C5x SWDS longer available from Texas Instruments Incorporated. alternative development platform 'C5x evaluation module (EVM).
Dual Mapping On-Chip Memory 'C5x 1056 words on-chip dual-access memory, words more than 'C25. While this type memory more efficient use, expensive terms silicon real estate. Another type on-chip memory available 'C5x devices single-access memory. 'C53 'C51 have 3K/1K words single-access memory, while 'C50 words. This memory block mapped simultaneously program data spaces. This dual-mapping feature very useful adaptive filters, such echo path transversal filter. multiply/accumulate loops require coefficients program space, same coefficient table also accessed data space update transversal filter coefficients. Placing this coefficient table single-access memory utilizing dual-mapping feature make transversal filter implementation more efficient. Note that data-move operation (DMOV instruction) works single-access (SARAM) block, well. Zero-Overhead Loops 'C5x features zero-overhead loops, opposed 3-cycle overhead 'C25 BANZ (branch zero) loops. This makes 'C5x looped code efficient inline implementation. code Example illustrates block repeats filter taps update algorithm: Example Zero-Overhead Loops UPDATE.ASM
lacl samm rptb lacc mpya sach $block_end: num_a_iter_2 brcr $block_end-1 *,16,arl *+,ar2 ;no. iterations ;start loop ;end loop
'C25 implementation, same algorithm coded inline. Dynamic Addressing Coefficient Tables multiply/accumulate instruction (MAC) 'C25/'C5x devices fetches input samples filter from data memory takes filter coefficients from program memory. This achieves single-cycle, multiply/accumulate operation simultaneously fetching operands from memory. Most 'C25/'C5x computations carried this way. 'C25, coefficient table address specified only direct addressing mode. This adequate most applications, except where coefficient table address determined runtime. such cases, 'C5x provides register-indirect mode addressing multiply/accumulate operations. Example Echo Estimation Routine FIR.ASM
lacl samm lacc madd apac sach last_a bmar one,14 num_a_1 est_echo,1 ;update coefficient table address ;clear preg ;repeat ;multiply/accumulate ;last product ;save echo estimate
This feature used echo estimation routine, shown Example block-move-address register (BMAR), dedicated register, points location coefficient table program
memory. This feature useful when code reuse consideration. code shown Example particularly important because length location transversal filter coefficients determined runtime. Nested Loops Complex applications like voice echo cancellation often need nested loops. instance, block update algorithm echo filter taps requires nested loops: inner loop compute time-averaged correlation error each coefficient block outer loop update coefficient. This easily accomplished 'C5x nesting single-instruction repeat (RPT) inside block-repeat (RPTB) loop. Example Coefficient Update Routine TAPINC.ASM
rptb lacc sach $calc_INCs: cun0 ar2, #inc0 $calc_INCs-1 one, pun0+1,*+ *,ar2 cun0 *+,0,arl
:outer loop ;inner loop ;compute error ;save coeff update
When single-instruction repeat (RPT) loop cannot used, block-repeat loops nested with delayed-branch loops such branch-on-AR-not-zero-delayed (BANZD). eight such BANZD loops nested, each using auxiliary register loop counter. 'C25 implementation, same algorithm coded in-line. Maxima/Minima Search 'C5x features special instructions efficiently find minimum maximum) value data array. Each element array fewer bits wide. signed comparison made between accumulator accumulator buffer, smaller greater) values updates accumulator buffer. This feature advantageous near-end speech detection algorithm.
Example Near-End Speech Detection Routine NESPDET.ASM
lacl samm sacb rptb lacc sacl crgt $max: sacl max_m ;largest M(k) max_m num_m_1 brcr $max *-,0,ar2 *-,0,ar1 ;repeat count ;initialize accb search ;get partial maxima M(k)'s ;save largest M(k) accb
code loop shown Example performs functions:
finds largest far-end speech sample power estimate) from num_m most recent samples. implements time window spanning echo path delay range.
TMS320C2x, same algorithm must implemented with conditional branches. built-in 'C5x support search algorithms generates faster more elegant code. Circular Buffers Another 'C5x advantage over 'C2x support circular addressing. independent circular buffers size supported 'C5x address generation unit. They used implement FIFO buffers queues. this echo canceler application, circular buffers used hold far-end near-end receive samples implement variable delay near-to-far far-to-near signal paths. Another important circular addressing filter implementations. conventional performing computation 'C2x/'C5x devices multiply/accumulate with data-move (MACD) operation. case 'C5x, circular addressing replace data-move operation update filter taps. This faster implementation filter taps reside on-chip single-access memory external data memory. echo simulation filter employs this technique, shown Example Example Echo Simulation Filter EFILT.ASM
apac sach *,ar5; ar5,efilt_ptr ;get echo filter taps address
#(filt_len-1) ;multiply/accumulate echo_filt_end,*+ with circular addressing ;add final product one,14 ;round output sim_echo_out,1 ;save result
Delayed Branches Conditional Execution 'C2x three-deep instruction pipeline. This allows perform more operations parallel overlapping various phases instructions. 'C5x features four-deep instruction pipeline attain even higher performance. Since deeper pipelines take more cycles flush, 'C5x supports special types branches calls avoid this overhead. Normal 'C5x branches take four machine cycles, while similar instruction 'C2x takes only three cycles. However, 'C5x instructions that cause pipeline flush support delayed option that reduces overhead only machine cycles. Moreover, special case which only instructions skipped over, even faster instruction, (conditional execute), which takes only machine cycle.
code shown Example illustrates delayed branches conditional execute instructions. Example Delayed Branches NESPDET.ASM
sacl lacc lacc sacl lacc samm $chk_hang max_m absy0f max_m arl,last_m_1 2,gt absy0f max_m num_m_1 brcr ;delayed branch ;branch executes here acc<=0 then skip next instructions
Barrel Shifters Both 'C2x 'C5x families support 16-bit input prescalar 8-bit output postscalar hardware. This necessary efficient fractional arithmetic manipulation. addition these barrel-shifters input output paths, 'C5x family also features 16-bit right barrel shifter accumulator. This complements left barrel shifting provided input prescalar. code Example illustrates barrel shifters. Example Code Excerpt From MULAW.ASM
lact bsar temp_B2 #0E0h treg1,4 ;Shift left biased linear into ;Shift right ;Shift left subtract
lact instruction uses left barrel shifter transfer data accumulator, input shift determined treg1 register. following instruction, bsar, performs 16-bit right barrel shift accumulator contents. Memory-Mapped Registers Both 'C2x 'C5x have accumulator-based internal architecture. 'C2x devices, arithmetic operations performed accumulator. There data path between accumulator other registers, including auxiliary register set. Therefore, temporary data memory location must used transfer data between arithmetic logic unit (ALU) address generation unit (AGU). 'C5x architecture considerably enhanced; provides direct data path between accumulator rest registers mapping them into local data memory. also supports direct memory-to-register data transfer internal registers. code Example illustrates 'C5x memory-mapped registers.
Example Taps Update Routine UPDATE.
update taps: splk lacc sacl lacc samm lacl samm lact samm rptb lacc mpya sach $block_end #16,indx AR1,#INCO ADA0 beta_gain treg1 num_a_2 brcr IABSY treg0 *+,ar2 $block_end-1 *,16,arl *+,ar2 ;init. index register ;init. register ;init. register ;get variable beta_gain factor ;init. temp register ;init. repeat count ;init. temp register
Parallel Logic Unit 'C5x manipulation unit runs independently from arithmetic logic unit. allows logical operations on-chip off-chip memory location (including memory-mapped registers) without modifying accumulator (ACC) accumulator buffer (ACCB). This feature, conjunction with memory mapping registers, provides 'C5x programmers more flexibility modify auxiliary registers implement software queues FIFOs. Additionally, read-modify-write operation performed parallel logic unit (PLU) instructions also used semaphore update. section code Example taken from echo canceler program. services serial port receive interrupt reading received data, transmitting data setting appropriate flags communicate with background program. Notice particular instructions setting software flags. Example Serial Port ECHOISR.ASM
rint_isr: smmr lmmr reti
#DRR_data drr,#DRR_data drr,#DXR_data #RXDATA,sp_flag #TXDATA,sp flag #ERINT,intr_flag
;get serial receive data ;send serial transmit data ;mark serial data received ;mark serial port data sent ;mark rint intr_flag
Code Data Requirement echo canceler software implementation gives maximum control over performance behavior. Various system parameters, such echo filter length, echo cancellation enable/disable mode, filter adaption enable/disable mode, represented memory variables rather than hard-coding software. This lets either:
Modify these parameters realtime supervisory software, illustrated SWDS demo program, these parameters initialization stage.
Table lists these user-defined system parameters along with their default values. modify default value parameters, edit echoequ.inc file. Table User-Defined System Parameters
Number Variable Name pd_wait echo_taps sim_echo host_comm control_flags Description Program/data wait states Transversal echo filter taps Simulated echo disable/enable Host communications disable/enable Type const const const const Default [range] [16-512] [0/1] [0/1] [0/1] [0/1] [0/1]
echo cancellation disable/enable variable residual suppression disable/enable coeff adaptation disable/enable
control_flags variable active only when host_comm Edit echoinit.asm file modify this memory variable.
Table indicates processor loading code size each software module 512-tap implementation. also indicates where each module located program memory. Most time-critical subroutines located on-chip single-access random-access memory (SARAM). auxiliary functions, such host mailbox, executed from external memory. Table Program Module Requirements
Module Name
ECHO.ASM ECHOINIT.ASM ECHOISR.ASM CYCLE.ASM EFILT.ASM FIR.ASM RESID.ASM MULAW.ASM PCALC.ASM NESPDET.ASM ONORM.ASM TAPINC.ASM UPDATE.ASM UTIL.ASM MAILBOX.ASM
Number
Description
Main module variable declarations. Initialization module. Interrupt services routines. samples. Convert µ-law linear. Poll host mailbox. echo simulation. Update delay buffers. Estimate echo. Compute error. Residual error suppressor. Linear-to-PCM conversion. Power estimate y(n) o(n). Near-end speech detection. Output normalization coefficient update. increment. filter update. Process host commands. Write monitored variables. Host mailbox.
Cycles
Total cycles 512-tap filter 1825
Code Size
Total code size words
Code Location
SARAM SARAM SARAM SARAM SARAM SARAM SARAM
Only modules that main cycle. Cycle count given taps transversal echo filter. 'C51 on-chip, read-only memory external memory. SARAM 'C51 on-chip, single-access RAM.
Data Allocation 'C51 1056 words dual-access 1024 words single-access on-chip memory. also words on-chip, read-only memory. on-chip data memory allocated various modules echo canceler software according their specific requirements. Table lists size location various data variables 512-tap implementation. coefficients echo transversal filter placed on-chip, single-access memory because dual-mapping capability. Note that these coefficients accessed both program data spaces different modules. 1024 words dual-access memory used data storage. Reference samples far-end talker reside this memory block. This makes efficient operations.
simulate delay paths between near-end far-end speakers, long buffers words each maintained external data memory. Another buffer that holds host messages resides external memory. Since three buffers noncritical paths would eventually deleted from final implementation, they placed external memory. Table 512-Tap Implementation Data Variables
On-Chip Single-Access Memory: Words words words Normalized outputs Un15 Transversal echo filter coefficients
On-Chip Dual-Access Memory: Words words words words words External Data Memory 2304 words 2304 words 2048 words Near-to-far sample delay buffer (optional) Far-to-near sample delay buffer (optional) Message buffer communications (optional) System variables Local maxima M(k) near-end speech detection Coefficient increment INC(k) Reference samples Y(k)
Code Benchmarks most computationally intensive routines this echo canceler application are:
transversal echo filter routine FIR.ASM, mean square error (MSE) computation routine TAPINC.ASM.
computational requirement these routines depends length echo transversal filter. Table shows relationship between processor loading length transversal filter. 512-tap filter, 'C5x takes only microseconds process each sample. With input sampling rate microseconds, this leaves processor with ample time system overhead. fact, 50-ns 'C5x processor implement about echo filter taps within 128-microsecond sampling period. other words, 50-ns 'C5x handle tail-end circuit delay. Table shows code benchmarks hardware platform that consists 'C51 software development system (SWDS) with analog front (AFE) board, zero-wait-state external data/program memory, 50-ns instruction cycle rate, 128-µs input sampling period, communication disabled. Table Code Benchmarks
Number Echo Filter Taps Time Required Process Sample 26.0 28.1 30.0 32.4 34.6 38.9 56.7 91.6
Echo Canceler Demonstration 'C5x SWDS primary hardware platform testing 'C5x echo canceler software (for code benchmarks) 'C5x SWDS. board communicates with 'C5x serial port codecs hybrid transformers near-end far-end telephone interfaces. board schematic shown appendix this report. demonstration software 'C5x SWDS board downloading echo.out file board running echodemo.exe file host this, type following commands prompt:
c51load echo.out echodemo.exe
control various system parameters such tail-circuit delay, transversal filter taps, echo cancellation mode, adaptation mode real time running echodemo.exe program.
Conclusion
This implementation single-channel voice echo canceler TMS320C51 highlights powerful versatile architecture that DSP. This particular algorithm first coded TMS32020. Coding same algorithm TMS320C51 shows that resulting performance improvement merely faster instruction rate 'C5x. Performance improved more than factor when enhanced 'C5x architecture fully utilized. 'C5x features used this implementation discussed detail. processor loading code data size each software module listed. Several auxiliary functions that used testing evaluation purposes discussed. details demonstration package that consists 'C51 SWDS, analog front-end board, 'C5x DSP, software given.
Acknowledgements
Texas Instruments acknowledges efforts Enterprises' project team: Kevin McCoy, Mark Sissom, Paul Kniffen.
Code Availability
associated program files available from Texas Instruments TMS320 Bulletin Board System (BBS) (713) 274-2323. Internet users access anonymous ti.com.
References
"Digital Voice Echo Canceler With TMS32020", Digital Signal Processing Applications, Volume Texas Instruments, 1986, 454. TMS320C5x User's Guide, Texas Instruments, 1991. TMS320C5x Software Development System Technical Reference, Texas Instruments, 1990. TMS320C5x Source Debugger User's Guide, Texas Instruments, 1991. TMS320 Fixed-Point Assembly Language Tools User's Guide, Texas Instruments, 1990.
Appendix: Schematic Dual-Telephone Interface TMS320C51 SWDS
TIP_FAR NMI8842 RING_FAR TIP_NEAR Near-End Circuit 182W 29C16 /PDN PWRO+ PWRO- AGND PCMOUT /TSX PCMIN DCLKR CLKR (46) CLKX (124) (45) (104) TMS320C5x Serial Port (106) (43)
NMI8842
29C16 PCMOUT /TSX PCMIN DCLKR
/PDN PWRO+ PWRO- AGND
RING_NEAR
Far-End Circuit 2.048-MHz Oscillator
74ALS163
74ALS163
74ALS164
T1-T2 Transformer Specifications Dual primary, center-tapped secondary Primary inductance kHz. Saturation current turns ratio Average winding resistance 62.5 Primary winding resistances should match within Wind secondary first; tape, then wind primary bifilar; tape, then wind rest secondary. Coefficient coupling 0.998 Pri-to-pri pri-to-sec Hipot (This single-coil, hybrid transformer.)
NOTE:
Codec Frame Generator
Enterprises. Inc.
Dual-Telephone Interface TMS320C51 SWDS

Kevin McCoy Enterprises Mansoor Chishtie Digital Signal Processing App

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