74HC4049 inverting high-to-low level shifter Product specificatio
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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC4049 inverting high-to-low level shifter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC4049 high-speed Si-gate CMOS device compatible with "4049" "4000B" series. specified compliance with JEDEC standard 74HC4049 provides inverting buffers with modified input protection structure, which diode connected VCC. Input voltages therefore used.
74HC4049
This feature enables inverting buffers used logic level translators, which will convert high level logic level logic, while operating from voltage power supply. example logic ("4000B series") converted down logic. actual input switch level remains related same mentioned family characteristics. same time each part used simple inverter without level translation. APPLICATIONS Converting logic ("4000B" series) down logic.
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/tPLH Note used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency output load capacitance supply voltage VCC2 outputs ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay input capacitance power dissipation capacitance buffer note CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
DESCRIPTION n.c. SYMBOL data outputs data inputs ground connected NAME FUNCTION positive supply voltage
74HC4049
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
74HC4049
Fig.5 Fig.4 Functional diagram.
Input protection HC4049. Single sided thick oxide field effect metal gate transistor input protection.
Fig.6 Logic diagram (one level shifter).
FUNCTION TABLE INPUT Notes HIGH voltage level voltage level OUTPUT
December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
RATINGS Limiting values accordance with Absolute Maximum System (IEC 134) Voltages referenced (ground SYMBOL -IIK ±IOK ±ICC; ±IGND Tstg PARAMETER supply voltage input voltage range input diode current output diode current output source sink current standard outputs current types with: standard outputs storage temperature range power dissipation package Ptot plastic plastic mini-pack (SO) RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL Tamb Tamb PARAMETER min. supply voltage input voltage range typ. max. +125 1000 1000 UNIT MIN. -0.5 -0.5 MAX. UNIT -0.5
74HC4049
CONDITIONS
-0.5 +0.5 -0.5 +0.5
+150
temperature range: +125 74HC above derate linearly with mW/K above derate linearly with mW/K
CONDITIONS
operating ambient temperature range operating ambient temperature range
characteristics 10.0 15.0
input rise fall times
December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
CHARACTERISTICS 74HC Voltages referenced (ground Tamb (°C) 74HC SYMBOL PARAMETER min. HIGH level input voltage level input voltage HIGH level output voltage outputs 3.15 typ. 1.35 3.84 5.34 0.26 0.26 0.33 0.33 +125 UNIT
74HC4049
TEST CONDITIONS
OTHER
max. min. max. min. max. 3.15 1.35 3.15 1.35
HIGH level 3.98 output voltage 5.48 standard outputs level output voltage outputs level output voltage standard outputs input leakage current
quiescent supply current
20.0
40.0
December 1990
Philips Semiconductors
Product specification
inverting high-to-low level shifter
CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay output transition time typ. max. min. max. +125 UNIT min. max.
74HC4049
TEST CONDITIONS WAVEFORMS Fig.7
tTHL/ tTLH
Fig.7
WAVEFORMS
50%; VCC. HCT:
Fig.7 Waveforms showing input (nA) output (nY) propagation delays output transition times.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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