Donnie Garcia Scott Pape 8/16 Applications Systems Engineering Austin,

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AN2493/D Rev. 9/2003 MC9S08GB/GT Power Modes
Donnie Garcia Scott Pape 8/16 Applications Systems Engineering Austin, Texas
Introduction
This application note guide using MC9S08GB/GT microcontroller achieve power-consumption. MC9S08GB/GT member low-cost, high-performance HCS08 Family 8-bit microcontrollers. Some features this family include 40-MHz HCS08 CPU, enhanced instruction set, background debug controller (BDC) that provides easy interface in-system real-time debugging. Please device data sheet, Motorola document MC9S08GB60/D, more complete description features this part. Always refer data sheet most current specification MC9S08GB/GT microcontroller additional features that pertain specifically achieving power-consumption. These features provide great deal flexibility user used provide ideal conditions many different types applications.
System Clock Generation
system clock generated from external (crystal, resonator, square wave) internal sources. Also, frequency-locked loop (FLL) stage used boost external internal clock source higher frequency. MC9S08GB/GT ability range kHz-100 kHz) high range MHz-16 MHz) crystal resonator. Upon system startup (from stop reset) uses internal clock source, which eliminates need long startup time. Depending application requirements, power reduced selecting best system clock generation option. Table shows configuration considerations among different clock modes. more information about clock options MC9S08GB/GT refer AN2494/D, Configuring System Peripheral Clocks MC9S08GB/GT.
Motorola, Inc., 2003
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Table Configuration Consideration
Clock Reference Source Internal
(FEI) Engaged-Internal Reference fBus MHz. Medium power (will less than oscillator range high) Medium clock accuracy (After trimmed) Lowest system cost external components required) (SCM) Self-Clocked Mode This mode mainly provided quick reliable system startup. fBus (default). fBus (via filter bits). Medium power Poor accuracy. off. open loop.
Clock Reference Source External
(FEE) Engaged-External Reference fBus Medium power (will less than oscillator range low) Good clock accuracy Medium/High system cost (crystal, resonator external clock source required) off.
Engaged
Bypassed
(FBE) Bypassed-External Clock fBus range when crystal resonator used. Lowest power Highest clock accuracy Medium/High system cost (Crystal, resonator external clock source required) off. off.
typically consumes typically consumes depending upon output frequency. minimum power consumption minimum jitter, choose small possible.
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AN2493/D Introduction
Modes Operation
After reset, normal mode operation mode which active peripherals enabled. executing WAIT instruction, enters wait mode. wait mode, power reduced because clocked. reduce power consumption further, stop mode used. When STOP instruction executed, three stop modes will entered. Stop1, stop2, stop3 each provide different levels operation that reduce power consumption. table below describes stop mode behaviors.
Table Stop Mode Behaviors
Mode
CPU, Digital Peripherals FLASH Standby
Disabled
Regulator
Pins
Stop1 Stop2 Stop3
Standby Standby
Standby(2)
Optionally
Standby Standby
Reset States held States held
Optionally Optionally
Disabled Disabled
Either stop mode power-down mode depending state ATDPU. Crystal oscillator configured stop3. Please registers.
Real-Time Interrupt (RTI)
used exit stop2 stop3. stop3, configured external internal reference. stop3, using internal reference will reduce power consumption further than using external reference. stop2, only internal reference used. module configured achieve real-time interrupts between 1.024 1-kHz reference tolerance about ±30%, thus wakeup times will approximate when internal reference used RTI.
Voltage Detect (LVD)
MC9S08GB/GT ability enable disable voltage detection when stop3 mode. important note that voltage detection enabled stop, only stop mode that used stop3. LVDSE SPMSC1 set, then upon execution STOP instruction, stop3 will entered regardless state PPDC bits SPMSC2.
Operating Voltage Ranges
MC9S08GB/GT specified operate from down (see Table lower than 2.08 operation, maximum speed should reduced lower. lower voltages, resulting power consumption will reduced modes.
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Table Characteristics (Temperature 85°C Ambient)
Parameter Supply voltage (run, wait, stop modes) fBus fBus Symbol 2.08 Typical Unit
Internal Voltage Regulator
MC9S08GB/GT uses internal voltage regulator provide about internal power supplies most peripherals. When falls below regulator bypassed. This regulation keeps operating currents from rising very much rises above regulator always when wait modes. stop2 stop3 modes, regulator into state that results looser regulation, thereby saving power. stop1, regulator turned off.
Description Low-Power Modes
Stop Modes With introduction HCS08 Family MCUs, forms stop mode were introduced, resulting three total forms stop. three modes stop referred stop1, stop2, stop3. Stop3 functionally equivalent stop mode HC08 MCUs, while stop1 stop2 forms. Stop1 full power-down mode which internal voltage regulator turned off. This will provide lowest possible standby current MCU. stop1, internal circuitry powered down, including registers. This means that contents registers will lost upon entering this mode. Also, peripherals left enabled stop1, including LVD, RTI, KBI, ATD. clocks left enabled internal device. Internal power driver turned off, output pins will pulled ground. pins will revert high-impedance inputs. Exiting stop1 accomplished asserting either RESET low. will always active this mode regardless configured before entering stop1. Internal pullups automatically enabled RESET stop1 mode. Upon exiting stop1, registers will configured occurred. will fetch reset vector begin code execution whether RESET used wake MCU.
Stop1
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AN2493/D Description Low-Power Modes
Stop2
Stop2 will provide lower standby currents than stop3, higher than stop1. Stop2 partial power-down mode which internal voltage regulator goes into "loose" regulation mode, thereby reducing current consumption reducing power output regulator. stop2, remains powered states pins latched their state prior entering stop2. Pins configured inputs remain inputs output pins drive last known state. However, other peripherals that powered voltage regulator powered down cannot used, such KBI. also turned therefore cannot used.
Although pins retain their state stop2, registers powered down. Therefore, values register such SCI, timer, port data preserved should copied into before entering stop2. Exit stop2 asserting either RESET low. will always active this mode matter configured before entering stop2. must enabled prior entering stop2 mode. addition RESET pin, stop2, enabled used wakeup without depending external input. However, only internal 1-kHz oscillator used clock source stop2. When event occurs, stop2 exited occurred. with stop1, exiting stop2 results registers resetting their values with following exception. PPDF SPMSC2 register pins remain latched their current state until logic written PPDACK SPMSC2. PPDF used flag branch stop2 recovery routine. order maintain current state pins, copy saved register values back into their respective locations before writing PPDACK bit. register restored will revert value corresponding pins will also revert their state. Upon stop2 recovery, normal operation peripherals will begin until PPDACK been written because will latched. Stop3 Stop3 HCS08 Family devices functionally equivalent stop mode HC08 Family MCUs. states pins latched state they were prior executing stop command. stop3, there couple options that available other stop modes. Stop3 only stop mode where protection enabled during stop. fact, LVDSE SPMSC2 register set, only stop mode that entered stop3. Also, OSCSTEN that individual clock generators enabled clock rest turned off. OSCSTEN option used avoid long oscillator startup times necessary. This also allows external clock source reference real-time
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AN2493/D
interrupts. time critical applications using external reference provides precise intervals. Exit from stop3 less intrusive than exits stop1 stop2. interrupt source such IRQ, KBI, used exit stop3, services interrupt then continues operation instruction that follows stop instruction. necessary initialize peripherals after exiting stop3. Stop3 also exited asserting RESET pin. this case will fetch reset vector registers peripherals will placed their reset state.
Wait
Wait mode consumes less power than mode. this mode, clocks turned reduce power. other peripherals enabled wait. this mode, interrupt used exit wait. common application would execute WAIT command then wait interrupt that operation continue. After exit from wait interrupt, services interrupt then continues operation instruction that follows WAIT command.
Using Power Modes
order enter three stop modes, three bits registers must configured properly. system options register (SOPT), stop mode enable (STOPE) must logic This register write-once after reset, care must taken configure other options same write. STOPE clear attempt execute STOP instruction made, instruction treated illegal opcode reset forced. system power management status control register (SPMSC2), bits, power down control (PDC) partial power down control (PPDC) used determine which three stop modes entered when STOP instruction executed. addition, able stop2 stop1 mode, LVDSE SPMSC1 must cleared. this cleared only stop mode that entered stop3. Table summarizes source exit condition upon exit each stop modes.
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AN2493/D Using Power Modes
Table Stop Mode Selection Source Exit
SPMC2 Mode Stop1 Stop2 Stop3 PDDC Don't Care Source Exit reset IRQ, reset, IRQ, reset, RTI, Condition Upon Exit (PPDF SPMSCR) reset used, then POR; else, normal operation continues from interrupt vector
Stop1
When logic PPDC logic stop1 entered upon execution STOP instruction. Stop1 will result lowest possible current drain powering internal voltage regulator on-chip peripherals that powered Also, pins memories turned off. Stop1 best suited situations where power consumption greatest importance required wake itself Only external falling edge either RESET will wake from this mode. Since majority powered down during stop1, minimal software necessary stop1 entry. main concerns enable STOP instruction SOPT register select stop1 with SPMSC2 register. There need configure individual peripherals since they will automatically powered down upon entry stop1. Since pins reset state, pins will revert inputs pullups will disabled. external oscillator enabled stop mode (OSCSTEN control register stop1 entered, this ignored clocks will powered down. module enabled stop mode, stop1 cannot used. Attempting enter stop1 with enabled stop will result entering stop3 mode instead. RESET pins will automatically configured wakeup pins stop1. software external pullups necessary. Upon waking from stop1, will start from POR. Since registers revert their state powered down, there mechanism indicate that just woke from stop1. Since results system clock being driven internal 4-MHz clock, stop recovery occurs fairly quickly allows rapid code execution perform register restoration before jumping back into normal program flow. longest delay time necessary internal
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voltage regulator turn from state stabilize. Typical delay times from falling edge wakeup signal first instruction being executed about Stop2 When PPDC both logic stop2 entered upon execution STOP instruction. Stop2 will result higher current consumption than stop1, less than stop3. kept powered maintain values pins latched their current state. There several considerations when using stop2 ensure proper operation:
must enabled pulled externally. must disabled stop (LVDSE using RTI, only internal clock source functions stop2. OSCSTEN effect stop2. This clock reference will always powered down. Only remains powered; other registers will reset upon wakeup. PPDF flag must always cleared before pins modified from their stop2 entry state.
must enabled writing enable (IRQPE) status control (IRQSC) register. Failure this will result waking from stop2 immediately after entering stop unless external pullup placed pin. interrupt does need enabled (IRQIE IRQSC). RESET will automatically configured wakeup stop2. software external pullups necessary. module enabled stop mode, stop2 cannot used. Attempting enter stop2 with enabled stop will result entering stop3 mode instead. When using module stop2 wakeup source, internal clock source must used since external clock source will remain powered stop2. external oscillator enabled stop mode (the OSCSTEN control register stop2 entered, this ignored clocks will powered down. always, stop instruction must enabled SOPT register PPDC bits SPMSC2 register must logic peripherals already mentioned require special handling since they will automatically powered down upon entry stop2.
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AN2493/D Using Power Modes
Stop2 best suited situations where lowest possible power consumption required, contents states must maintained. Since module stop2, also wake without external input. Upon waking from stop2, will start occurred. However, unlike stop1, PPDF SPMSC2 register used indicate that woke from stop2 instead standard POR. using PPDF PPDACK, user code save desired register values into before entering stop2 restore these values after waking port registers saved restored before PPDACK written logic then states will preserved. port that reconfigured latched stop2 state will revert reset state. Also, peripheral reconfigured pre-stop2 state will revert reset state. typical code execution sequence stop2 entry exit would
Constant declarations IRQSCinit: enable SOPTinit: enable STOP SRTISCinit: enable select 1.024 timeout SPMSC2init: PPDC both SPMSC2st2: PPDACK, PPDC both PPDFmask: mask PPDF SPMSC2 System initialization after reset Start: SPMSC2 Check coming from stop2 #PPDFmask Stop2rec branch recovery code #SOPTinit Else, treat normal SOPT init System Options #SPMSC2init SPMSC2 init SPMSC2 #IRQSCinit,IRQSC init Entering stop with enabled SaveRegs #SRTISCinit ;Enable module SRTISC stop After times out, will execute code restarts reset vector this time PPDF will Start: SPMSC2 #PPDFmask Stop2rec LoadRegs SPMSC2st2 SPMSC2 Main
Stop2rec:
Begin Main code execution Main:
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Note that constant SPMSC2st2, addition setting PPDACK clear PPDF flag, also sets PPDC bits logic This because these bits write-once. Failure these bits this write would result next STOP instruction going into stop3 mode instead stop2. user may, course, elect enable either stop1 stop3 instead stop2 this point, desired. case with stop1, results system clock being driven internal 4-MHz clock, stop recovery occurs fairly quickly, allowing rapid code execution restore registers. delay regulator return full regulation state same stop1, about
Stop3
Though stop3 mode does lead lowest possible IDDs, very versatile least intrusive stop modes. Stop3 entered long SPMSC2 Also, important note that enabled stop entry into background debug mode enabled (ENBDM BDCSCR set), only stop mode that entered will stop3. When ENBDM stop instruction executed, system clocks background debug logic remain active background debug communication still possible. Stop3 should used when user depending easy exit from stop mode. Stop recovery time typically around when using internal clock FLL. applications that boost reference frequency, stop3 advantage preserving previous settings when recovering from stop3 with interrupt. This means that upon stop recovery, will with system clock configuration predefined. Unlike other stop modes, stop3 exited with interrupt, there need initialization reconfiguration. When interrupt occurs, will begin processing with stacking operations leading interrupt service routine. Upon command interrupt service routine, will resume instruction immediately following stop command. Another situation where necessary stop3 mode where keyboard interrupt (KBI) module must used. MC9S08GB/GT eight pins which used wake part from stop3. module cannot used stop1 stop2, some applications, necessary have multiple sources exit from stop.
Stop Recovery Times
Stop recovery times stop1 stop2 very similar. recovering from stop1 stop2, internal voltage regulator needs time re-establish regulation. this reason, stop1 stop2 recovery times dependent VDD. stop recovery time approximately stop recovery time approximately measurements shown Table were taken using M68DEMO908GB60 board power modes code.
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AN2493/D Typical IDDs Specific Low-Power Modes
Table Approximate Stop Recovery Times Stop1 Stop2
Mode Stop1 Stop2
Stop3 startup time vary greatly depending clock configuration used. minimum stop3 recovery time will around regardless VDD. This stop recovery time will seen except when configured bypassed-external clock mode (FBE). typical measurement room temperature. mode stop3 recovery time will vary based external clock frequency. example, when 32-kHz crystal used, stop recovery will occur until crystal stabilized. From bench measurements, stop3 recovery time when 32-kHz crystal used approximately ms-300 OSCTEN (oscillator enabled stop mode) then recovery time becomes 2.42 This delay 16-cycle count interrupt fetching overhead. external clock frequency higher, stop recovery times will reduced. Measurements stop recovery time with 32-kHz crystal worst case because long start-up time frequency crystal. reset used exit stop3, stop recovery time will approximately same stop1 stop2. Table stop3 recovery time data. Table Stop3 Approximate Stop Recovery Time Measurements
Clock Source Internal clock used reference External crystal (OSCTEN External crystal (OSCTEN Recovery Time ms-300
Typical IDDs Specific Low-Power Modes
Table Table contain data taken M68DEMO908GB60 board. code following tables used template enter different stop modes.
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Table Typical Room Temperature 3.12
Mode Stop1 Stop2 Stop2 with enabled Stop3 Stop3 with enabled Current 14.5
Stop3 with enabled with external 32-kHz source
Table Typical Room Temperature
Mode Stop1 Stop2 Stop2 with enabled Stop3 Stop3 with enabled Stop3 with enabled with external 32-kHz source Current 10.5
Creating Code Achieve Power-Consumption
Here some important notes about create code that achieve power-consumption. pins should initialized either outputs driving inputs with pullups enabled. This will ensure that there extra current consumption floating inputs. achieve lowest possible IDDs, should disabled stop mode. stop mode code executed, thus risk low-voltage causing code runaway minimal. However, this risk increased when used stop2 stop3. Stop1 stop2 will entered enabled stop, stop3 application code should ensure that disabled stop. same true OSCSTEN bit. lowest power-consumption will reached oscillator allowed continue stop mode. dealing with stop2 recovery, important note that registers I/Os will latched until PPDACK set. example, port pins will able change state until PPDACK set. Below assembly code listing software used take measurements this application note.
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AN2493/D Typical IDDs Specific Low-Power Modes
Metrowerks HC08-Assembler COPYRIGHT METROWERKS 1987-2003 Rel. Obj. code Source line Copyright Motorola 2003 ;*File name: Low_Power_Modes.asm Current Release Level: ;*Last Edit Date: 06-May-03 Classification: ;*Include Files: 9S08GB60v1r3.inc MC68HC9S08GB60 definitions ;*Assembler: Assembler V5.0.13 Version: 3.16 ;*Target Device: MC68HC9S08GB60 ;*Documentation: GB60 Power Modes AN2493 Author: Donnie Garcia First Release: 06-May-03 Update History: Date Author Description Change 5-06-03 Initial Release This code used along with M68DEMO908GB60 board demonstrate Stop Modes measurements AN2493 where taken using this code Demo Board Measurement purposes headers/jumpers (Except Power_Sel jumper) were removed from demo board When using Stop2 Stop1 order re-establish connection PTG0/BKGD should held power then released. StopSelect WakeSelect used configure code test Stop1 StopSelect %00000001 WakeSelect Dont Care test Stop2 StopSelect %00000010 WakeSelect %00000000 test Stop2 StopSelect %00000010 WakeSelect %00000010 test Stop3 StopSelect %00000100 WakeSelect %00000001 test Stop3 Internal StopSelect %00000100 WakeSelect %00000010 test Stop3 External StopSelect %00000100 WakeSelect %00000100 include "9S08GB60v1r3.inc"
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0000 0004
;SELECT STOP MODE WAKE SOURCE HERE StopSelect: %00000100 ;Select Stop Mode Here ||+-Stop1 Mode selected |+-Stop2 Mode selected +-Stop3 Mode Selected more than mode selected lowest stop mode will selection made stop3 chosen WakeSelect: %00000010 ;Select Method wake (Stop2,3) ||+-KeyBoard wake selected (For Stop3) ||+-RTI Internal wake selected +-RTI external wake Selected (For Stop3) selection made selected
0000 0002
0000 0014
;IMPORTANT REGISTER INITS initSPMSC1: %00010100 ;Disable stop |||||| |||||| |||||| |||||+-LVDE Enable ||||+-LVDSE Disable stop |||+-LVDRE Enable reset protection ||+-LVDIE |+-LVDACK +-LVDF initSPMSC2: %00000000 ;This register sets stop mode |||||||| |||||||+-PPDC ||||||+-PDC |||||+-PPDACK ||||+-PPDF |||+-LVWV ||+-LVDV |+-LVWACK +-LVWF
0000 0000
0000 0063
initSOPT:
%01100011 ;COP STOP enable controls |+-RSTPE Reset enabled +-BKGDPE BKGD enabled ||+-STOPE STOP allowed |+-COPT long timeout 2^18 +-COPE
0000 003C
initICGC1:
%00111100 ;Clock Generator Control 0|||||xx this setting xtal ||||+-OSCSTEN keep stop mode
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AN2493/D Typical IDDs Specific Low-Power Modes
|||+-CLKS0 select engaged external ||+-CLKS1 (FEE) mode |+-REFS enable oscillator amplifier +-RANGE 32.768 kHHz crystal
0000 0021
initICGC2:
%00100001 ;Clock Generator Control |||||||| should write MFDx before ICGC1 |||||||+-RFD0 ||||||+-RFD1 post-PLL divider |||||+-RFD2 ||||+-LOCRE loss clock doesn't reset |||+-MFD0 ||+-MFD1 loop multiplier |+-MFD2 +-LOLRE loss lock doesn't reset
0000 0000
RamStart StopSet WakeSet PTFD_STORE ;Used select stop mode ;Used select Wait Mode ;Used store
0080 0081 0082
START: 1080 1082 1802 1085 1087 1809 108A 180A 108D 108F
RomStart
#initSOPT SOPT ;Disable enable STOP #initSPMSC1 SPMSC1 ;Disable stop SPMSC2 ;how here? #mPPDF ;was wake-up from STOP2? Stop2Recovery normal reset Stop2 Recovery needed
;This begins path normal reset (Not stop2 recovery) INIT: ;FIRST setup SPMSC2 proper stop mode #StopSelect StopSet brset brset Set_Stop3: 109B StopSelectDone ;Reset state SPMSC2 selects stop3 0,StopSet,Set_Stop1 1,StopSet,Set_Stop2
1091 1093 1095 1098
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Set_Stop2: 109D 109F 10A1 180A initSPMSC2 ;enable stop2 #(mPDC|mPPDC) SPMSC2
10A4 Set_Stop1: 10A6 10A8 10AA 180A
StopSelectDone
initSPMSC2 ;enable stop1 #(mPDC) SPMSC2
StopSelectDone: Stop2Recovery: ;Initialize before PDACK ;Now selected wakeup source #WakeSelect WakeSet brset 0,WakeSet,InitKBI brset 1,WakeSet,InitRTIint brset 2,WakeSet,InitRTIext WakeSelectDone InitKBI: 10BC 10BE 10C0 10C2 10C4 InitRTIint 10C6 10C8 1808 10CB InitRTIext 10CD 10CF 10D2 10D5 10D8 1808 brclr WakeSelectDone #$37 ;External clock ;Enable Interrupts long timeout #$17 ;Enable Interrupts timeout SRTISC WakeSelectDone bset bset bset bset KBIPE4,KBIPE ;Enable Keyboard KBIE,KBISC ;Enable Keyboard Interrupts KBACK,KBISC ;Clear Pending Keyboard Interrupts PTAPE4,PTAPE ;Enable Pullup Keyboard WakeSelectDone
10AD 10AF 10B1 10B4 10B7 10BA
SRTISC #initICGC2,ICGC2 ;sets divider #initICGC1,ICGC1 ;32.768 4.166mHz rate LOCK,ICGS1,*
;Initialize achieve Power Init_IO 10DB 10DE 10E1 10E4 10E7 10EA #mIRQPE,IRQSC ;pull-up enable ;Make unused Outputs Driving #$EF,PTADD ;ADDR #$ff,PTBDD ;BDDR #$ff,PTCDD ;CDDR #$ff,PTDDD ;DDDR #$ff,PTEDD ;EDDR
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AN2493/D Typical IDDs Specific Low-Power Modes
10ED 10F0 10F3 10F6 10F9 10FC 10FF 1102 1105
MainLoop
#$ff,PTFDD ;FDDR #$ff,PTGDD ;GDDR #$00,PTAD #$00,PTBD #$00,PTCD #$00,PTDD #$00,PTED #$01,PTFD #$00,PTGD SPMSC2 #mPPDF MainLoop ;ADR ;BDR ;CDR ;DDR ;EDR ;FDR ;GDR ;how here? ;was wake-up from STOP2?
1108 180A 110B 110D 110F 1112 1115 1117 111A 111C 111E 1120 180A 180A
PTFD_STORE,PTFD ;Replace with stored info SPMSC2 ;acknowledge Stop2 recoverey #(mPPDACK|mPDC|mPPDC) SPMSC2 PTFD #mPTFD0 PTFD ;Toggle here Stop2
;Wait while (Debounce)
1122 1124 1126 1127
stop
PTFD PTFD_STORE ;Store state into MainLoop
1129 112B 112D 112F 1131 1132 1135 1137 113A 113C 113E 1140
1808 1808
;***********Interrupt Service kbi_isr bset KBACK,KBISC ;Acknowledge Interrupt PTFD ;Toggle Here #mPTFD0 PTFD rti_isr SRTISC #mRTIACK SRTISC ;Acknowledge Interrupt PTFD ;Toggle Here #mPTFD0 PTFD Vrti rti_isr Vkeyboard kbi_isr Vreset START
FFCC 1132 FFD2 1129 FFFE 1080
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Conclusion
MC9S08GB/GT configured variety ways achieve power-consumption. three different stop modes offer variety solutions user's application. data shows that stop modes, operational current kept very low. flexibility different stop modes combined with other features such RTI, operating voltage range clock configuration options make MC9S08GB/GT ideal low-power applications.
Below summary features each low-power modes: Stop1 complete power-down mode with register content lost Exit stop1 with reset; exit requires external event Stop2 partial power-down mode with contents maintained with states latched Exit with IRQ, reset, internal auto wakeup timer Requires initialization peripheral used Stop3 equivalent M68HC08 MCU's stop mode with Exit with IRQ, KBI, LVD, internal auto wakeup timer, reset Allows clock generators enabled driven peripherals external clock references used Does require initialization peripherals Wait mode disables clock clock peripherals with (FBE) Typically used when waiting interrupt such receive interrupt Immediate processing interrupt service routine mode with (FBE)
files accompany this application note, AN2493SW1.zip AN2493SW2.zip. AN2493SW1.zip contains just assembly include file low-power modes software. AN2493SW2.zip contains complete CodeWarrior project folder. Inside first level project folder CodeWarrior project file with ".mcp" filename extension. Double-clicking this file will open project CodeWarrior been installed. project been assembled listing (".lst" file extension) available "bin" subfolder. Also, record (".s19" file extension) available same folder.
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AN2493/D Conclusion
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REACH
USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 1-800-521-6274 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 HOME PAGE:
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters that provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals", must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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AN2493/D Rev. 9/2003
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Donnie Garcia Scott Pape 8/16 Applications Systems Engineering Austin,

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