AN2189 Using Clock Generation Module HC12 Family Martyn Gall
|
|
|
Top Searches for this datasheet
Order this document AN2189/D
AN2189
Using Clock Generation Module HC12 Family
Martyn Gallop Stuart Robb East Kilbride, Scotland
Freescale Semiconductor, Inc.
Introduction
M68HC912D Family microcontrollers incorporate clock generation circuitry comprising power oscillator phaselocked loop (PLL). enhanced operational capability under adverse conditions there also clock monitor circuit, computer operating properly (COP) watchdog addition, features emergency operating mode called Limp-home mode (LHM). purpose this document present most commonly used configurations clock control registers outline behaviour clock generation circuit power modes under adverse conditions. This document should used conjunction with relevant microcontroller Technical Manual.
Oscillator
internal Colpitts oscillator requires external components order generate clock signal. Commonly, quartz crystal ceramic resonator used, together with pair load capacitors. quartz crystal will realise precise stable clock frequency this reason they preferred component when clock will used base high frequency communications such controller area network (CAN). other hand, ceramic resonators lower
Motorola, Inc., 2001
More Information This Product, www.freescale.com
Application Note
cost, side effect lower that start-up time oscillator significantly shorter than quartz crystals. Ceramic resonators also available with integrated load capacitors which give this component size advantage over quartz crystals. Resonators with tight accuracy stability increasingly becoming available. cases highly recommended that correct value load capacitors obtained directly from crystal/resonator manufacturer. Note that arrangement external components different from standard Pierce circuit used other HC12 microcontrollers. Note also that VSSPLL ground connection oscillator well that this must always connected ground. common node crystal/resonator capacitor should connected directly VSSPLL pin. order minimise power consumption, oscillator contains amplitude limitation control loop. This limits peak-to-peak amplitude EXTAL pin. oscillator continues Wait mode. Stop mode, oscillator completely stopped PSTP PLLCR register clear. PSTP PLLCR register set, microcontroller enters Pseudostop mode when `stop' instruction executed. Pseudo-stop mode internal clocks stopped oscillator continues run. Exit from Stop mode subject delay whilst oscillator restarted, this delay minimised Pseudo-stop mode used. Although current consumption Pseudo-stop mode higher that Stop mode, mechanical stress ageing crystal/resonator reduced Pseudo-stop mode.
Freescale Semiconductor, Inc.
EXTAL XTAL VSSPLL QUARTZ CRYSTAL CERAMIC RESONATOR
D60A/DG128A
Figure Oscillator Circuit
AN2189 Oscillator More Information This Product, www.freescale.com Motorola
Application Note
optimum performance, physical layout oscillator circuit should occupy small area. Signal traces should kept short possible. other traces should cross below between oscillator components. crystal resonator load capacitors should same side board microcontroller minimise vias. High stability load capacitors recommended such multilayer ceramic with temperature coefficient.
Phase-Locked Loop
internal used generate higher clock frequency than crystal oscillator microcontroller system clock. allowed generate PCLK frequency which lower than crystal oscillator frequency operation some internal synchronizers would jeopardized. VDDPLL must connected operation. With VDDPLL connected VDD, enabled reset, selected source SYSCLK disabled/enabled under software control. always disabled when VDDPLL connected VSS. VDDPLL must left floating. VSSPLL must always connected ground this ground connection oscillator well PLL. used (VDDPLL connected VDD) then external components second order low-pass filter configuration must connected pin. used (VDDPLL connected VSS) then left floating connected (but VDD). Advantages using include: Increased flexibility power consumption strategies switched under software control give lower clock frequency lower power consumption. Reduced susceptibility electromagnetic interference Acts filter electromagnetic interference oscillator. Reduced electromagnetic emissions Short term frequency drift reduces emissions peak. Emergency Limp-home mode Microcontroller continue operate even crystal/resonator fails.
Freescale Semiconductor, Inc.
AN2189 Motorola Phase-Locked Loop More Information This Product, www.freescale.com
Application Note
operating modes: Acquisition Mode this mode higher value charge pump current (approximately allows large corrections voltage controlled oscillator (VCO) frequency. This mode used start-up when frequency target frequency. Tracking Mode this mode charge pump current reduced approximately only small corrections made frequency. normal configuration `automatic bandwidth selection' which obtained having AUTO PLLCR register. this configuration automatically switched from acquisition mode tracking mode frequency approaches target frequency. current leakage excessive, adverse environmental conditions example, then repetitively switch between acquisition tracking modes. these circumstances advisable manual acquisition configuration clearing both AUTO bits PLLCR register. Doing this will maintain higher charge pump current level constantly which will overcome higher levels leakage pin. LOCK PLLFLG register when frequency within tolerance target frequency indication that PLLCLK safe microcontroller system clock, SYSCLK. output frequency multiplied create PLLCLK frequency, ECLK frequency (fBus) equal frequency when PLLCLK selected SYSCLK (BCSP set). unaffected Wait mode, although power consumption reduced switching under software control before entering Wait mode. operation suspended Stop Pseudostop modes.
Freescale Semiconductor, Inc.
AN2189 Phase-Locked Loop More Information This Product, www.freescale.com Motorola
Application Note
VDDPLL D60A/DG128A
Figure Filter Circuit
Freescale Semiconductor, Inc.
Table Suggested Filter Components Tracking/Auto Mode
fREF [MHz] (Note fBus [MHz] SYNR [nF] 0.47 0.47 0.22 0.47 0.22 [nF] 0.22 0.047 0.47 0.047 0.022 0.22 0.047 0.022 0.01 Loop Bandwidth [kHz] 10.0 15.1 21.4 20.1 30.1 42.7 20.1 40.2 60.3 93.8
Note fREF fOSC (REFDV
AN2189 Motorola Phase-Locked Loop More Information This Product, www.freescale.com
Application Note
Table Suggested Filter Components Acquisition/Manual Mode
fREF [MHz] (Note fBus [MHz] SYNR [nF] [nF] 0.47 0.47 0.22 0.47 0.22 Loop Bandwidth [kHz] 10.1 15.2 21.6 10.1 22.1 30.4 46.9 20.2 44.1 66.2 93.8
Freescale Semiconductor, Inc.
Note fREF fOSC (REFDV
fPLLCLK
fXTAL [SYNR [REFDV
Equation PLLCLK Frequency when Locked
Clock Monitor
clock monitor circuit based internal resistor-capacitor (RC) time delay. oscillator (EXTALi) clock edges detected within this delay time, clock monitor generate microcontroller reset. Alternatively, VDDPLL connected VDD, clock monitor cause enter emergency Limp-home mode. VDDPLL connected VDD, clock monitor enabled reset, disabled/enabled under software control means FCME bits COPCTL register. VDDPLL connected VSS,
AN2189 Clock Monitor More Information This Product, www.freescale.com Motorola
Application Note
clock monitor disabled reset enabled/disabled under software control means FCME bits COPCTL register. Note that FCME write once after reset `normal' modes). There short delay from point when oscillator clock fails detection clock monitor circuit. microcontroller clocked directly from oscillator clock, there risk spurious clock signals disrupting normal operation microcontroller during this time. This risk eliminated microcontroller system clock derived from PLL. Once oscillator clock failed, application software should take action ensure that microcontroller remains safe state, especially case intermittent failure. clock monitor must disabled order microcontroller enter Stop Pseudo-stop mode because EXTALi clock stopped these modes.
Freescale Semiconductor, Inc.
Limp-home Mode
emergency Limp-home mode allows microcontroller continue operation frequency fVCOMIN event crystal/resonator oscillator failure long oscillator startup time. This mode available only VDDPLL connected VDD. Limp-home mode, PLLCLK frequency drops minimum frequency VCO. PLLCLK drives ECLK, PCLK, MCLK, XCLK BCLK frequency fVCOMIN. Limp-home mode disabled under software control means NOLHM PLLCR register. This write once after reset `normal' modes). LHOME PLLFLG register when microcontroller Limp-home mode cleared when Limp-home mode. LHIE PLLCR register enables limp-home interrupt when set. Exit from Limp-home mode occurs when clock monitor circuit detected EXTALi clock edges. However, although clock monitor circuit detect clock edges, does detect oscillator clock signal valid duty cycle frequency. recommended shut down microcontroller executing `stop' instruction when Limp-home mode entered.
AN2189 Motorola Limp-home Mode More Information This Product, www.freescale.com
Application Note
BCSP BCSS PHASE LOCK LOOP PLLCLK SYSCLK
CLOCK GENERATOR
TCLKs
CLKSRC EXTAL EXTALi BCSP BCSS REDUCED CONSUMPTION OSCILLATOR XTAL EXTALi SCI0, SCI1, EXTALi BCSP BCSS MSCAN CLOCK GENERATOR ECLK PCLK BUSES, SPI, PWM, ATD0, ATD1
Freescale Semiconductor, Inc.
MCLK SLOW MODE CLOCK DIVIDER SLWCLK
SYNC XCLK RTI, BCLK SYNC
CLOCK MONITOR
Figure Clock Generation Chain
Effects Oscillator Failure
effect oscillator failure categorised according conditions under which event occurs. three situations are: power-on reset During normal operation exit from Stop Pseudo-stop mode
AN2189 Effects Oscillator Failure More Information This Product, www.freescale.com Motorola
Application Note
response oscillator clock failure depends state VDDPLL clock configuration bits. response oscillator failure three situations described different clock configurations sections below.
Clock Behaviour with Disabled
VDDPLL level floating level Connecting VDDPLL disables Limp-home mode. clock monitor disabled reset. ECLK half oscillator clock frequency. possible enable select PLLCLK when VDDPLL level.
Freescale Semiconductor, Inc.
Power-on Reset
microcontroller begins operation when oscillator starts. Code execution begins after count 4096 XCLK cycles (8192 EXTALi cycles). order prevent code execution beginning before oscillator stabilised, RESET should held (VSS level) sufficient time allow oscillator stabilise. oscillator fails before during Power-on reset, microcontroller stops operating.
Normal Operation
Oscillator failure during normal operation could result improper operation microcontroller unstable oscillator clock signal oscillator fails. reduce this risk, clock monitor watchdog should enabled software. clock monitor enabled setting either FCME COPCTL register (note FCME write once after reset). Once enabled, clock monitor will cause reset oscillator clock should fail. watchdog enabled writing value other than CR2.CR0 bits COPCTL register. Once enabled, software must prevent reset periodically writing followed COPRST register. Note that microcontroller distinguishes between internal reset (COP clock monitor) external reset sampling level reset about ECLK cycles after driven low. level
AN2189 Motorola Clock Behaviour with Disabled More Information This Product, www.freescale.com
Application Note
reset still when sampled, external reset assumed. Thus, external circuitry reset prevents reset from rising within this time, reset vector clock monitor reset vector will never taken.
Stop Mode
order enter Stop mode, clock monitor must disabled: FCME bits COPCTL register must both clear disable clock monitor. Also, condition codes register must cleared enable `stop' instruction. When `stop' instruction executed clocks microcontroller stopped. PSTP PLLCR register then Pseudo-stop mode entered oscillator continues run. Stop mode Pseudo-stop mode exited means interrupt external reset. Only specific interrupts cause exit from Stop Pseudo-stop modes, these IRQ, XIRQ, wakeup, MSCAN wakeup. INTCR register must always before entering Stop mode when using internal oscillator. This ensures that delay 4096 XCLK cycles occurs before code allowed execute, this give sufficient time oscillator stabilise after restarting. microcontroller will resume operation more quickly PSTP before entering Pseudo-stop mode oscillator does have restarted, still recommended INTCR register. oscillator fails during Stop Pseudo-stop modes microcontroller will restart operation. oscillator partially fails, does stabilise during 4096 XCLK delay time, there risk improper operation microcontroller.
Freescale Semiconductor, Inc.
Clock Behaviour with Enabled
VDDPLL level. connected order low-pass filter. Connecting VDDPLL enables PLL, clock monitor Limp-home mode reset.
AN2189 Clock Behaviour with Enabled More Information This Product, www.freescale.com Motorola
Application Note
Power-on Reset
With VDDPLL level, PLL, clock monitor Limp-home mode enabled. microcontroller (when configured `normal', opposed `special', modes) starts Limp-home mode 4096 XCLK cycle count started limp-home clock frequency, fVCOMIN. EXTALi clock edges detected clock monitor circuit during 4096 XCLK cycle count Limp-home mode exited immediately 4096 XCLK cycle count continues using EXTALi clock instead PLLCLK. 4096 XCLK cycle count reset released code execution begins with EXTALi selected SYSCLK. Note however, that although clock monitor circuit detect clock edges, does detect oscillator clock signal valid duty cycle frequency. Therefore possible that with slow starting oscillator microcontroller begin executing code from oscillator clock which stabilised improper operation result. avoid this issue, necessary hold reset with external circuit extended period time allow oscillator clock stabilise errata AR627 latest Mask Errata appropriate microcontroller more details. oscillator failed start clock monitor detected edges 4096 XCLK cycle count, microcontroller remains Limp-home mode code execution begins fVCOMIN with LHOME set. clock monitor output checked after another 4096 XCLK cycles then again every 8192 XCLK cycles thereafter. oscillator clock edges detected, Limp-home mode will exited check point, clearing LHOME generating interrupt enabled LHIE bit. recommended check status LHOME PLLCR register immediately start code execution determine oscillator started. microcontroller operating Limp-home mode must decided whether safe allow microcontroller continue operating, shut down. recommended shut down microcontroller enabling stop instruction (clear condition codes register) executing `stop' instruction. Refer Stop Mode different Stop mode senarios.
Freescale Semiconductor, Inc.
AN2189 Motorola
Clock Behaviour with Enabled More Information This Product, www.freescale.com
Application Note
There risk associated with allowing operation continue Limphome mode possibility partial oscillator recovery leading improper operation.
Normal Operation
response microcontroller oscillator failure during normal operation depends state NOLHM, FCME bits. 8.2.1 Clock Monitor Disabled FCME This mode recommended normal operating mode included only completeness. oscillator fails, longer reference clock PLLCLK frequency will drop minimum frequency. LOCK PLLFLG register will cleared interrupt generated enabled LHIE bit. SYSCLK derived from PLLCLK (BCSP microcontroller will continue operate frequency fVCOMIN. however, SYSCLK derived from EXTALi (BCSP microcontroller will stop operating. both cases peripheral modules which require clock derived from EXTALi will operate. oscillator clock recovers, PLLCLK will gradually recover target frequency. NOLHM FCME oscillator fails, clock monitor will generate clock monitor reset microcontroller will forced reset state. There short delay from point which oscillator fails detection clock monitor. Peripheral modules which require clock derived from EXTALi affected during this time. status NOLHM signal latched throughout clock monitor reset microcontroller does start Limp-home mode. Reset clears BCSP bit, i.e. EXTALi selected SYSCLK microcontroller will only restart when oscillator clock recovers. external reset will enable microcontroller restart Limp-home mode. There risk improper operation unstable oscillator clock oscillator clock recovers.
Freescale Semiconductor, Inc.
8.2.2 Limp-home Mode Disabled, Clock Monitor Enabled
AN2189 Clock Behaviour with Enabled More Information This Product, www.freescale.com Motorola
Application Note
8.2.3 Limp-home Mode Enabled, Clock Monitor Enabled
NOLHM FCME Limp-home mode entered oscillator fails microcontroller continues operation fVCOMIN regardless state PLLON PLLCR register, BCSP bits CLKSEL register, value SLOW register. LHOME PLLFLG register indicate operation Limp-home mode. clock monitor output checked every 8192 XCLK cycles thereafter oscillator clock edges detected, Limp-home mode will exited. must decided whether safe allow microcontroller continue operating, shut down. recommended shut down microcontroller disabling interrupts, enabling stop instruction (clear condition codes register) executing `stop' instruction. Refer Stop Mode different Stop mode senarios. There risk associated with allowing operation continue Limphome mode possibility partial oscillator recovery leading improper operation.
Freescale Semiconductor, Inc.
Stop Mode
response microcontroller `stop' instruction with VDDPLL level depends state PSTP, NOLHM, FCME bits. INTCR register must always before entering Stop mode when using internal oscillator. This ensures that delay 4096 XCLK cycles occurs before code allowed execute, this give time oscillator stabilise after restarting. recommended INTCR register before entering Pseudo-stop mode. following descriptions Stop/Pseudo-stop mode recover assume that set. Stop mode Pseudo-stop mode exited means interrupt external reset. Only specific interrupts cause exit from Stop Pseudo-stop modes, these IRQ, XIRQ, wakeup, MSCAN wakeup.
AN2189 Motorola Clock Behaviour with Enabled More Information This Product, www.freescale.com
Application Note
8.3.1 Limp-home Mode Disabled, Clock Monitor Disabled NOLHM FCME Execution `stop' instruction causes clocks microcontroller stop. PSTP before `stop' instruction executed, oscillator will remain running Pseudo-stop mode. exit from Stop Pseudo-stop) mode microcontroller begins operation with BCSP determining clock source 4096 XCLK cycle count delay. Code execution begins this delay time. BCSP clear, operation begins with EXTALi clock selected. oscillator fails start microcontroller will exit Stop mode will start operating. oscillator partially fails, does stabilise during 4096 XCLK delay time, there risk improper operation microcontroller. BCSP set, operation begins with PLLCLK selected. this case SLOW register configured before entering Stop mode extend 4096 XCLK cycle count that already locked time code execution begins. oscillator fails start microcontroller will exit Stop mode start operation fVCOMIN (but Limp-home mode). Peripheral modules which require clock derived from EXTALi will operate. 8.3.2 Limp-home Mode Disabled, Clock Monitor Enabled NOLHM FCME Execution `stop' instruction causes clock monitor detect oscillator clock "failure" which immediately results system reset. Stop mode entered. status NOLHM signal latched throughout clock monitor reset microcontroller continues operation from clock monitor reset vector using EXTALi clock SYSCLK. Note that microcontroller distinguishes between internal reset (COP clock monitor) external reset sampling level reset about E-clock cycles after driven low. level reset still when sampled, external reset assumed. Thus external circuitry reset prevents reset from rising within this time, reset vector will taken instead clock monitor reset vector.
Freescale Semiconductor, Inc.
AN2189 Clock Behaviour with Enabled More Information This Product, www.freescale.com Motorola
Application Note
8.3.3 Limp-home Mode Enabled
NOLHM Limp-home mode enabled when `stop' instruction executed, FCME bits disregarded clock monitor disabled. clocks microcontroller stop oscillator remains running only PSTP set. exit from Stop mode clock monitor forced enabled microcontroller begins operation Limp-home mode fVCOMIN 4096 XCLK cycle count clock monitor status checked before code execution begins. clock monitor detected oscillator clock edges 4096 XCLK cycle count, then Limp-home mode exited immediately code execution begins with value BCSP determining source SYSCLK. clock edges have been detected, microcontroller remains Limp-home mode code execution begins fVCOMIN with LHOME set. clock monitor output checked after another 4096 XCLK cycles again every 8192 XCLK cycles thereafter. oscillator clock edges detected, Limp-home mode will exited, clearing LHOME generating interrupt enabled LHIE bit. microcontroller begins code execution Limp-home mode must decided whether safe allow microcontroller continue operating, shut down. recommended shut down microcontroller disabling interrupts executing `stop' instruction. There risk associated with allowing operation continue Limphome mode possibility partial oscillator recovery leading improper operation.
Freescale Semiconductor, Inc.
Summary Recommended Configuration with Enabled
8.4.1 Power-on Reset 8.4.2 Normal Operation reset must held with external circuit until oscillator clock stabilised. Clock monitor enabled (CME FCME set). Reset required clock failure: Limp-home mode disabled (NOLHM set).
AN2189 Motorola Clock Behaviour with Enabled More Information This Product, www.freescale.com
Application Note
Software shutdown required clock failure: Limp-home mode enabled (NOLHM clear). 8.4.3 Stop Mode Conditions before entering Stop mode: set. EXTALi clock selected (BCSP clear). PSTP faster Stop mode recovery expense increased current consumption.
Freescale Semiconductor, Inc.
operation required clock fails start: Limp-home mode disabled (NOLHM set), clock monitor disabled (CME FCME bits clear), EXTALi clock selected (BCSP clear). Software shutdown required clock fails start: Limp-home mode enabled (NOLHM clear), PLLCLK selected (BCSP set).
Summary Terms
byte value equal Clear byte value equal
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
Motorola, Inc., 2001
More Information This Product, www.freescale.com
AN2189/D
Other recent searches
SZAF0B - SZAF0B SZAF0B Datasheet
QFN33-16 - QFN33-16 QFN33-16 Datasheet
PALC22V10D - PALC22V10D PALC22V10D Datasheet
LT1195 - LT1195 LT1195 Datasheet
IRFV260 - IRFV260 IRFV260 Datasheet
HE9204-A - HE9204-A HE9204-A Datasheet
AVR32709 - AVR32709 AVR32709 Datasheet
2SC5103 - 2SC5103 2SC5103 Datasheet
2SC5525 - 2SC5525 2SC5525 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
