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AN2188
Freescale Semiconductor, Inc.
Compatibility considerations between 0.65µ M68HC12D60 0.5µ Flash M68HC912D60A
Introduction
Designs using 0.65µ M68HC12D60 mask device require support from Flash device either emulation tool during development and/or provide flexibility production where Flash device used bridge unexpected short term increases production demand. 0.65µ Flash M68HC912D60 currently being superseded 0.5µ Flash M68HC912D60A. purpose this document help designers maintain compatibility when using 0.5µ Flash M68HC912D60A (referred 'Flash device') emulation tool socket replacement 0.65µ mask M68HC912D60 (referred 'ROM device'). This document intended conjunction with most current data sheets mask errata each device. time writing these documents were available download from Motorola site* they requested from your Motorola distributor Motorola Sales Office. Please check these documents information.
Motorola, Inc., 2001
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Application Note
Table Documentation Order Numbers
Document Number MC68HC912D60/D MC68HC912D60A/D Device MC68HC12D60 (document also covers MC68HC912D60) MC68HC912D60A
Freescale Semiconductor, Inc.
Table MC68HC12D60 Device Ordering Information
Temperature Package Range +70°C 112-Pin TQFP Single Tray +85°C +105°C +125°C +70°C 80-Pin Single Tray +85°C +105°C +125°C 4.5V-5.5V XC68HC12D60VFU8 XC68HC12D60MFU8 4.5V-5.5V XC68HC12D60VPV8 XC68HC12D60MPV8 XC68HC12D60FU8 XC68HC12D60CFU8 Designator XC68HC12D60PV8 XC68HC12D60CPV8 Voltage Frequency Order Number
Table MC68HC912D60A Device Ordering Information
Temperature Package Range 112-Pin TQFP Single Tray +85°C +105°C +125°C +85°C +105°C +125°C Designator 4.5V-5.5V 4.5V-5.5V MC912D60ACPV8 MC912D60AVPV8 MC912D60AMPV8 MC912D60ACFU8 MC912D60AVFU8 MC912D60AMFU8 Voltage Frequency Order Number
80-Pin TQFP Single Tray
AN2188 Introduction More Information This Product, www.freescale.com Motorola
Application Note
Summary Most aspects devices fully compatible. Where there functional differences simple recommendations described which should provide compatibility. majority differences relate Non-Volatile Memory (NVM) implementation. also modified Flash device improved flexibility when selecting conversion source results location format. Most additional features default being compatible with ROM. registers device supported Flash device other peripheral modules unchanged. There mask option registers device parameters configured application software. device, control `BDM lockout' located shadow EEPROM byte. Flash device, control `BDM lockout' default EEPROM pre-scaler value (Section 3.2) located shadow EEPROM word.
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Code Storage
device, code stored static, factory masked, Read Only Memory (ROM). Flash device, code stored non-volatile, electrically erasable programmable memory constructed from split-gate flash technology (Flash EEPROM). Reading from Flash memories identical. equivalent array sizes equivalent (32K 28K) MAPROM, ROMON28 ROMON32 bits MISC control register, swapping disabling memory arrays, function identically.
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Application Note Flash Architecture
Flash memory only' separate external programming voltage (VFP) required. Programming carried whole bytes) time whilst erase carried bulk erase each entire array (32K 28K). reduce possibility accidental modification Flash contents, code programming erasing Flash should included application device can't reprogrammed this should issue). Programming should carried downloading boot loader program (typically connection) into which then executed modify flash this most party programmers work.
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Flash Control Registers
4-byte register block each module controls Flash EEPROM operation. reset, 4-byte register section starts address $00F4/$00F8 modules respectively. device these registers ($00F4 $00FF) reserved therefore should accessed. Flash device, best practice, application choose access these registers although this essential compatibility with ROM: Initializing FEExxLCK (Flash EEPROM Lock Control) Register.
$00F4/$00F8 LOCK
FEE32LCK/FEE28LCK Flash EEPROM Lock Control Register
Each Flash EEPROM module hardware interlocks which protect stored data from accidental corruption. erase- programprotected 8-Kbyte `boot block' protected routines located $6000-$7FFF $E000-$FFFF following reset. Note that upper rows (128 bytes) these memory arrays contains Reset interrupt vectors. System critical fault recovery routines, including
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Application Note
reset unused interrupt service routines, stored these locations protected from accidental corruption. Protection `boot block' controlled BOOTP FEExxMCR (Flash EEPROM Module Configuration) register. reset default `protected'. avoid this state being accidentally modified, setting LOCK `write once' FEExxLCK register prevents accidental writes FEExxMCR register from unprotecting `boot block'. Summary: lock `boot block' protection mechanism bit0 (LOCK) FEExxLCK register each Flash module during initialization. (Optional) Initialising FEExxLCK (Flash EEPROM Control) Register.
FEE32LCK/FEE28LCK Flash EEPROM Lock Control Register FEESWAI HVEN $00F4/$00F8 ERAS
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clocks Flash modules optionally disabled entering WAIT mode reduce power consumption (all clock drivers disabled module becomes fully static). order this happen FEESWAI FEExxCTL register must set.
CAUTION:
this register controls write erase function flash extreme care must taken write incorrectly. Summary: reduce current consumption WAIT mode Bit4 (FEESWAI) FEExxMCR register each Flash module during initialization. (Optional)
Flash Programming Procedure
Programming Flash greatly simplified over previous Flash based HC12s. read verify re-pulse programming algorithm replaced much simpler method. This should only carried externally controlled process i.e. external from application.
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Application Note Flash Programming Voltage
Flash does require external high voltage supply. voltages required programming erase generated internally. early 0.5µ Flash devices (112 QFP) QFP) used factory test purposes. recommended that this connected within application, connected 5.5V without issue. later production devices this bonded out. device this bonded. Summary: compatibility leave (112 QFP) QFP) unconnected application.
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EEPROM data
EEPROM Architecture
Flash device, EEPROM also made from split-gate which physically constructed different from EEPROM array device. order achieve object code compatibility state machine implemented Flash device EEPROM module make difference transparent. architecture basic programming erase operations unchanged application programming level. However, there optional AUTO programming method that allows faster programming EEPROM compatibility reasons this should used. included here completeness because additional AUTO Flash device allows application identify between Flash device circuit'.
AN2188 EEPROM data More Information This Product, www.freescale.com Motorola
Application Note
Flash device EEPROM Clock Source Pre-scaler
difference Flash device that EEPROM module requires constant time base ensure correct programming erase operations. cater large range input clock frequencies found applications, this time base (around 28.6KHz) derived from external clock signal (EXTALi) divided pre-scaler. divide ratio this source must configured programming 10-bit time base pre-scalar value into registers, EEDIVH EEDIVL (referred single word register `EEDIV') produce 35µs timebase.
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EEDIVH EEPROM Modulus Divider EEDIV9
$00EE EEDIV8
EEDIVL EEPROM Modulus Divider EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1
$00EF EEDIV0
result EEPROM clock requirement resonator crystal frequency tolerance should better than total 2MHz, total 2MHz. This well within requirements most applications certainly those using communications bus. EEDIVH/L values determined following formula: EEDIVH/L INT[reference clock (Hz) 35x10-6 0.5] INT[x] denotes round down integer value
AN2188 Motorola EEPROM data More Information This Product, www.freescale.com
Application Note
example Reference Frequency 4.0MHz, EEDIV value from above formula will INT[140.5] hence module clock will 4.0x106 28.571KHz frequency equivalent period 35.00µs
EXTALi Freq Clock Period 125ns 250ns 500ns DivideFactor EEDIV value $0118 $008C $0046 $0023 $0012
Freescale Semiconductor, Inc.
appropriate value easily calculated pre-processor e.g.
#define XTAL_FREQ macro value calculating EEDIV value rounded down preprocessor only used unsigned integer #define EEDIVIDER_VALUE ((XTAL_FREQ 35.0) 0.5)
EEDIV register volatile. However, loaded upon reset contents non-volatile SHADOW word much same NOBDML EEPROM module control register (EEMCR) interacts with SHADOW word locking ROM. Summary: both) following methods setting EEDIV value MUST implemented before programming erasing EEPROM location incorrect value will damage EEPROM. program shadow word with appropriate divider value (proportional application's XTAL value) same time Flash programed. Care must taken ensure that other bits shadow word programmed correct values. over-write reset value EEDIV `write once only' register with appropriate divider value application initialization routine.
AN2188 EEPROM data More Information This Product, www.freescale.com Motorola
Application Note
Non-volatile default into pre-scaler registers Reset.
SHADOW ($0FC0)
RESET
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Pre-scaler registers modified software once normal modes. into counter overflow.
EEDIV ($00EE) Prescaler
OVER FLOW
COUNTER
35µs timebase
Figure Loading EEDIV value
EEPROM AUTO Detecting whether Flash device
Another difference Flash device EEPROM module inclusion EEPROG (EEPROM control) register additional AUTO (Bit-5).
EEPROG EEPROM Control BULKP AUTO BYTE ERASE EELAT $00F3 EEPGM
device this unused. AUTO functionality available ROM, AUTO should order ensure compatible program erase. However, AUTO tested application detect whether running Flash device.
AN2188 Motorola EEPROM data More Information This Product, www.freescale.com
Application Note
Flash device this (AUTO) cleared mode, hence attempts clear will successful Flash device where will read appropriate. ROM, Bit-5 EEPROG register unused will always read `0'. Summary: application software should ensure that bit-5 EEPROG register always cleared during normal EEPROM functions.
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3.3.1 Code example determining device type
This function returns TRUE Flash, FALSE
testFlashDevice(void) attempt Bit-5 $00F3 Eeprom.eeprog.bit.autobit if(Eeprom.eeprog.bit.autobit it's 0.5u Flash device clear AUTO again Eeprom.eeprog.bit.autobit return( TRUE else failed it's 0.65u Flash device return( FALSE
This useful determining whether write EEDIV value application e.g.
testFlashDevice() TRUE write EEDIVIDER $00EE Eeprom.eediv (unsigned int)EEDIVIDER_VALUE 0x03FF; else nothing
this case EEDIV register only written application running 912D60A (but ROM). This routine also extended initialize flash registers described Section 2.2.
AN2188 EEPROM data More Information This Product, www.freescale.com Motorola
Application Note
When Entering Limp Home Mode
Flash device, Limp Home entered during program erase cycle, i.e. with EEPGM state machine will complete cycle with EEDIV forced nominal value $0023 (reflecting fVCOMIN typical 1MHz). Program erase EEPROM guaranteed Limp home mode. This valid restriction both Flash devices Limp Home Frequency (fVCOMIN) tightly specified. Flash device very important program erase EEPROM with undefined clock (outside specification described Section 3.2) order avoid damaging EEPROM. Summary: recommended abort EEPROM modify operations immediately entry Limp Home Mode clearing EEPGM then EELAT EEPROM Control Register.
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Clock Monitor
Clock Monitor (CME bit) should enabled during program/erase order avoid damaging EEPROM. clock failure, case Clock Monitor reset sequence EEPROM modify progress will aborted EEPGM EELAT bits EEPROM Control Register cleared reset) thus protecting cell(s). This valid strategy both Flash devices. Summary: Clock Monitor detect when clock goes spec order terminate EEPROM functions either reset process entry into Limp Home mode.
AN2188 Motorola EEPROM data More Information This Product, www.freescale.com
Application Note EERC
Flash device, EEPROM module oscillator implemented EERC replaced with dummy (DMY) with functionality.
EEMCR EEPROM Module Configuration Device NOBDML NOSHW EESWAI PROTLCK $00F0 EERC $00F0 PROTLCK
EEMCR EEPROM Module Configuration Flash Device NOBDML NOSHW EESWAI
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device, frequencies fPROG (i.e. <1MHz current spec 2MHz EXTALi without PLL) EERC enable oscillator EEPROM module program erase. Flash device there EEPROM cell state machine program erase lower frequencies. However, order meet EEPROM time base specification, program/erase should performed with input clock frequency EXTALi <250 KHz. Setting replacement Flash device effect there software compatibility issues. Summary: compatibility issue.
Flash device EEPROM Module Selective Write More Zeros
split-gate construction allows additional technique referred `Selective Write More Zeros', described M68HC912D60A data book. this functionality specified this technique should used. Summary: programming erase cycles should considered independent successive writes EEPROM location should ALWAYS preceded erase cycle.
AN2188 EEPROM data More Information This Product, www.freescale.com Motorola
Application Note
STOP mode
Flash device will exit STOP mode without having synchronize start STOP with clock. device this errata. Summary: Implement work around errata. This will cause problems 912D60A.
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WAIT mode
Flash device will correctly exit WAIT mode using short XIRQ inputs. device this errata. Summary: Implement work around errata. This will cause problems 912D60A.
Filter
Flash device filter will ignore pulses shorter than microseconds. device this errata. Summary: Implement work around errata. This will cause problems 912D60A.
AN2188 Motorola STOP mode More Information This Product, www.freescale.com
Application Note
CAUTION:
both Flash, power must applied VDDA times even being used. This necessary port port function correctly digital inputs line with specification both devices.
Operation bits ATDxCTL5 Control Register
There difference operation module between device Flash device when performing multichannel conversions (MULT Flash Device cleared below), i.e. with conversions making conversion sequence.
ATD0CTL5/ATD1CTL5 Control Register S8CM SCAN MULT $0065/$01E5
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ATD0CTL5/ATD1CTL5 Control Register S8CM SCAN MULT
$0065/$01E5
ROM, value bits masked depending value S8CM bits. value bits doesn't affect where conversion results stored. selects internal channels conversion. Table Table Multichannel Mode Result Register Assignment
S8CM Channel Signal Result ADRxx MULT ADRx0 ADRx1 ADRx2 ADRx3
AN2188 More Information This Product, www.freescale.com Motorola
Application Note
Table Multichannel Mode Result Register Assignment
Result ADRxx MULT ADRx0 ADRx1 ADRx2 ADRx3 Reserved ADRx0 Reserved ADRx1 Reserved ADRx2 Reserved ADRx3 ADRx0 ADRx1 (VRH VRL)/2 ADRx2 TEST/Reserved ADRx3 ADRx0 ADRx1 ADRx2 ADRx3 ADRx4 ADRx5 ADRx6 ADRx7 Reserved ADRx0 Reserved ADRx1 Reserved ADRx2 Reserved ADRx3 ADRx4 ADRx5 (VRH VRL)/2 ADRx6 TEST/Reserved ADRx7 Shaded bits "don't care" MULT entire block four eight channels make conversion sequence. When MULT four bits (CD, must specified conversion sequence consists four eight consecutive conversions single specified channel. S8CM Channel Signal
Freescale Semiconductor, Inc.
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Application Note
Flash device value bits used provide greater flexibility allowing application select which eight input channels sampled first sequence. result this they also effectively modify where result conversions stored first conversion sequence stored lowest results register. been renamed (Special Conversion) differentiate functionality from bits. still selects internal channels conversion note that bits continue modify which internal channel converted first. Table Table MC68HC912D60A Multichannel Mode Result Register Assignment (MULT=1)
channel conversion, External channels (S8C ADR0 ADR1 ADR2 ADR3
must clear.
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channel conversion, Internal sources (S8C ADR0 ADR1 ADR2 ADR3
Shaded cells reserved (VRH VRL) must clear.
AN2188 More Information This Product, www.freescale.com Motorola
Application Note
Table MC68HC912D60A Multichannel Mode Result Register Assignment (MULT=1)
channel conversion, External channels (S8C ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 channel conversion, Internal Sources (S8C ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7
Shaded cells reserved (VRH VRL) NOTES: compatibility with 68HC912D60, bits must where masked 68HC912D60. This shown above bold text. When MULT four bits (SC, must specified conversion sequence consists four eight consecutive conversions single specified channel. When four bits (SC, must specified conversion sequence consists conversion single specified channel.
Freescale Semiconductor, Inc.
Summary: compatibility between Flash software should ensure that relevant bits ATDxCTL5 register cleared when performing conversions with MULT shown bold text Table
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Application Note Additional features Flash device
extra feature available Flash M68HC912D60A controlling justification conversion results enabled additional ATDxCTL2 register. This features should used ensure compatibility
ATD0CTL2/ATD1CTL2 Control Register ADPU AAFC ASWAI Reserved Reserved $0062/$01E2 ASCIE ASCIF
Freescale Semiconductor, Inc.
(Result Register Data Justification Mode) controls whether result registers left right justified. Result Left justified ROM)
Summary: default setting (bit ensures compatibility between device Flash device. other bits this register usually written only once initialization this expected problem. Ensure this additional cleared writes this register compatibility.
NOTE:
AWAI ATDxCTL2 device renamed ASWAI Flash device compatible with M68HC912DT128A functionality unchanged. initial documentation flash device, this register additionally defined DSGN, controlling sign extension results. This incorrect should always written zero.
NOTE:
Additional Conversion Sequence Controls Flash Device
Extra features available Flash M68HC912D60A controlling sequence location conversions enabled additional
AN2188 More Information This Product, www.freescale.com Motorola
Application Note
bits ATDxCTL3 register. These features should used ensure compatibility.
ATD0CTL3/ATD1CTL3 Control Register FIFO $0063/$01E3 FRZ1 FRZ0
Freescale Semiconductor, Inc.
(Conversion Sequence Length lsb) interacts with control ATDCTL5 register determine many conversions performed sequence. Sequence length defined ROM) then Sequence length conversion
FIFO (Result Register FIFO Mode) controls whether result registers conversion sequence i.e. whether result register counter reset beginning ending conversion sequence.
NOTE:
correct definition result registers conversion sequence ROM) result registers conversion sequence some early device documentation these definitions were incorrectly swapped. Summary: both features default setting (bit ensures compatibility between device Flash device. other bits this register usually written only once initialization this expected problem. Ensure these additional bits cleared writes this register compatibility.
ATD0CTL4/ATD1CTL4 Control Register RES10 SMP1 SMP0 PRS1 PRS1 PRS1 $0064/$01E4 PRS1 PRS0
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Application Note
S10BM (Select Mode) ATDxCTL4 device renamed RES10 (Resolution bits) Flash device, compatible with M68HC912DT128A functionality unchanged.
ATD0CTL5/ATD1CTL5 Control Register SCAN MULT $0065/$01E5
Freescale Semiconductor, Inc.
Flash device channel selected first conversion multiple channel conversion. Bits ATDxCTL5 masked, they device, used select which channel used start sequential conversion sequence. compatibility ensure that appropriate bits cleared software. Section 7.1. ATDxCTL5 device renamed (Special Conversion) Flash device differentiate from extended functionality Bits Functionality unchanged still selects conversion from internal reference sources when doing multiple channel scan bits must cleared appropriate compatible reference selection. Section 7.1. S8CM (Select Channel Mode) ATDxCTL5 device renamed (Conversion Sequence Length) Flash device highlight extended functionality ATDxCTL3 (see Section 9.1). Functionality compatible with S8CM (its default value).
AN2188 More Information This Product, www.freescale.com Motorola
Application Note
Flash device, SCAN mode (SCAN ATDxCTL5) Sequence Complete Flag (SCF ATDSTATx) after completion each conversion sequence. device only first conversion sequence. ensure compatibility application should rely this flag being only once SCAN mode.
Starting Aborting Conversion Sequences Register writes
device writing ATDxCTL2 ADTxCTL3 aborts ongoing sequence leaving idle mode conversion sequence being processed). Flash device, writing these registers does abort ongoing conversion sequence. device writing ATDxCTL4 register aborts ongoing sequence leaving idle mode conversion sequence being processed). Flash device, writing this register aborts ongoing conversion sequence initiates conversion sequence. This unlikely compatibility issue applications mostly write these registers configure ATD, closely followed write ATDxCTL5 register initiate conversion sequence which aborts ongoing conversion sequence resets appropriate flags. Summary: ensure compatibility application should rely ongoing conversions being aborted writes registers other than ATDxCTL5. interrupts from completion sequence should masked and/or handled correctly allow fact that writing ATDxCTL4 have started conversion.
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AN2188 Motorola
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Application Note Other Changes
Reading ATDTESTx register normal modes returns value Successive Approximation Register (SAR). Previously always read zero. Summary: ensure compatibility this register should relied upon read zero. ATDTESTx register written normal modes order reset ATD). Previously read only. Summary: ensure compatibility this register should read written
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AN2188 More Information This Product, www.freescale.com Motorola
Application Note
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Application Note
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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reach USA/EUROPE: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPS, Technial Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-266668334 CUSTOMER FOCUS CENTER: 1-800-521-6274
Motorola, Inc., 2000
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AN2188/D
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