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AN2166
Freescale Semiconductor, Inc.
Programming Erasing FLASH EEPROM Memories MC68HC912DT128A/DG128A/D60A
Darci Ernst, Adeela Gill, Kazue Kikuchi Transportation Standard Products Group Austin, Texas
Introduction
Motorola released microcontrollers (MCU), MC68HC912DT128A (DT128A) MC68HC912DG128A (DG128A), products M68HC12 Family devices.
NOTE:
MC68HC912D60A referenced specifically this application note, memory technology algorithms apply this part well. DT128A DG128A offer many features, including: 16-bit central processor unit (CPU) Kbytes FLASH memory FLASH boot code protection Kbytes EEPROM Kbytes on-chip
This application note explains FLASH EEPROM MC68HC912DT128A/DG128A provides example software program erase operations. These algorithms written M68HC12 assembly code.
Motorola, Inc., 2001
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Freescale Semiconductor, Inc. Application Note
This code available download from which Motorola's Semiconductor Product Sector's site. topics covered this application note include: Reference Documents MC68HC912DT128A/DG128A MC68HC912DG128 FLASH Functional Description FLASH Memory Mapping FLASH Control Registers FLASH Erase Operation FLASH Program Operation EEPROM Functional Description EEPROM Control Registers EEPROM Block Protection Timebase Initialization SHADOW Word EEPROM Erase Operation EEPROM Program Operation Selective Programming Evaluating Delay Times Sample Code FLASH Frequently Asked Questions EEPROM Frequently Asked Questions Sample Code
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Application Note Reference Documents
Reference Documents
complete information MC68HC912DT128A/DG128A devices, user should reference MC68HC912DT128A MC68HC912DG128A Technical Data, Motorola document number MC68HC912DT128A/D. information MC68HC912D60A, user should reference MC68HC912D60A Technical Data, Motorola document number MC68HC912D60A/D.
Freescale Semiconductor, Inc.
memory cells used MC68HC912DT128A/DG128A devices split gate cells from Silicon Storage Technology (SST) 0.5-micron geometry. site contains detailed description these cells. Refer http://www.ssti.com.
MC68HC912DT128A/DG128A MC68HC912DG128
general, MC68HC912DT128A/DG128A devices discussed this application note technology shrink from MC68HC912DG128 device. addition transistor size reduction, changes were made devices. These include: Using FLASH EEPROM technology FLASH programming algorithm. algorithm programs per-row basis faster simpler than before. Availability new, faster EEPROM programming algorithm. This algorithm automatically turns erasing/programming voltage when operation completed. Addition internal charge pump FLASH supply programming erasing voltage. There need provide high voltage supply pin.
WARNING:
apply volts Family devices. This damage device! safety, user connect this VDD.
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Freescale Semiconductor, Inc. Application Note
Adding required constant timebase source EEPROM. timebase external clock input, EXTAL, divided value programmed into EEDIVH EEDIVL registers.
devices compared detail Table Table Table FLASH Comparison
MC68HC912DG128 MC68HC912DT128A/ DG128A (SST) ERAS function. external high voltage needed; internal charge pump fixed pulse; erase programming times fixed word bytes) bulk Kbyte array)
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Type FLASH control register Programming voltage Algorithm Bit-erased state Programming minimum size Erasing minimum size Kbytes programming time Erase time
(1.5T) ERAS LATCH control External programming erasing voltage must provided Multiple pulses using margin read verification byte bulk Kbyte array)
Typical Minimum sizes: bytes, bytes, Kbytes, Kbytes
Minimum
Bulk erase: minimum
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Application Note MC68HC912DT128A/DG128A MC68HC912DG128
Table EEPROM Comparison
MC68HC912DG128 Minimum programming clock frequency Bit-erased state MC68HC912DT128A/ DG128A modes: Standard mode: utilize same routine MC68HC912DG128 AUTO mode: Program/erase cycle terminated internal timer byte block from $00EE EEDIVH $00EE EEDIVL $00EF other registers same byte, word bytes), bytes), bulk byte word bytes) Clock source oscillator clock (EXTAL) User specifies divide ratio word bytes) $0FC0-$0FC1 reset, SHADOW word loaded into EEMCR, EEDIVH, EEDIVL NOSHW, EEMCR Erase operation required before programming. same byte successively programmed only selective programming used. Standard mode: minimum AUTO mode: maximum Standard mode: minimum Auto mode: maximum
Algorithm
Fixed delays
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Registers Erase sizes supported Program sizes supported Charge pump clock SHADOW size location SHADOW mapping SHADOW disable
4-byte block from $00F0 byte, word bytes), bytes), bulk byte word bytes) EERC controls clock source. EERC system clock; EERC internal oscillator byte $0FC0 reset, SHADOW byte loaded into EEMCR NOSHB, EEMCR
Successive programming
Successive programming allowed
Programming time
Minimum
Erasing time
Minimum
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Freescale Semiconductor, Inc. Application Note FLASH Functional Description
MC68HC912DT128A/DG128A devices contain Kbytes FLASH memory. memory divided into four arrays Kbytes each. Each array consists windows, which software selectable page Kbytes) pages Kbytes) each. While memory subdivided into four arrays, there restrictions arrays used hold program/erase execution code. 32-Kbyte window configuration, such code cannot located FLASH. 16-Kbyte window configuration, code executed FLASH program/erase other arrays. But, this, code must direct-addressable FLASH, $4000-$7FFF $C000-$FFFF. This code cannot program erase addresses either those ranges. erased FLASH reads logic programmed reads logic algorithm programs row, words bytes), time. erase operation will erase entire active FLASH array Kbytes). FLASH Memory Mapping description FLASH window ranges. Program erase operations facilitated through control bits memory-mapped registers. Details these operations appear later this application note. FLASH memory module associated registers MC68HC912DT128A/DG128A are: 16-K window configuration: $4000-$7FFF $C000-$FFFF, direct accessible FLASH space $8000-$BFFF, page-addressable FLASH space
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NOTE:
ROMHM MISC register must cleared access addresses $4000-$7FFF. direct addressable space means that addresses read without using PPAGE register. However, program erase operations still require paging. 32-K window configuration: $8000-$FFFF, page-addressable FLASH space
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Application Note FLASH Memory Mapping
$0013, miscellaneous mapping control register, MISC $00F4, FLASH lock control register, FEELCK $00F5, FLASH module configuration register, FEEMCR $00F7, FLASH control register, FEECTL
Programming tools available from Motorola. Contact local Motorola representative more information.
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FLASH Memory Mapping
FLASH memory MC68HC912DT128A/DG128A configured different window sizes. mentioned earlier, four physical arrays FLASH memory device. special controls whether each array divided into 16-Kbyte 32-Kbyte windows. This function controlled special mapping register which critical FLASH operation. This known miscellaneous mapping control register, located $0013.
Read: ROMTST Write: Reset: NDRF RFSTR1 RFSTR EXSTR1 EXSTR0 ROMHM ROMON
Figure Miscellaneous Mapping Control Register (MISC) Only bits that relate FLASH operation will discussed here. Refer MC68HC912DT128A MC68HC912DG128A Technical Data information device modes other bits. ROMTST FLASH EEPROM Test Mode This determines memory window configuration FLASH. normal modes, this clear upon reset, changed with write MISC register. FLASH divided into 16-Kbyte windows from $8000-$BFFF. FLASH divided into 32-Kbyte windows from $8000-$FFFF.
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Freescale Semiconductor, Inc. Application Note
ROMHM FLASH EEPROM Half This meaning ROMON clear. function this changes depending value ROMTST bit. ROMTST when ROMHM Page accessed locations $4000-$7FFF Page accessed locations $4000-$7FFF. Page accessed addresses $8000-$BFFF using PPAGE register
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ROMTST when ROMHM There four distinct page-addressable FLASH memory arrays. four FLASH arrays overlap each other. write erase array will write erase four arrays. ROMON FLASH EEPROM Enable This used enable/disable FLASH arrays. FLASH arrays disabled. FLASH arrays enabled. Table summarizes effect these bits address ranges page values each memory window configuration.
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Application Note FLASH Memory Mapping
Table Memory Window Ranges
Array Page PPAGE FLASH Control Register Locations $00F4- $00F7(2) ROMTST MISC Windows Each Figure $8000-$BFFF $8000-$BFFF Boot block $A000-$BFFF $8000-$BFFF $00F4- $00F7(2) $8000-$BFFF Boot block $A000-$BFFF $8000-$BFFF $00F4- $00F7(2) $8000-$BFFF Boot block $A000-$BFFF $8000-$BFFF $4000-$7FFF(4) $00F4- $00F7(2) $8000-$BFFF Boot block $A000-$BFFF $C000-$FFFF Boot block $E000-$FFFF $8000-$FFFF Boot block $E000-$FFFF(3) $8000-$FFFF Boot block $E000-$FFFF(3) $8000-$FFFF Boot block $E000-$FFFF(3) $8000-$FFFF Boot block $E000-$FFFF(3) ROMTST MISC Windows Each(1) Figure
00FEE32K
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01FEE32K 10FEE32K
11FEE32K
Addresses $4000-$7FFF accessible this configuration. Also, both ROMTST ROMHM bits set, four memory arrays overlap. write/erase location will duplicated over four arrays. Each FLASH array registers. Therefore, access registers with either page value PPAGE register. ROMTST set, then array programmed/erased with PPAGE register either page. This memory window only exists ROMHM MISC register clear. cleared reset. this case, these addresses read directly programmed erased using PPAGE register.
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Freescale Semiconductor, Inc. Application Note
16-KBYTE CONFIGURATION: 16-KBYTE WINDOWS PPAGE REGISTER DETERMINES WHICH WINDOW ACTIVE
$4000 $7FFF
PAGE DUPLICATED $4000-$7FFF. OPTION ENABLED, THESE KBYTES READ, PROGRAMMED, ERASED EITHER "LOCATION."
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$8000 $BFFF
$C000 $FFFF
PAGE DUPLICATED $C000-$FFFF. THESE BYTES READ, PROGRAMMED, ERASED EITHER "LOCATION." BOOT BLOCKS THESE PAGES SHARE REGISTERS
Figure 16-Kbyte Configuration
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Application Note FLASH Block Protection
32-KBYTE CONFIGURATION: 32-KBYTE WINDOWS PPAGE REGISTER DETERMINES WHICH WINDOW ACTIVE
$4000 $7FFF
NON-FLASH SPACE
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$8000 $FFFF
BOOT BLOCKS THESE PAGES SHARE REGISTERS
Figure 32-Kbyte Configuration
FLASH Block Protection
Four memory ranges Kbytes each protected from being inadvertently programmed erased. protected blocks located page addressable addresses $A000-$BFFF $E000-$FFFF depending memory windows configured. Table summarizes protected boot blocks these devices. Block protection controlled FLASH module configuration register, FEEMCR, located $00F5. MC68HC912DT128A MC68HC912DG128A Technical Data, more information this register.
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Freescale Semiconductor, Inc. Application Note FLASH Control Registers
Each four FLASH arrays three registers that control operation: $00F4, FLASH lock control register (FEELCK) $00F5, FLASH module configuration register (FEEMCR) $00F7, FLASH control register (FEECTL)
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PPAGE register must used select correct register set. user should ensure that correct FLASH control registers configured each memory array. Table more information.
NOTE:
There essentially distinct FLASH control registers. These registers described detail MC68HC912DT128A MC68HC912DG128A Technical Data.
Word Alignment
programming erasing algorithms include write random address within array. This write allows memory pinpoint proper physical location actual erasing programming. While actual data written word, address written must aligned word. aligned word defined 2-byte space starting with address where final digit even number. That means words starting with address form $xxx0, $xxx2, $xxx4, $xxxE. misaligned word final digit. user specifies misaligned word write step erasing algorithm, memory erase function will successful. This restriction also holds true programming algorithm, both row-selection write (step also actual address being programmed.
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Application Note FLASH Erase Operation
FLASH Erase Operation
MC68HC912DT128A/DG128A, entire active FLASH array Kbytes erased once. protected locations will erased unless BOOTP FLASH module configuration register (FEEMCR) cleared first. Table boot block locations. Figure shows flowchart erase operation.
NOTE:
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user should make sure that proper window selected MISC PPAGE registers, other FLASH addresses accidentally erased. ERAS FLASH control register (FEECTL). ERAS configures FLASH memory erase operation. Write word word-aligned FLASH address within window. data written address written important. Wait time, tNVS. Internal high voltage charged. HVEN bit. Internal high voltage applied window. Wait time, tERAS. tERAS erase time. Clear ERAS bit. erase operation disabled. Wait time, tNVHL. This time required internal high voltage discharge from window. Clear HVEN bit. Disable internal high voltage. Wait time, tRCV. After time, tRCV, memory accessed normal read mode.
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Freescale Semiconductor, Inc. Application Note
ERASE STEP ERAS STEP WRITE WORD-ALIGNED ADDRESS WINDOW ERASE STEP WAIT TIME tNVS STEP
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HVEN STEP WAIT TIME tERAS STEP CLEAR ERAS STEP WAIT TIME tNVHL STEP CLEAR HVEN STEP WAIT TIME tRCV
ERASE OPERATION COMPLETE
Figure FLASH Erase Operation Flowchart
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Application Note FLASH Program Operation
FLASH Program Operation
MC68HC912DT128A/DG128A, programming FLASH memory done row-by-row basis, with each programming cycle writing word bytes). consists consecutive words bytes) with following boundaries:
Freescale Semiconductor, Inc.
$xx00-$xx3F $xx40-$xx7F $xx80-$xxBF $xxC0-$xxFF
During programming cycle, make sure that addresses being written within ranges specified. Attempts program addresses different ranges programming cycle will cause unintentional programming. example, programming from addresses $xx30 $xx6F will successful because addresses $xx30-$xx3F $xx40-$xx6F different rows.
WARNING:
FLASH attempts program rows. user should ensure that programmed data fits row, some FLASH addresses unintentionally programmed! programming algorithm outlined next specifies some delay times. Take care that exact delay times used. Excessive program time result program disturb condition, which case erased being programmed become unintentionally programmed.
NOTE:
avoid program disturb, must erased before byte that programmed. Figure shows flowchart programming algorithm.
NOTE:
user should make sure that proper window selected MISC PPAGE registers, proper FLASH addresses programmed.
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Freescale Semiconductor, Inc. Application Note
FLASH control register (FEECTL). configures FLASH memory program operation. Write word data word-aligned FLASH address within address range desired. Wait time, tNVS. Internal high voltage charged. HVEN bit. Internal high voltage applied programming row. Wait time, tPGS. tPGS program hold time. Write data word bytes) word-aligned FLASH address programmed. BOOTP FLASH module control register (FEEMCR) this range set, attempt program location will ignored. Wait time, tFPGM.
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tFPGM 1-word programming time. tFPGM actually includes total time from step flowchart) back step flowchart) additional word programming, from step step flowchart) last word. This total time must between both cases. Refer Figure Repeat steps until bytes within programmed. Clear bit. Disable programming operation. Wait time, tNVH. Internal high voltage discharged from row. Clear HVEN bit. Internal high voltage disabled. Wait time, tRCV. After time, tRCV, memory accessed normal read mode. While these operations must performed order shown, other unrelated operations occur between steps.
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Application Note FLASH Program Operation
exceed tFPGM maximum maximum. tFPGM defined step defined cumulative time that high voltage applied same before erase. tNVS (tFPGM (Number Words Programmed))
This routine assumes that being programmed initially erased.
STEP
PROGRAM
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STEP WRITE WORD WORD-ALIGNED ADDRESS STEP WAIT TIME tNVS STEP HVEN STEP WAIT TIME tPGS STEP WRITE DATA WORD WORD-ALIGNED FLASH LOCATION STEP WAIT TIME tFPGM STEP
Note: tFPGM total time from from This time must between
COMPLETED PROGRAMMING THIS ROW?
STEP
CLEAR
STEP WAIT TIME tNVH STEP CLEAR HVEN STEP WAIT TIME tRCV
PROGRAM OPERATION COMPLETE
Figure FLASH Program Operation Flowchart
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Freescale Semiconductor, Inc. Application Note EEPROM Functional Description
MC68HC912DT128A/DG128A devices contain Kbytes EEPROM memory. erased EEPROM reads logic programmed reads logic algorithm program byte aligned word bytes) time. erase operation used erase entire EEPROM Kbytes), bytes), word bytes), single byte time. Program erase operations facilitated through control bits memory-mapped registers. Details these operations appear later this application note. EEPROM memory module associated registers MC68HC912DT128A/DG128A are: $0800-$0FFF, EEPROM array, Kbytes $00EE, EEPROM modulus divider high register, EEDIVH $00EF, EEPROM modulus divider register, EEDIVL $00F0, EEPROM module configuration register, EEMCR $00F1, EEPROM block protect register, EEPROT $00F3, EEPROM control register, EEPROG
Freescale Semiconductor, Inc.
Programming tools available from Motorola. Contact local Motorola representative more information.
EEPROM Control Registers
EEPROM register consists five registers listed previously. modulus divider registers used timebase EEPROM clock. module configuration register controls several modes device well block protection SHADOW word. Timebase Initialization SHADOW Word more information these registers.
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Application Note EEPROM Block Protection
block protect register will discussed further EEPROM Block Protection, EEPROM control register used directly erasing programming algorithms. These registers described detail MC68HC912DT128A MC68HC912DG128A Technical Data.
EEPROM Block Protection
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block protection feature exists protect EEPROM from being inadvertently programmed erased. user specify which regions EEPROM protect using EEPROM block protect register, EEPROT. Table summarizes protection size addresses each EEPROT register. Table EEPROM Protected Ranges
Name BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 Protected Addresses $0800-$0BFF $0C00- $0DFF $0E00-$0EFF $0F00-$0F7F $0F80-$0FBF $0FC0-$0FFF Protected Size 1024 bytes bytes bytes bytes bytes bytes
Once user block protection, contents block protection register locked. this, PROTLCK EEPROM module configuration register, EEMCR.
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Freescale Semiconductor, Inc. Application Note Timebase Initialization SHADOW Word
function properly, this version EEPROM requires steady internal clock µs). This clock divided down from oscillator clock (EXTAL) value EEPROM modulus divider registers, EEDIVH EEDIVL. following formula determine proper divide value.
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EEDIV [EXTAL (Hz) 10-6) 0.5]
NOTE:
denotes round-down integer value EEPROM contains special word location called SHADOW word ($0FC0-$0FC1) which used required timebase. reset, value programmed into SHADOW word automatically loaded into EEDIVH:EEDIVL registers. Once timebase been SHADOW word, user will able EEPROM without considering clocking. Other than this timebase step, code backward compatible with MC68HC912DG128. timebase, follow these steps: Calculate EEDIV value. Write EEDIV into EEDIVH:EEDIVL registers. Program SHADOW word reflect EEDIV value desired values EEPROM module configuration register, EEMCR.
WARNING:
When EEDIV value EEPGM cannot set. SHADOW word maps into upper four bits EEMCR bits EEDIV registers. Table information SHADOW word mapping.
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Application Note EEPROM Erase Operation
Table SHADOW Word Mapping
High Byte $0FC0 Register EEMCR NOBDML EEMCR NOSHW EEMCR EEMCR EEDIVH EEDIV9 EEDIVH EEDIV8
Byte $0FC1 Register EEDIVL EEDIV7 EEDIVL EEDIV6 EEDIVL EEDIV5 EEDIVL EEDIV4 EEDIVL EEDIV3 EEDIVL EEDIV2 EEDIVL EEDIV1 EEDIVL EEDIV0
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Once timebase module information been defined programmed using SHADOW word, this location protected from unintended programming erasing. This feature controlled SHPROT EEPROM block protect register, EEPROT.
EEPROM Erase Operation
MC68HC912DT128A/DG128A, erasing done perbyte, per-word bytes), per-row bytes) bulk array Kbytes) basis. Word erasing requires start address aligned word. more information word alignment, Word Alignment. some protected locations included erase area, those bytes will affected only unprotected locations will erased. Refer Table block protection locations. There ways erase EEPROM. This done using standard mode erasing algorithm which includes defined delays, AUTO mode erasing algorithm employed. AUTO mode, there fixed delays, instead EEPGM polled. When cleared, erasing been completed.
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Freescale Semiconductor, Inc. Application Note EEPROM Standard Mode Erasing Algorithm
Figure shows flowchart standard mode erasing algorithm. Write BULKP, BYTE, bits EEPROM control register (EEPROG) specify erase size. ERASE specify erasing operation. EELAT control erasing latches. Table Erase Size Selection
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BULKP X(1)
BYTE
X(1)
Block Size Bulk erase Kbytes) erase bytes) byte word erase(2)
Don't care BYTE then value BULKP bits important. value written step byte, then operation will erase byte. value written word, then erase operation will erase word.
Write byte data EEPROM address write word data word-aligned EEPROM address. erase operation erasing entire array full row, then this write determines whether single byte word will erased. Therefore, address written must within desired erase block. EEPGM bit. Apply erasing voltage EEPROM.
NOTE:
value stored EEDIV registers zero, then EEPGM will set. Wait tERASE. tERASE high voltage hold time erasing. Clear EEPGM bit. Disable erasing voltage from array. Clear EELAT bit. EEPROM into normal mode.
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Application Note EEPROM AUTO Mode Erasing Algorithm
EEPROM AUTO Mode Erasing Algorithm
Figure shows flowchart AUTO mode erasing algorithm. Write BULKP, BYTE, bits EEPROM control register (EEPROG) specify erase size. ERASE specify erasing operation. EELAT control erasing latches. AUTO automatic erasing time termination. Table description BULKP, BYTE, bits.
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Write byte data EEPROM address write word data word-aligned EEPROM address. erase operation erasing entire array full row, then this write determines whether single byte word will erased. Therefore, address written must within desired erase block. EEPGM bit. Apply erasing voltage EEPROM.
NOTE:
value stored EEDIV registers zero, then EEPGM will set. Poll EEPGM until cleared internal timer. Clear EELAT bit. EEPROM into normal mode.
NOTE:
AUTO mode, careful about erase attempts protected areas. erase area (byte, word, row) protected area, erasing will successful EEPGM will never clear. user include step verify that addresses question protected, include timer ensure that software does trapped that step. bulk erase, even some memory areas protected, WILL result unprotected memory areas being erased.
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Freescale Semiconductor, Inc. Application Note
STANDARD ERASE
AUTO ERASE
STEP WRITE BYTE, ROW, BULKP ERASE SIZE ERASE EELAT STEP WRITE BYTE EEPROM ADDRESS WORD WORD-ALIGNED ADDRESS WITHIN RANGE ERASED
STEP WRITE BYTE, ROW, BULKP ERASE SIZE ERASE, EELAT, AUTO BITS STEP WRITE BYTE EEPROM ADDRESS WORD WORD-ALIGNED ADDRESS WITHIN RANGE ERASED STEP EEPGM EEPGM
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STEP
STEP WAIT TIME tERASE STEP CLEAR EEPGM STEP CLEAR EELAT
ERASE OPERATION COMPLETE
STEP EEPGM CLEARED? STEP CLEAR EELAT
ERASE OPERATION COMPLETE
Figure EEPROM Erasing Algorithm Flowcharts
EEPROM Program Operation
MC68HC912DT128A/DG128A, programming done per-byte per-aligned-word bytes) basis. more information aligned words, Word Alignment. some protected locations included program area, those bytes will affected only unprotected locations will altered. Table block protection locations. There ways program EEPROM. This done using standard mode programming algorithm which includes defined delays, AUTO mode programming algorithm employed. AUTO mode, there fixed delays, instead EEPGM polled. When cleared, programming been completed.
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Application Note EEPROM Standard Mode Programming Algorithm
EEPROM Standard Mode Programming Algorithm
Figure shows flowchart standard mode programming algorithm. Clear ERASE specify programming operation. EELAT control programming latches. Write byte data EEPROM address write word data word-aligned EEPROM address. size this write determines whether single byte word will programmed. Make sure that address byte aligned word. EEPGM bit. Apply programming voltage EEPROM. Wait tPROG. tPROG high voltage hold time programming. Clear EEPGM bit. Disable programming voltage from array. Clear EELAT bit. EEPROM into normal mode.
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Freescale Semiconductor, Inc. Application Note EEPROM AUTO Mode Programming Algorithm
Figure shows flowchart AUTO mode programming algorithm. Clear ERASE specify programming operation. EELAT control programming latches. AUTO automatic programming time termination.
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Write byte data EEPROM address write word data word-aligned EEPROM address. size this write determines whether single byte word will programmed. Make sure that address byte aligned word. EEPGM bit. Apply programming voltage EEPROM. Poll EEPGM until cleared internal timer. Clear EELAT bit. EEPROM into normal mode.
NOTE:
AUTO mode, programming block protected area, programming will successful EEPGM will never clear. user include step verify that addresses question protected, include timer ensure that software does trapped that step.
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Application Note Selective Programming
STANDARD PROGRAM
AUTO PROGRAM
STEP CLEAR ERASE EELAT STEP WRITE BYTE EEPROM ADDRESS WORD WORD-ALIGNED ADDRESS WITHIN RANGE PROGRAMMED STEP
STEP CLEAR ERASE, EELAT AUTO BITS STEP WRITE BYTE EEPROM ADDRESS WORD WORD-ALIGNED ADDRESS WITHIN RANGE PROGRAMMED STEP EEPGM EEPGM
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STEP WAIT TIME tPROG STEP CLEAR EEPGM STEP CLEAR EELAT
PROGRAM OPERATION COMPLETE PROGRAM OPERATION COMPLETE
STEP EEPGM CLEARED? CLEAR EELAT
STEP
Figure EEPROM Programming Algorithm Flowcharts
Selective Programming
each programming cycle, eight bits EEPROM memory programmed. possible program multiple bits same time. However, same programmed twice unless entire byte been erased first. This means that same byte location programmed eight times long individual written more than once. This referred selective programming. acceptable sequence Table shows same byte used eight program cycles without erase.
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Freescale Semiconductor, Inc. Application Note
Table Selective Programming
Acceptable Sequence Operation Erase Write Write Write Program Data 1111:1110 1111:1101 1111:1011 1111:0111 1110:1111 1101:1111 1011:1111 0111:1111 Value Memory 1111:1111 1111:1110 1111:1100 1111:1000 1111:0000 1110:0000 1100:0000 1000:0000 0000:0000 1111:1111 Unacceptable Sequence Operation Erase Write Write Write Write Program Data 1111:1110 1111:1001 1110:1111 1101:1000 Value Memory 1111:1111 1111:1110 1111:1000 1110:1000 Unknown
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Write Write Write Write Write Erase
EEPROM memory lifetime guaranteed 10-K program/erase cycles. However, using selective programming extends life cycle memory 8-fold since each only programmed 10-K times. This allows user program single byte 80-K times. programmed more than once before byte erased, Motorola cannot guarantee proper operation EEPROM array.
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Application Note Practical Considerations Programming/Erasing
Practical Considerations Programming/Erasing
ensure successful programming erasing FLASH and/or EEPROM MC68HC912DT128A/DG128A, user should consider following suggestions: Provide good ground. Provide clean constant clock during program erase operations. Filter signals leaving noisy environment. microcontroller programmed erased socket, ensure that pins making good electrical contact. Provide electrically noise-free environment MCU. supply should filtered within specification limits. Decoupling capacitors should placed very close VDD/VSS pairs. high current switching activity general vicinity should disabled during programming.
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Evaluating Delay Times Sample Code
FLASH algorithm include specific delay steps. These delay times defined MC68HC912DT128A/DG128A specification must considered when utilizing algorithm. ensure that each delay step meets specification, delay times have evaluated. delays sample code provided this application note were evaluated confirmed meet specification using general port pin. port initialized with high output signal. Just before entering delay, port toggled held until delay. actual delay times shown Table Table were periods measured oscilloscope. toggle port pin, instructions BSET, BCLR, were used. sample code also includes instructions used delay time evaluation.
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Freescale Semiconductor, Inc. Application Note
Table FLASH Erase Delay Times
Name Delay tNVS tERAS tNVHL tRCV Specified Duration Calculated Delay Time(1) 10.25 100.25 1.25 Actual Delay Time 10.8 E1)(3) E2)(3) 101.2 E3)(3) 1.76 E4)(3) Delta(2) 0.55 0.95 0.51
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Delay time calculated dividing number cycles delay speed MHz. Most delta times around Since instructions BSET require four internal cycles, this additional time comes from execution time instruction. cycles These times refer measured delays based running attached sample code. that code, points which measurements were taken defined these markers.
Table FLASH Program Delay Times
Name Delay tNVS tPGS Specified Duration Calculated Delay Time(1) 10.25 5.37 30.6 µs(4) tFPGM µs-40 30.25 µs(5) 5.375 1.25 Actual Delay Time 10.76 E5)(3) 5.88 E6)(3) 31.20 E7)(3) 30.80 E8)(3) 5.88 E9)(3) 1.76 (S10 E10)(3) Delta(2) 0.51 0.505 0.55 0.505 0.51
tNVH tRCV
Delay time calculated dividing number cycles delay speed MHz. Most delta times around Since instructions BSET require four internal cycles, this additional time comes from execution time instruction. cycles These times refer measured delays based running attached sample code. that code, points which measurements were taken defined these markers. word programmed last word being programmed Figure word programmed last word being programmed Figure
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Application Note FLASH Frequently Asked Questions
FLASH Frequently Asked Questions
These questions answers designed help user with frequent concerns.
Question
cannot program/erase FLASH memory all. What should consider make program/erase code work? Check following: FLASH arrays enabled? FLASH enabled/disabled ROMON miscellaneous system control register, MISC. Ensure that ROMON write these addresses. each step programming algorithm erasing algorithm) performed right order? sequence program erase operations interlocked hardware only prescribed order these operations will allow erase/program operations. However, other non-FLASH operations occur between steps shown. memory block where want program/erase unprotected? block protect feature FLASH present prevent unintentional programming erasing. block protect bits must cleared right page such that memory erased programmed unprotected. delay times (tPGS, tERAS, tNVHL, tNVS, tRCV, tNVH, tFPGM) within specification? Timing critical ensure proper FLASH operation. Delay times that long short alter FLASH performance point where does work reliable. Motorola does guarantee FLASH performance timing requirements being adhered
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Answer
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Freescale Semiconductor, Inc. Application Note
correct FLASH register being written enable erase program? MC68HC912DT128A/DG128A four FLASH arrays four separate sets control block protect registers. Make sure appropriate register being addressed PPAGE register. Refer FLASH Control Registers. enabled? computer operating properly timer that periodically checks device proper operation. enabled, COPRST register written periodically (with values then $AA) prevent reset. avoid issues, make sure that selected period long enough that feeding process performed during program/erase operation disable entirely during this operation.
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NOTE:
always enabled RESET normal modes disabled modifying COPCTL register. Motorola's recommended programming algorithm erasing algorithm) used your code? recommended programming algorithm ensures that FLASH programmed sufficient data retention with minimum program time. following this algorithm lead overprogramming, which risks program disturb.
Question
wanted erase only vector locations using page erase operation, memory addresses were also erased. anything wrong? vector locations ($FF00-$FFFF) located FLASH. MC68HC912DT128A/DG128A, minimum erase size Kbytes. 16-Kbyte configuration, memory addresses $4000 $7FFF $C000-$FFFF will erased time. 32-Kbyte configuration, bytes from $8000-$FFFF active page will erased.
Answer
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Application Note FLASH Frequently Asked Questions
Question Answer
What FLASH charge pump? charge pump dynamic (clocked) circuit which generates high voltages internally FLASH program erase nonvolatile memory. Users have access these voltages.
Question
MC68HC912DT128A/DG128A FLASH programs bytes) time. always have program entire row? necessary program entire row. include test make sure that programming stops when boundary ends, then addresses which programmed left they were before programming started. careful allow code attempt program beyond row; other addresses overwritten. Also note that, before reprogramming additional bytes this row, entire page must erased.
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Answer
Question
During program/erase process, execute interrupt service include additional steps? Unrelated (non-FLASH) steps included between steps program/erase algorithms long sequence steps remains consistent. However, interrupt service routines cause errors program erase timing lead corrupt missing data FLASH. Motorola does recommend interrupts during program erase operations. Make certain enter stop wait mode during program erase operation. High voltage exposed cells extended period cause permanent damage.
Answer
WARNING:
Question
executing program/erase code memory arrays. same array programmed/erased? question
Answer
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Freescale Semiconductor, Inc. Application Note
Question While running program/erase code memory arrays, other memory array programmed/erased? Yes. MC68HC912DT128A/DG128A four FLASH memory arrays. memory configured into 16-Kbyte windows (ROMTST array 11FEE32K used program erase code other arrays. code must addresses $4000-$7FFF $C000-$FFFF.
Answer
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Question Answer
program/erase FLASH arrays same time? While each array does have separate charge pump, address decode logic does allow more than programmed time. However, 32-Kbyte window configuration, memory such that four memory arrays overlap. This done setting ROMHM MISC register. this case, memory arrays programmed same time with same data. more information this feature, refer Resource Mapping Section MC68HC912DT128A MC68HC912DG128A Technical Data.
Question
When writing bytes data FLASH memory programming, does order written data matter? long bytes written within row, data latched programming operation.
Answer
Question
sending external data into MC68HC912DT128A/DG128A programming. speed this programming process? Excluding data download time, takes about seconds program Kbytes FLASH. data transferred higher communication baud rate parallel manner, overall programming time reduced. ideal situation would fast parallel transfer data during delay times associated with programming algorithm.
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Application Note FLASH Frequently Asked Questions
Question
need confirm memory contents after programming FLASH? recommended that code used program FLASH also include verification step ensure integrity data programmed into FLASH.
Answer
Question
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block memory FLASH array protected programming block protect register. When execute erase operation, will unprotected block erased? Yes. When FLASH array partially protected, erase operation erases non-protected bytes, leaves protected bytes they were before erasing.
Answer
Question Answer
What expected lifetime FLASH memory? minimum program/erase endurance data retention lifetime FLASH memory conditions found MC68HC912DT128A MC68HC912DG128A Technical Data.
Question Answer
What steps take prolong life FLASH memory? FLASH memory finite program/erase durability finite data retention lifetime. However, specification shows minimum lifetime considering worst case conditions applied part. general, FLASH will last longer used moderate temperatures (0-70C) program/erase cycles kept minimum.
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Freescale Semiconductor, Inc. Application Note
Question programming algorithm includes write steps. both writes need aligned word addresses? Yes. programming algorithm requires writes occur aligned words. This restriction applies both step step programming algorithm.
Answer
Question
What modes operation cause most noise? Program erase modes cause significant amount (electromagnetic interference) power supply noise high transient current demand charge pump. High accuracy (analog-to-digital) conversions possible while FLASH programming erasing.
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Answer
Question
memory configured 32-Kbyte windows. What value should PPAGE register program/erase array? There pages memory array. PPAGE register either page value program/erase associated array block when 32-K configuration. Table more information memory mapping.
Answer
Question
using memory 16-Kbyte window configuration, want write address $4000-$7FFF (page directly. This function working. Why? Direct access address locations $4000-$7FFF controlled ROMHM miscellaneous system control register, MISC. Ensure that ROMHM clear write these addresses. Note that programming erasing these locations requires setting PPAGE register
Answer
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Application Note FLASH Frequently Asked Questions
Question
32-Kbyte configuration, there four memory arrays four sets registers that must considered. Kbyte configuration, there eight sets registers? There always four physical arrays FLASH these devices, each array registers. 16-Kbyte configuration, registers shared between Pages 0&1, 2&3, 4&5, 6&7. write registers will modify their contents with either page being PPAGE register. FLASH Memory Mapping more information.
Answer
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Question
attempted program/erase section memory, different section memory programmed/erased instead. What wrong? MC68HC912DT128A/DG128A Kbytes FLASH memory, they require page accessing program. only does proper address have used programming erasing algorithm, PPAGE register must pointing desired page. Table more information.
Answer
Question
memory configured 16-Kbyte windows. Will erase function erase active 16-Kbyte window, will erase entire 32-Kbyte array that active window entire 32-Kbyte window will erased, unless boot block protection set. that case, non-protected bits, Kbytes array, will erased.
Answer
Question
erasing algorithm uses write determine which array erase. Does matter which address that write? long address written aligned word, address within array. Word Alignment more information.
Answer
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Freescale Semiconductor, Inc. Application Note EEPROM Frequently Asked Questions
Question cannot program/erase EEPROM memory all. What should consider make program/erase code work? Check following: EEPROM array enabled? EEPROM enabled/disabled EEON Initialization Internal EEPROM position register, INITEE. Ensure that EEON write these addresses. program correct divider values EEDIV registers (EEDIVH EEDIVL)? EEDIVH EEDIVL registers loaded from SHADOW word ($0FC0-$0FC1) reset. must first calculate desired EEDIV value crystal frequency being used. After that, either write that value EEDIVH:EEDIVL temporary operation, program that value into SHADOW register reset part. this must done before executing erase program operation. normal mode, EEDIV registers write-once registers. Timebase Initialization SHADOW Word more information. recommended programming erasing algorithms your code? EEPROM consists FLASH memory surrounded logic state machine. Motorola's recommended programming algorithm ensures that EEPROM programmed sufficient data retention minimum program time. Motorola does guarantee performance EEPROM recommended algorithms followed. each step programming erasing algorithms performed right order? sequence program erase operations interlocked hardware only prescribed order these operations occur. However, other non-EEPROM operations occur between steps shown.
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Answer
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Application Note EEPROM Frequently Asked Questions
memory block where want program/erase unprotected? block protect feature EEPROM present prevent unintentional programming erasing. block protect bits must cleared such that memory erased programmed unprotected.
delay times (tPROG, tERASE) within specification? standard mode, timing critical ensure proper EEPROM operation. Delay times that long short alter EEPROM performance point where does work reliable. Motorola does guarantee EEPROM performance wrong delay times used.
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array mapped where expect EEPROM mapped 4-Kbyte boundary within address space. upper four bits initialization internal EEPROM position register, INITEE, sets EEPROM address block. These bits clear reset.
Question Answer
need constant timebase? EEPROM actually FLASH cell surrounded logic state machine. state machine requires accurate clock source applying high voltage during erase program operations.
Question Answer
What benefit using AUTO mode? When AUTO EEPROM programming erasing algorithms, programming erasing time much shorter than when standard EEPROM algorithms. Whenever programming erasing done, EEPGM automatically cleared, eliminating wait fixed delay time. Furthermore, since delay time necessary, delay routine required your code.
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Question During program/erase process, execute interrupt service include additional steps? Unrelated (non-EEPROM) steps included between steps program/erase algorithms long sequence steps remains consistent. However, interrupt service routines cause errors program erase timing lead corrupt missing data EEPROM. Motorola does guarantee performance EEPROM interrupts masked during program erase operation.
Answer
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Question Answer
program each same EEPROM location successively? However, same byte location successively programmed using selective programming. Refer Selective Programming.
Question Answer
charge pump used both EEPROM FLASH arrays? Each FLASH array separate charge pump, EEPROM charge pump.
Question
need confirm memory contents after programming EEPROM? recommended that code used program EEPROM also include verification step ensure integrity data programmed.
Answer
Question Answer
What expected lifetime EEPROM memory? minimum program/erase endurance data retention lifetime EEPROM memory conditions found MC68HC912DT128A MC68HC912DG128A Technical Data.
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Application Note EEPROM Frequently Asked Questions
Question Answer
What steps take prolong life EEPROM memory? EEPROM memory finite program/erase durability finite data retention lifetime. However, specification quotes minimum guaranteed lifetime considering worst case conditions applied part. general, EEPROM array will last longer program/erase cycling kept minimum temperature kept nominal level (0-70oC).
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Question
program/erase EEPROM maximum temperature limits specified life part? Yes. Program/erase cycle durability specified 10-K minimum. However, exceeding that value recommended. Reading EEPROM occur continuously over life product.
Answer
Question
have calculated EEDIV value tried program SHADOW word locations. value programming into this location? This have several causes. instance: What value SHPROT EEPROM block protect register, EEPROT? this set, SHADOW word protected from programming erasing. Have reset part after programming SHADOW word? SHADOW word loaded into EEDIV register only reset. trying read SHADOW word locations $0FC0-$0FC1? These EEPROM locations mapped SHADOW word ONLY when NOSHW EEPROM module configuration register, EEMCR, clear.
Answer
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Freescale Semiconductor, Inc. Application Note
Question cleared EEPROM block protection register, EEPROT. still able program EEPROM addresses? While have executed erase register, erase function have been successful. First check value PROTLCK EEPROM module configuration register, EEMCR. PROTLCK set, then EEPROM block protect register cannot changed.
Answer
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Question
ignore SHADOW word directly program EEDIV value into EEDIVH EEDIVL registers? Yes. normal modes, these write-once registers (the EEPROM latch control, EELAT, must off). special modes, these registers written time, with same condition mentioned earlier.
Answer
Question
AUTO same time other bits EEPROM control register, EEPROG? Yes. sample code sets AUTO same time that BULKP, BYTE, ROW, ERASE, EELAT bits written. EEPGM same time.
Answer
Question
What happens erase/program protected range EEPROM? unprotected areas change, protected areas unaffected.
Answer
Question
What happens when SHADOW word used? What happens locations $0FC0 $0FC1? program divider value? First all, SHADOW word distinct place device. When SHADOW word enabled NOSHW EEPROM module configuration register, EEPROM addresses $0FC0 $0FC1 SHADOW word. When SHADOW word disabled, locations normal EEPROM locations.
Answer
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Application Note FLASH Assembly Source Code Flowcharts
Whether location enabled not, reset still loads SHADOW word into EEDIVH:EEDIVL registers. temporary operation, change divider value writing directly those registers. longterm operation, want these locations normal EEPROM, then will need execute sequence where SHADOW word enabled, programmed, disabled.
Question
Even SHADOW word enabled, still just write divider value EEDIVH:EEDIVL registers once part reset? Yes. normal modes, these registers once-write registers, special modes, they written time.
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Answer
FLASH Assembly Source Code Flowcharts
main routine SSTflash.mrt initializes device erasing programming operations before calling subroutines themselves. routine starts setting FLASH desired filling data buffer with values program into array. then calls FlashErase subroutine which follows algorithm listed this application note. After erasing array data, main routine calls ProgRow program bytes). SSTflash.mrt also includes verification step after programming completed. FlashErase ProgRow subroutines follow flowcharts shown Figure Figure closely. flowchart also included ms_delay subroutine which generates delays greater than millisecond.
NOTE:
These routines must executed 8-MHz frequency meet expected delay times. flowcharts SSTflash.mrt, FlashErase, ProgRow, ms_delay Figure Figure Figure Figure respectively.
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Freescale Semiconductor, Inc. Application Note
SSTflash.mrt
TURN CLOCK MONITOR
FILL BUFFER WITH BYTES DATA PROGRAM INTO FLASH
SIZE MEMORY WINDOW
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PAGE ERASE
CLEAR BLOCK PROTECTION
LOAD FLASH ADDRESS WITHIN ADDRESS RANGE ERASED INTO INDEX REGISTER
CALL FlashErase ERASE ARRAY
LOAD PROGRAMMING START ADDRESS INTO INDEX REGISTER
LOAD BUFFER START ADDRESS INTO INDEX REGISTER
CALL ProgRow PROGRAM FLASH
BLOCK PROTECTION
VERIFY PROGRAMMED DATA AGAINST BUFFER DATA
PROGRAMMING FAILURE
DATA MATCH?
PROGRAMMING SUCCESS
Figure FLASH Main Routine Flowchart
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Application Note FLASH Assembly Source Code Flowcharts
FlashErase (SSTflash.srt)
DISABLE INTERRUPTS STEP ERAS STEP WRITE FLASH ADDRESS WINDOW ERASE
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STEP WAIT TIME tNVS STEP HVEN STEP CALL ms_delay WAIT tERAS STEP CLEAR ERAS STEP WAIT TIME tNVHL STEP CLEAR HVEN STEP WAIT TIME tRCV
ENABLE INTERRUPTS
RETURN
Figure Subroutine FlashErase Flowchart
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Freescale Semiconductor, Inc. Application Note
ProgRow (SSTflash.srt)
DISABLE INTERRUPTS STEP STEP WRITE DATA WORD FLASH START ADDRESS
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STEP WAIT TIME tNVS STEP HVEN STEP STEP WAIT TIME tPGS STEP WAIT TIME tNVH WORDS PROGRAM counter STEP CLEAR HVEN STEP WAIT TIME tRCV CLEAR
STEP WRITE DATA WORD FLASH LOCATION
FLASH NEXT WRITE STEP WAIT TIME tFPGM
ENABLE INTERRUPTS
RETURN
DECREMENT counter
STEP
COMPLETED PROGRAMMING THIS ROW? (counter
Figure Subroutine ProgRow Flowchart
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Application Note FLASH Assembly Source Code
ms_delay (SSTflash.srt)
GENERATE MILLISECOND DELAY TIME DEPENDING VALUE times
RETURN
Figure Subroutine Delay Flowchart
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FLASH Assembly Source Code
FLASH Memory Programming Erasing MC68HC912DT128A/DG128A File Name: SSTflash.mrt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM012Z (P&E Microcomputer Systems, Inc.) Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u Flash Memory Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: DATA Subroutine Called: FlashErase, ProgRow Full Functional Description Routine Design: SSTflash.mrt main routine Flash programming erasing operations MC68HC912DT128A MC68HC912DG128A.* This main routine calls programming erasing algorithms SSTflash.srt file. This programming algorithm minimizes amount time needed program FLASH memory. consists consecutive bytes FLASH memory within specified address ranges. Before programming operation executed, bytes programming data stored
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Freescale Semiconductor, Inc. Application Note
buffer. Note: This routine must executed frequency 8MHz because each delay time algorithm calculated with this frequency. Motorola reserves right make changes without further notice product herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product, circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts.* Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death* occur. Should Buyer purchase Motorola products such intended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, any* claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent* regarding design manufacture part. Motorola Motorola symbol registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. ***** Include Files ***** NOLIST $INCLUDE "912DG128A_memory.frk" ;Equates MC68HC912DG/DT128A registers bits used this routine $INCLUDE "SSTflash.var" ;RAM variable definitions LIST ***** Main Routine ***** RAM+$50 ;The code start address ;The below this address used Start: FLASH data buffer spare data storage movb #$4000 #$8F,COPCTL ;Set Stack Pointer ;Enable Clock Monitor Function loss clock detected, take appropriate action
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Application Note FLASH Assembly Source Code
ldaa Data_load: staa inca cmpa
#$00 DATA,x
;Fill buffer with bytes data program into FLASH (ie. 01,02,03,.,3E,3F,40)
#!65 Data_load
movb
#$81,MISC
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;Select Window Select either Window Window. Default 16K. NOTE: This register also controls narrow data stretch bits. ;Select PPAGE=1 Select desired page Boot Block this page protected, clear BOOTP bit. NOTE: FEELCK ($00F4) must ;Load Index Register with address within page. address with aligned word selected ;Erase whole selected page ;Load Index Register with programming start address ($xx00, $0xx40, $0080, $xxC0) ;Load Index Register with buffer start address ;Program words) ;Set BOOTP protect Boot Block ;After desired block programmed, recommended that programmed data verified ;Load Index Register with buffer start address ;Load Index Register with verifying start address ;Read data from FLASH location ;Compare read data with data Buffer ;When verify fails, branch Error
movb
#$01,PPAGE
bclr
FEEMCR,BOOTP.
#$8002
FlashErase #$BF40
bset Verify: movb Verify_Loop:
#DATA ProgRow FEEMCR,BOOTP.
#!32,COUNTER #DATA #$BF40
Error COUNTER Success
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Freescale Semiconductor, Inc. Application Note
Success: Error: Programming Successful program Programming Failed Take appropriate action
Verify_Loop
***** Subroutine Body Includes Section ***** $INCLUDE "SSTflash.srt" ;SST FLASH subroutine
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FLASH Memory Programming Erasing MC68HC912DT128A/DG128A File Name: SSTflash.var Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM12Z (P&E Microcomputer Systems, Inc.) Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u Flash Memory Used (Bytes): Description: variable definitions main routine SSTflash.mrt. ***** Variables ***** DATA data bytes that will programmed COUNTER byte storage word number contained TIMES byte which delay time will determined
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Application Note FLASH Assembly Source Code
FLASH Memory Program Erase Subroutines MC68HC912DT/DG128A File Name: SSTflash.srt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM12Z (P&E Microcomputer Systems, Inc.) Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u Flash Memory Module Size (Bytes): FlashErase ProgRow ms_delay Stack Space Used (Bytes): FlashErase ProgRow WriteFLCR ms_delay Used (Bytes): FlashErase ProgRow ms_delay Global Variable(s) Used: FlashErase None ProgROW DATA ms_delay None Submodule(s) Called: EraseRoutine ms_delay ProgRow ms_delay ms_delay None Calling Sequence: FlashErase, ProgRow ms_delay Entry Label: FlashErase, ProgRow, ms_delay Entry Conditions: FlashErase Flash address defined Index Register ProgRow Flash address defined Index Register Buffer address defined Index Register programming bytes located variables DATA ms_delay Delay variable passed TIMES Number Exit Points: Exit Label: FlashErase FlashErase_End ProgRow ProgRow_End ms_delay ms_delay_End Exit Conditions: FlashErase None ProgRow None ms_delay None
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Freescale Semiconductor, Inc. Application Note
Full Functional Description Subroutine: SSTflash.srt consists primary subroutines called FlashErase* ProgRow. These routines demonstrate FLASH erasing programming algorithms, respectively. routines also call another subroutine ms_delay. Since delay times must precisely successful FLASH programming erasing, additional* software added measure delay times. This code included comments throughout file. recommended that user verify delay times before using this software production. Note: Each delay time related FLASH program erase operations calculated with frequency 8MHz. ***** FLASH Erase Subroutine ***** FlashErase: Delay Time Evaluation Initialize Port output high bset PORTA,PA0. ;Set Port bset DDRA,DDRA0. ;Select output Port ;Disable maskable interrupts bset FEECTL,ERAS. ;Step ERAS
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;Step Write FLASH address with aligned word within page erased Delay Time tNVS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$1B ;Step Wait time tNVS cycles cycles (10.25us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port bset FEECTL,HVEN. ;Step HVEN
Delay Time tERAS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port movb #!8,TIMES ;Step Wait time tERAS (8.0ms)
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Application Note FLASH Assembly Source Code
ms_delay
Delay Evaluation: Point bset PORTA,PA0. ;Set Port bclr FEECTL,ERAS. ;Step Clear ERAS
Delay Time tNVHL Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port
Freescale Semiconductor, Inc.
dbne
#$010B
;Step Wait time tNVHL 267) cycles cycles (100.25us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port bclr FEECTL,HVEN. ;Step Clear HVEN
Delay Time tRCV Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$03 ;Step Wait time tRCV cycles cycles (1.25us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port ;Enable maskable interrupts FlashErase_End: ***** FLASH Programming Subroutine ***** ProgRow: Delay Time Evaluation Initialize Port output high bset PORTA,PA0. ;Set Port bset DDRA,DDRA0. ;Select output Port ;Disable maskable interrupts bset FEECTL,PGM. ;Step ;Step Write start address
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Freescale Semiconductor, Inc. Application Note
with word data Delay Time tNVS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$1B ;Step Wait time tNVS cycles cycles (10.25us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port
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bset
FEECTL,HVEN.
;Step HVEN
Delay Time tPGS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$0E ;Step Wait time tPGS cycles cycles (5.375us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port ;-;- tFPGM defined total time from writing data word writing next data word. (labelled below). last word programmed, tFPGM defined time from writing data word ("A") clearing WriteFLCR routine). Both these loops should executed time between word-to-next-word time cycles (30.6 us). word-to-PGM time cycles (30.25 us). ;-movb #!32,COUNTER ;Write total word number ROW, COUNTER Copy_Loop: movw
;Step Copy word data from buffer appropriate FLASH location ("A") Delay Time word-to-next-word Evaluation (one loop period starting from point point Measure level period Port using scope Delay Evaluation: Point PORTA ;Complement Port
0,Y,0,X
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Application Note FLASH Assembly Source Code
Delay Time word-to-PGM Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ;Set next Flash programming location ;Set next Buffer location
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ldaa dbne
#$4C
;Step Delay, part tFPGM cycles cycles (28.625us) ;Step Repeat step through until bytes within programmed ;Step Clear
COUNTER Copy_Loop
bclr
FEECTL,PGM.
Delay Evaluation: Point bset PORTA,PA0. Delay Time tNVH Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$0E ;Step Wait time tNVH cycles cycles (5.375us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port bclr FEECTL,HVEN. ;Step Clear HVEN Delay Time tRCV Evaluation (Time between points E10) Measure level period Port using scope Delay Evaluation: Point bclr PORTA,PA0. ;Clear Port ldaa dbne #$03 ;Step Wait time tRCV cycles cycles (1.25us)
Delay Evaluation: Point bset PORTA,PA0. ;Set Port
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Freescale Semiconductor, Inc. Application Note
;Enable maskable interrupts ProgRow_End: ***** Delay Routine ***** This routine generates unit millisecond delay depending value "TIMES". example times=1, delay time 1ms. Delay 1597 (TIMES 1597 Frequency (8000 TIMES 8MHz Initializations required: value "TIMES" Values returned: None ms_delay: #$063E cyc. ms_loop: subd ms_delay_End: #$01 ms_loop TIMES TIMES ms_delay cyc. branch taken, cyc. branch taken, cyc. taken, cyc. branch cyc.
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taken, cyc. branch cyc.
EEPROM AUTO Mode Source Code Flowcharts
main routine AutoEEPROM.mrt initializes device erasing programming operations. sets clock monitor timebase divider EEPROM memory specifies value location programmed. routine then performs EEPROM erase program operations calling AutoRoutine twice. AutoRoutine subroutine follows flowcharts shown Figure Figure closely. flowcharts AutoEEPROM.mrt AutoRoutine Figure Figure respectively.
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Application Note EEPROM AUTO Mode Source Code Flowcharts
AutoEEPROM.mrt
TURN CLOCK MONITOR
STORE CLOCK DIVIDER VALUE EEDIVH:EEDIVL
STORE WORD DATA DATA BUFFER
Freescale Semiconductor, Inc.
LOAD WORD-ALIGNED FLASH ADDRESS PROGRAM ERASE INDEX REGISTER
CLEAR BLOCK PROTECTION
ERASE SIZE ACCUMULATOR
CALL AutoRoutine ERASE BLOCK
SELECT PROGRAM ACCUMULATOR
CALL AutoRoutine PROGRAM WORD
BLOCK PROTECTION
Figure EEPROM AUTO Mode Main Routine
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Freescale Semiconductor, Inc. Application Note
AutoRoutine (AutoEEPROM.srt)
DISABLE INTERRUPTS STEP SAVE SELECTED BULKP, ROW, BYTE, ERASE BITS INTO EEPROG; EELAT AUTO BITS STEP COPY WORD DATA FROM BUFFER ADDRESS INDEX REGISTER STEP EEPGM
Freescale Semiconductor, Inc.
STEP EEPGM CLEARED? STEP CLEAR EELAT
EEPROG RESET VALUE
ENABLE INTERRUPTS
RETURN
Figure Subroutine AutoEEPROM Flowchart
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Application Note EEPROM AUTO Mode Assembly Source Code
EEPROM AUTO Mode Assembly Source Code
EEPROM AUTO Programming Erasing MC68HC912DT128A/DG128A File Name: AutoEEPROM.mrt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM12Z (P&E Microcomputer Systems, Inc.) Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u EEPROM Memory Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: DATA Subroutine Called: AutoRoutine Full Functional Description Routine Design: AutoEEPROM.mrt main routine EEPROM programming erasing operations using AUTO mode. demonstrates AUTO programming erasing MC68HC912DT128A MC68HC912DT128A. Note: EEDIV value calculated with oscillator frequency 16MHz. user must recalculate EEDIV value different oscillator frequency. ***** Program Specific Equates ***** auto_BULKerase. %00100110 ;Select BULK Erase: AUTO, ERASE, EELAT bits, clear BULKP auto_ROWerase. %00101110 ;Select Erase: AUTO, ROW, ERASE, EELAT bits, clear BULKP auto_WORDerase. %10110110 ;Select WORD Erase: AUTO, BYTE ERASE EELAT bits auto_WORDprogram. %10100010 ;Select WORD Program: AUTO EELAT bits ***** Include Files *****
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Application Note
NOLIST $INCLUDE
"912DG128A_memory.frk"
;Equates MC68HC912DG/DT128A registers bits used this routine
$INCLUDE "AutoEEPROM.var" ;RAM variable definitions LIST ***** Main Routine ***** RAM+$50 ;The code start address ;The below this address used Start: EEPROM data buffer spare data storage
Freescale Semiconductor, Inc.
movb
#$4000 #$8F,COPCTL
;Set Stack Pointer ;Enable Clock Monitor loss clock detected, take appropriate action. Other bits set/cleared user application. SHADOW word does constant timebase 35us, write EEDIVH EEDIVL, respectively since oscillator frequency 16MHz ;<CAUTION> When EEDIVH:EEDIVL=00:00, EEPGM automatically cleared These registers "write once" normal mode ;Write word data $55AA buffer ;Load Index Register with address where aligned word should erased programmed ;Unprotect block which will erased programmed ;<CAUTION> When programming erasing location protected (except with bulk erase), EEPGM automatically cleared ;Select Bulk, Word Erase ;Erase selected EEPROM size using AUTO Mode ;Select Word Program ;Program word using AUTO Mode ;Protect programmed block
movw
#$0230,EEDIVH
movw
#$55AA,DATA #$0E02
bclr
EEPROT,BPROT3.
ldaa
#auto_WORDerase. AutoRoutine
ldaa bset
#auto_WORDprogram. AutoRoutine EEPROT,BPROT3.
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Application Note EEPROM AUTO Mode Assembly Source Code
***** Subroutine Body Includes Section ***** $INCLUDE "AutoEEPROM.srt" ;Auto EEPROM subroutines
Freescale Semiconductor, Inc.
EEPROM AUTO Programming Erasing MC68HC912DT128A/DG128A File Name: AutoEEPROM.var Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM12Z (P&E Microcomputer Systems, Inc.) Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u EEPROM Memory Used (Bytes): Description: variable definitions AutoEEPROM.mrt. ***** Variables ***** DATA ;one data word that will programmed
EEPROM AUTO Program Erase Subroutine MC68HC912DT128A/DG128A File Name: AutoEEPROM.srt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: July 2001 Current Release Written Kazue Kikuchi Darci Ernst Motorola Applications Engineering Austin, Assembled Under: CASM12Z (P&E Microcomputer Systems, Inc.)
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Freescale Semiconductor, Inc. Application Note
Ver.: 3.11 Part Family Software Routine Works With: HC12 0.5u EEPROM Memory Module Size (Bytes): AutoRoutine Stack Space Used (Bytes): AutoRoutine Used (Bytes): AutoRoutine Global Variable(s) Used: AutoRoutine DATA Calling Sequence: AutoRoutine Entry Label: AutoRoutine Entry Conditions: AutoRoutine byte setup (BULKP, AUTO, BYTE, ROW, ERASE, EELAT bits) defined accumulator bytes address defined Index Register programming word located variable DATA (the erasing operation required) Number Exit Points: Exit Label: AutoRoutine AutoRoutine_End Exit Conditions: AutoRoutine None Full Functional Description Subroutine: AutoEEPROM.srt contains primary subroutine called AutoRoutine. This demonstrates EEPROM erasing programming AUTO mode. ***** EEPROM AUTO Program Erase Subroutine ***** AutoRoutine: ;Disable maskable interrupts staa EEPROG ;Step Select BULKP, BYTE, ROW, ERASE bits, EELAT AUTO bits DATA ;Step Copy word data from buffer address specified index register ;Step EEPGM
Freescale Semiconductor, Inc.
bset
EEPROG,EEPGM.
Clear_EEPGM: ;Step Wait until EEPGM cleared brset EEPROG,EEPGM.,Clear_EEPGM ;<CAUTION> When EEDIVH:EEDIVL=00:00 programming/erasing location protected (except bulk erase), EEPGM automatically cleared bclr movb AutoRoutine_End: EEPROG,EELAT. #$80,EEPROG ;Step Clear EELAT ;Write reset value EEPROG register ;Enable maskable interrupts
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Application Note EEPROM AUTO Mode Assembly Source Code
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
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Motorola, Inc., 2001
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