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AN2156 Freescale Semiconductor, Inc. Programming Erasing FLA


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AN2156
Freescale Semiconductor, Inc.
Programming Erasing FLASH EEPROM Memories MC68HC908AS60A/AZ60A
Adeela Gill Kazue Kikuchi Transportation Standard Products Group Austin, Texas
Introduction
Motorola released microcontrollers (MCU), MC68HC908AS60A (AS60A) MC68HC908AZ60A (AZ60A), products M68HC08 Family low-cost, high-performance devices. AS60A AZ60A offer many features, including: 8.4-MHz internal frequency Kbytes FLASH memory FLASH data security Kbyte EEPROM with security option Kbytes on-chip On-chip charge pump
This application note explains FLASH EEPROM MC68HC908AS60A/AZ60A provides example software program erase operations. These algorithms written M68HC08 assembly code.
Motorola, Inc., 2001
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Freescale Semiconductor, Inc. Application Note
This code available download from http://www.motorola.com/mcu which Motorola's Semiconductor Product Sector's microcontroller site. topics covered this application note include: Memory Overview MC68HC908AS60A/AZ60A MC68HC908AS60/AZ60 FLASH Functional Description FLASH Block Protection FLASH Control Block Protect Registers FLASH Erase Operations FLASH Program Operation EEPROM Functional Description Configuration Register EEPROM Timebase Divider Control Registers EEPROM Timebase Divider Initialization EEPROM Block Protection Security Standard EEPROM Erase Operation AUTO Mode EEPROM Erase Operation Standard EEPROM Program Operation AUTO Mode EEPROM Program Operation Selective Programming Practical Considerations Programming/Erasing Evaluating Delay Times Sample Code FLASH Frequently Asked Questions EEPROM Frequently Asked Questions FLASH Assembly Source Code EEPROM AUTO Mode Assembly Source Code
Freescale Semiconductor, Inc.
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Application Note Memory Overview
Memory Overview
FLASH cell utilized MC68HC908AS60A/AZ60A industry proven split gate cell available from Silicon Storage Technology (SST) 0.5-micron geometry. More information FLASH cell available http://www.ssti.com which SST's site. cell uses channel electron injection programming Fowler-Nordheim tunneling erasing. programming voltages generated internally charge pump from single connection VDD. With quick programming time organization FLASH array into 64-byte rows, entire 60-Kbyte memory programmed less than seconds. cell field-proven reliability endurance. Motorola already four devices with this technology that have been qualified AEC-Q1000 Stress Test. MC68HC908AS60A/AZ60A, 60-Kbyte memory separated into arrays, each having charge pump. Decode logic programming circuitry allows only array programmed time. EEPROM simple extension FLASH technology. Motorola added logic state machine around EEPROM make programming erasing code older (0.65-µ technology) M68HC08 Family devices compatible with these devices (0.5-µ technology). However, new, faster technique available programming/erasing EEPROM. using AUTO EEPROM control register, fixed delays eliminated. Instead, software polls program/erase complete flag. complete description this technique included AUTO Mode EEPROM Erase Operation AUTO Mode EEPROM Program Operation.
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Application Note MC68HC908AS60A/AZ60A MC68HC908AS60/AZ60
MC68HC908AS60A/AZ60A devices discussed this application note technology shrink from previous MC68HC908AS60/AZ60 devices. addition transistor size reduction, changes were made devices. These include:
Freescale Semiconductor, Inc.
Using FLASH technology Adding special program/erase protection option EEPROM. Relocating several registers devices
Table lists registers that were moved parts. Also, divider EEPROM registers discussed Configuration Register EEPROM Timebase Divider Control Registers registers specific parts. Table Register Address Differences
MC68HC908AS60/ AZ60 FLASH-1 control register (FL1CR) FLASH-2 control register (FL2CR) EEPROM-2 control register (EE2CR) EEPROM-2 array configuration register (EE2ACR) EEPROM-2 nonvolatile register (EE2NVR) $FE0B $FE11 $FE19 $FE1B $FE18 MC68HC908AS60A/ AZ60A $FF88 $FE08 $FF7D $FF7F $FF7C
Additional differences between devices listed detail Table Table
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Application Note MC68HC908AS60A/AZ60A MC68HC908AS60/AZ60
Table FLASH Differences
MC68HC908AS60/AZ60 Technology clock frequency requirement (2TS) clock must such that, when divided prescaler yields frequency MHz-2.5 Multiple pulses using margin read bytes Typical Typical 77.5 Minimum sizes: bytes, bytes, Kbytes, Kbytes MC68HC908AS60A/AZ60A (SST) Minimum Maximum
Algorithm
fixed pulse bytes Minimum 1.94 Minimum 1.85 bytes: minimum Kbytes: minimum
Freescale Semiconductor, Inc.
Bit-erased state Programming minimum size bytes programming time Kbytes programming time Erase size time Erase/program block protect register (Note: Does refer erasing/programming array)
High voltage required
High voltage required
Block protect size
128-byte increments except that locations $7F00- $7FFF $FF00-$FFFF (255 bytes each) protected block Minimum 10,000 cycles Minimum 10,000 cycles Minimum years
erase endurance program endurance Data retention
Minimum cycles Minimum cycles Minimum years
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Freescale Semiconductor, Inc. Application Note
Table EEPROM Differences
MC68HC908AS60/AZ60 EExDIVHNVR EExDIVLNVR registers EExDIVH EExDIVL registers EEDIVCLK CONFIG-2 EEBCLK EEPROM control register Timebase reference clock frequency MC68HC908AS60A/AZ60A value programmed these registers automatically loaded into EExDIVH/L registers reset. These registers either loaded from EExDIVH/LNVR registers must written directly constant 35-µs timebase. Timebase reference clock selection (bus clock CGMXCLK)
EEPROM clock selection (bus clock internal oscillator)
Freescale Semiconductor, Inc.
kHz-16 MC68HC908AS60/AZ60 EEPROM algorithm used. However, EEDIV initialization required proper prescaler value. Program/erase cycle terminated internal time auto mode. Minimum standard mode Minimum standard mode Minimum standard mode Minimum standard mode Erase operation required before programming. same byte successively programmed only selective programming used.
Algorithm
Fixed delays
Bit-erased state Programming time byte Erasing time byte Erasing time block Erasing time bulk
Minimum Minimum Minimum Minimum Erase operation necessary before programming. Recovery time required stabilize after clearing EEOFF recovering from stop mode. Minimum 10,000 cycles Minimum years
Successive programming
Recovery time lower power consumption Write/erase cycles Data retention
Recovery time required.
Minimum 10,000 cycles Minimum years
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Application Note FLASH Functional Description
FLASH Functional Description
FLASH memory MC68HC908AS60A/AZ60A physically consists independent arrays each with bytes block protection. erased reads logic programmed reads logic Program erase operations facilitated through control bits memory-mapped registers. Details these operations appear later this application note.
Freescale Semiconductor, Inc.
Memory FLASH array organized into byte pages, each page subdivided into rows bytes each. minimum erase block size single page bytes. Programming performed per-row basis, bytes time. address ranges user memory, control registers, block protect registers, vectors listed here. FLASH memory MC68HC908AS60A/AZ60A consists $0450-$05FF, FLASH-2 array, bytes (See Note) $0E00-$7FFF, FLASH-2 array, 29,184 bytes $8000-$FDFF, FLASH-1 array, 32,256 bytes $FE08, FLASH-2 control register, FL2CR $FF80, FLASH-1 block protect register, FL1BPR $FF81, FLASH-2 block protect register, FL2BPR $FF88, FLASH-1 control register, FL1CR $FFD2-$FFD3, $FFDA-$FFFF, vector space; subset FLASH-1 area, bytes (See Note)
NOTE:
memory MC68HC908AZ60A differs slightly from MC68HC908AS60A. MC68HC908AZ60A: FLASH-2 array continuous. divided into three sections: $0450-$04FF (176 bytes), $0580-$05FF (128 bytes), $0E00-$7FFF (29,184 bytes) $FFCC-$FFD1 $FFD4-$FFD9 also defined vector addresses (total vector size bytes).
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Freescale Semiconductor, Inc. Application Note
64-byte address boundaries MC68HC908AS60A/AZ60A are: $xx00-$xx3F $xx40-$xx7F $xx80-$xxBF $xxC0-$xxFF When programming FLASH, exact programming time must used program row. Excessive program time result program disturb condition, which case erased being programmed becomes unintentionally programmed. Program disturb avoided using recommended algorithm. FLASH Program Operation.
Freescale Semiconductor, Inc.
NOTE:
security feature prevents viewing FLASH contents.1 Programming tools available from Motorola. Contact local Motorola representative more information.
FLASH Block Protection
protect contents FLASH array from being inadvertently programmed erased run-away code user application, FLASH block protect register option implemented. This register composed nonvolatile bytes within FLASH-1 array, with byte FLASH array. Once block protect bits FLxBPR registers, defined address ranges protected from being programmed erased. FLASH Block Protection description address ranges. However, protected memory block needs programmed erased, block protection overridden applying voltage during erase program operations.
NOTE:
vector locations FLxBPR registers located same page. FLxPBR registers protected with special hardware software. Therefore, page protected FL1BPR vector locations erased either page mass erase operation, both FL1BPR FL2BPR registers also erased.
security feature absolutely secure. However, Motorola's strategy make reading copying FLASH difficult unauthorized users.
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Application Note FLASH Control Block Protect Registers
FLASH Control Block Protect Registers
Each FLASH array registers that control operation, FLASH control register (FLxCR) FLASH block protect register (FLxBPR). Figure Figure
Read: HVEN MASS ERASE
Freescale Semiconductor, Inc.
Write: Reset:
Unimplemented
Figure FLASH Control Register (FLxCR) FLASH control registers, FL1CR FL2CR, FLASH-1 FLASH-2 arrays, respectively. $FF88 FLASH-1 control register (FL1CR) $FE08 FLASH-2 control register (FL2CR)
HVEN High-Voltage Enable This read/write enables charge pump drive high voltages program erase operations array. HVEN only either ERASE proper sequence program erase followed. High voltage enabled array charge pump High voltage disabled array charge pump MASS Mass Erase Control This read/write configures memory mass page erase operations. Mass erase operation selected Page erase operation selected
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Freescale Semiconductor, Inc. Application Note
ERASE Erase Control This read/write configures memory erase operation. ERASE interlocked with such that both bits cannot same time. Erase operation selected Erase operation unselected Program Control
Freescale Semiconductor, Inc.
This read/write configures memory program operation. interlocked with ERASE such that both bits cannot same time. Program operation selected Program operation unselected
Read: BPR7 Write: BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure FLASH Block Protect Register (FLxBPR) FLASH block protect registers, FL1BPR FL2BPR, FLASH-1 FLASH-2 arrays, respectively. $FF80 FLASH-1 block protect register (FL1BPR) $FF81 FLASH-2 block protect register (FL2BPR)
BPR[7:0] Block Protect Register These eight bits specify most significant bits 32-K FLASH memory location. Memory protected against program erase operations starting from this address FLASH array.
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Application Note FLASH Control Block Protect Registers
protected range
FLxBPR Value FLASH-1 protection $FF00-$FFFF $FE80-$FFFF FLASH-2 protection $7F00-$7FFF $7E80-$7FFF
Freescale Semiconductor, Inc.
$8580-$FFFF $8500-$FFFF $8480-$FFFF $8400-$FFFF
$0580-$7FFF $0500-$7FFF $0480-$7FFF $0450-$7FFF
$8200-$FFFF $8180-$FFFF $8100-$FFFF $8080-$FFFF $8000-$FFFF
$0450-$7FFF $0450-$7FFF $0450-$7FFF $0450-$7FFF $0450-$7FFF
Decreasing value FLxBPR increases protected range page (128 bytes). However, programming block protect register with protects range twice that size, bytes, corresponding array. means that locations $FF00-$FFFF $7F00-$7FFF protected FLASH-1 FLASH-2, respectively. FLASH memory does exist some locations. block protection range unaffected FLASH memory does exist that range. Refer memory make sure that desired locations protected.
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Freescale Semiconductor, Inc. Application Note FLASH Erase Operations
MC68HC908AS60A/AZ60A, FLASH arrays erased page (128 bytes) time entire array erased with routine (mass erase.) pages from addresses $xx00 $xx7F from $xx80 $xxFF. Figure shows mass erase page erase flowcharts.
Freescale Semiconductor, Inc.
FLASH Mass Erase Algorithm
NOTE:
Each FLASH array separate FLASH control block protect registers. Make sure bits appropriate register. ERASE MASS FLASH control register (FLxCR). ERASE configures FLASH memory erase operation. MASS sets MASS erase operation. Read FLASH block protect register (FLxBPR). block protect register must read before high voltage enabled. desired address step protected block, erase will fail. Write FLASH address within address range erased. mass erase, this address that FLASH array. address used determine which array will erased. Wait time, tNVS. Internal high voltage charged. HVEN bit. Internal high voltage applied array. Wait time, tMERASE. tMERASE mass erase time. Clear ERASE bit. erase operation disabled.
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Application Note FLASH Page Erase Algorithm
Wait time, tNVHL. This time required internal high voltage discharge from array. Clear HVEN bit. Disable internal high voltage. Wait time, tRCV. After time, tRCV, memory accessed normal read mode.
Freescale Semiconductor, Inc.
FLASH Page Erase Algorithm
NOTE:
Each FLASH array separate FLASH control block protect registers. Make sure bits appropriate register. ERASE clear MASS FLASH control register (FLxCR). ERASE configures FLASH memory erase operation. MASS sets PAGE erase operation. Read FLASH block protect register (FLxBPR). block protect register must read before high voltage enabled. desired address step protected block, erase will fail. Write FLASH address within address range erased. page erase, this address within that 128-byte block. address used determine address range that will erased. Wait time, tNVS. Internal high voltage charged. HVEN bit. Internal high voltage applied page.
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Freescale Semiconductor, Inc. Application Note
Wait time, tERASE. tERASE page erase time. Clear ERASE bit. erase operation disabled. Wait time, tNVH. This time required internal high voltage discharge from page.
Freescale Semiconductor, Inc.
Clear HVEN bit. Internal high voltage disabled. Wait time, tRCV. After time, tRCV, memory accessed normal read mode.
NOTE:
Programming erasing FLASH locations cannot performed code being executed from same FLASH array. However, code executed FLASH array when programming/erasing locations other array.
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Application Note FLASH Page Erase Algorithm
PAGE ERASE
MASS ERASE
STEP ERASE CLEAR MASS STEP READ BLOCK PROTECT REGISTER
STEP ERASE MASS STEP READ BLOCK PROTECT REGISTER STEP WRITE FLASH ADDRESS PAGE WRITE FLASH ADDRESS ARRAY STEP WAIT TIME tNVS WAIT TIME tNVS STEP HVEN HVEN
Freescale Semiconductor, Inc.
STEP
STEP
STEP
STEP WAIT TIME tERASE STEP CLEAR ERASE
STEP WAIT TIME tMERASE STEP CLEAR ERASE
STEP WAIT TIME tNVH STEP CLEAR HVEN
STEP WAIT TIME tNVHL STEP CLEAR HVEN
STEP WAIT TIME tRCV
STEP WAIT TIME tRCV
ERASE OPERATION COMPLETE
ERASE OPERATION COMPLETE
Note: erase multiple pages, repeat steps 1-10.
Figure FLASH Erase Operation Flowcharts
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Freescale Semiconductor, Inc. Application Note FLASH Program Operation
MC68HC908AS60A/AZ60A, programming FLASH memory done row-by-row basis. consists bytes, with address ranges follows: $xx00 $xx3F $xx40 $xx7F $xx80 $xxBF $xxC0 $xxFF
Freescale Semiconductor, Inc.
During programming cycle, make sure that addresses being written within ranges specified. Attempts program addresses different ranges programming cycle will fail. example, programming from addresses $xx30 $xx6F will successful because addresses $xx30-$xx3F $xx40-$xx6F different rows. Also take care that initial address written makes logical sense. programming algorithm includes step (step that follows) where programmed identified writing address that with data. most rows, this address chosen haphazardly since consists bytes. However, there areas where entire does consist FLASH space. these rows, when programming array, ensure that non-FLASH location used specifier written during sequence. First FLASH-2 ($0450-$047F) bytes Vector area MC68HC908AS60A ($FFD2-$FFD3 $FFDA-$FFFF) bytes Vector area MC68HC908AZ60A ($FFCC-$FFFF) bytes
NOTE:
avoid program disturbs, must erased before byte that programmed. programming flowchart shown Figure
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Application Note FLASH Program Operation
FLASH control register (FLxCR). configures FLASH memory program operation. Read FLASH block protect register. block protect register must read before high voltage enabled. desired address step protected block, programming will fail. Write FLASH address within address range desired with data.
Freescale Semiconductor, Inc.
Wait time, tNVS. Internal high voltage charged. HVEN bit. Internal high voltage applied programming row. Wait time, tPGS. Write data byte FLASH address programmed. Wait time, tPROG. tPROG 1-byte programming time. tPROG actually includes total time from step flowchart) back step flowchart) additional byte programming, from step step flowchart) last byte. This total time must between both cases. Refer Figure Repeat steps until bytes within programmed. Clear bit. Disable programming operation. Wait time, tNVH. Internal high voltage discharged from row. Clear HVEN bit. Internal high voltage disabled. Wait time, tRCV. After time, tRCV, memory accessed normal read mode.
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Freescale Semiconductor, Inc. Application Note
NOTE:
Programming erasing FLASH locations cannot performed code being executed from same FLASH array. However, code executed FLASH array program/erase locations other array. While these operations must performed order shown, other unrelated operations occur between steps. exceed tPROG maximum maximum. tPROG defined step defined cumulative time that high voltage applied same before erase. tNVS tNVH tPROG
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Application Note FLASH Program Operation
Note: This page program routine assumes that being programmed initially erased.
FLASH PROGRAMMING
STEP STEP READ BLOCK PROTECT REGISTER STEP
Freescale Semiconductor, Inc.
WRITE FLASH ADDRESS STEP WAIT TIME tNVS STEP HVEN STEP WAIT TIME tPGS STEP
WRITE DATA BYTE FLASH LOCATION STEP WAIT TIME tPROG Note: tPROG total time from from This time must between
STEP
COMPLETED PROGRAMMING THIS ROW?
STEP
CLEAR
STEP WAIT TIME tNVH STEP CLEAR HVEN STEP WAIT TIME tRCV
PROGRAM OPERATION COMPLETE
Figure FLASH Programming Algorithm Flowchart
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Freescale Semiconductor, Inc. Application Note EEPROM Functional Description
EEPROM memory MC68HC908AS60A/AZ60A physically consists independent 512-byte arrays each with bytes block protection four bytes timebase dividers. erased reads logic programmed reads logic Program erase operations facilitated through control bits memory mapped registers. Details these operations appear later this application note. Memory EEPROM array programmed only byte bits) time. However, entire array (512 bytes), block (128 bytes), single byte erased time. EEPROM memory MC68HC908AS60A/AZ60A, which includes registers related EEPROM operation, consists $0600-$07FF, EEPROM-2 array, bytes $0800-$09FF, EEPROM-1 array, bytes $FE09, configuration write-once register, CONFIG-2 $FE10, EEPROM-1 nonvolatile register, EE1DIVHNVR $FE11, EEPROM-1 nonvolatile register, EE1DIVLNVR $FE1A, EEPROM-1 divider high register, EE1DIVH $FE1B, EEPROM-1 divider register, EE1DIVL $FE1C, EEPROM-1 nonvolatile register, EE1NVR $FE1D, EEPROM-1 control register, EE1CR $FE1F, EEPROM-1 array configuration register, EE1ACR $FF70, EEPROM-2 nonvolatile register, EE2DIVHNVR $FF71, EEPROM-2 nonvolatile register, EE2DIVLNVR $FF7A, EEPROM-2 divider high register, EE2DIVH $FF7B, EEPROM-2 divider register, EE2DIVL $FF7C, EEPROM-2 nonvolatile register, EE2NVR $FF7D, EEPROM-2 control register, EE2CR $FF7F, EEPROM-2 array configuration register, EE2ACR
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Application Note Configuration Register EEPROM Timebase Divider Control Registers
Configuration Register EEPROM Timebase Divider Control Registers
Five registers related EEPROM timebase divider, which discussed EEPROM Timebase Divider Initialization.
Read: Write: EEDIV MSCAND AT60A AZxx
Freescale Semiconductor, Inc.
Reset:
Unimplemented
Figure Configuration Register (CONFIG-2) There byte configuration write-once register, CONFIG-2. $FE09, CONFIG-2
EEDIVCLK CONFIG-2 register must configured EEPROM erased programmed properly. EEDIVCLK EEPROM Timebase Divider Clock Select This selects reference clock source EEPROM-1 EEPROM-2 timebase divider modules. EExDIV clock input driven internal clock. EExDIV clock input driven CGMXCLK.
NOTE:
Once register written, further writes will have effect until reset occurs AZxx will change except power-on reset. EEPROM requires 35-µs timebase. next four registers EEPROM timebase divider provide this constant clock. EEPROM Timebase Divider Initialization.
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Freescale Semiconductor, Inc. Application Note
Read: Write: Reset: EEDIV SECD
EEDIV
EEDIV9
EEDIV8
Unimplemented Programmed value when blank
Figure EExDIV Nonvolatile High Register (EExDIVHNVR)
EEDIV6 EEDIV5 EEDIV4 Programmed value when blank EEDIV3 EEDIV2 EEDIV1 EEDIV0
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Read: EEDIV7 Write: Reset:
Figure EExDIV Nonvolatile Register (EExDIVLNVR)
Read: Write: Reset: Unimplemented EEDIV SECD EEDIV EEDIV9 EEDIV8
Contents EExDIVHNVR
Figure EExDIV Divider High Register (EExDIVH)
Read: EEDIV7 Write: Reset: Contents EExDIVLNVR EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
Figure EExDIV Divider Register (EExDIVL) There sets registers proper constant timebase EEPROM-1 EEPROM-2 arrays. They are: $FE10, EEPROM-1 nonvolatile register, EE1DIVHNVR $FE11, EEPROM-1 nonvolatile register, EE1DIVLNVR $FE1A, EEPROM-1 divider high register, EE1DIVH
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Application Note Configuration Register EEPROM Timebase Divider Control Registers
$FE1B, EEPROM-1 divider register, EE1DIVL $FF70, EEPROM-2 nonvolatile register, EE2DIVHNVR $FF71, EEPROM-2 nonvolatile register, EE2DIVLNVR $FF7A, EEPROM-2 divider high register, EE2DIVH $FF7B, EEPROM-2 divider register, EE2DIVL
NOTE:
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EExDIVHNVR EExDIVLNVR registers consist nonvolatile memory. Therefore, programming erasing these locations requires normal EEPROM program/erase sequences, which described later sections. other hand, EExDIVH EExDIVL consist nonvolatile memory. Whenever reset occurs, values EExDIVHNVR EExDIVLNVR automatically loaded into EExDIVH EExDIVL, respectively. These registers also writable software. EEDIVSECD EEPROM Divider Security Disable This enables/disables security feature EExDIV registers. When EExDIV security feature enabled (EEDIVSECD programmed logic EExDIVHNVR), registers EExDIVH, EExDIVL, EExDIVHNVR, EExDIVHNVR locked permanently. EExDIV security feature disabled EExDIV security feature enabled
NOTE:
This security feature enabled when EEDIVSECD EExDIVHNVR programmed then system reset. EEDIV10-EEDIV0 EEPROM Timebase Prescaler Bits These prescaler bits store value EExDIV which used divisor derive timebase from selected reference clock source (CGMXCLK clock) EEPROM related internal timer circuits. EEDIV10-EEDIV0 readable time.
NOTE:
EExDIVH EExDIVL registers writable anytime that EELAT cleared EEDIVSECD set. However, modified values held only until next reset. EExDIV value calculated using this formula: EExDIV [Reference Frequency (Hz) 10-6)
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Freescale Semiconductor, Inc. Application Note EEPROM Control Configuration Registers
Each EEPROM array three registers that control operation: EEPROM control register (EExCR) EEPROM nonvolatile register (EExNVR) EEPROM array configuration register (EExACR)
EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM
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Read: Write: Reset:
USED
Unimplemented
Figure EEPROM Control Register (EExCR) There EEPROM control registers, EE1CR EE2CR, EEPROM-1 EEPROM-2 arrays, respectively. $FE1D EEPROM-1 control register (EE1CR) $FF7D EEPROM-2 control register (EE2CR)
Unused EEOFF EEPROM Power-Down This read/write disables EEPROM module lower power consumption. attempts access array will give unpredictable results. Reset clears this bit. Disable EEPROM array Enable EEPROM array EERAS1 EERAS0 Erase Bits These read/write bits erase modes. Reset clears these bits.
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Application Note EEPROM Control Configuration Registers
Table EEPROM Program/Erase Mode Select
EEBPx EERAS1 EERAS0 MODE Byte program Byte erase Block erase Bulk erase erase/program
Freescale Semiconductor, Inc.
don't care
EELAT EEPROM Latch Control This read/write latches address data buses programming EEPROM array. EELAT cannot cleared EEPGM still set. Reset clears this bit. Buses configured EEPROM programming/erasing Buses configured normal read operation AUTO Indication Automatic Termination Program/Erase Cycle When AUTO set, EEPGM cleared automatically after program/erase cycle terminated internal timer. Automatic clear EEPGM enabled. Automatic clear EEPGM disabled. EEPGM EEPROM Program/Erase Enable This read/write enables internal charge pump. EELAT write valid EEPROM location occurred, then programming/erasing voltage applied EEPROM array. Reset clears EEPGM bit. EEPROM programming/erasing power switched EEPROM programming/erasing power switched
NOTE:
Writing logic both EELAT EEPGM bits with single instruction will only clear EEPGM allow time high voltage dissipate.
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Freescale Semiconductor, Inc. Application Note
Read: Write: Reset: USED
USED
USED
PRTCT
EEBP3
EEBP2
EEBP1
EEBP0
Programmed value when blank
Figure EEPROM Nonvolatile Register (EExNVR)
NOTE:
Freescale Semiconductor, Inc.
EExNVR registers factory programmed that full array available unprotected.
Read: Write: Reset: Unimplemented Contents EExNVR USED USED USED PRTCT EEBP3 EEBP2 EEBP1 EEBP0
Figure EEPROM Array Configuration Register (EExACR) registers Figure Figure determine memory protection block. There sets registers both EEPROM-1 EEPROM-2 arrays. They are: $FE1C, EEPROM-1 nonvolatile register, EE1NVR $FE1F, EEPROM-1 array configuration-volatile register, EE1ACR $FF7C, EEPROM-2 nonvolatile register, EE2NVR $FF7F, EEPROM-2 array configuration-volatile register, EE2ACR
NOTE:
EExNVR registers nonvolatile memory locations. Therefore, programming erasing registers requires normal EEPROM program/erase sequences, which described later sections. other hand, EExACR registers nonvolatile memory. reset, values EExNVRs automatically loaded into EExACRs. Thereafter, reads EExNVRs will result EExACRs being reloaded.
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Application Note EEPROM Control Configuration Registers
Bits Unused Bits EEPRTCT EEPROM Program/Erase Protection This one-time programmable used protect bytes (EEPROM-1: $8F0-$8FF EEPROM-2: $6F0-$6FF) from being erased programmed. EEPROM program/erase protection disabled EEPROM program/erase protection enabled
Freescale Semiconductor, Inc.
NOTE:
This feature write-once feature. Once protection enabled, cannot disabled. EEBP3-EEBP0 EEPROM Block Protection Bits These read/write bits select blocks EEPROM array from being programmed erased. Reset loads EEBP[3:0] from EExNVR EExACR. EEPROM array block protected. EEPROM array block unprotected.
EEPROM-1 EEBP0 EEBP1 EEBP2 EEBP3 $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF
EEPROM-2 $0600-$067F $0680-$06FF $0700-$077F $0780-$07FF
NOTE:
configuration EExNVRs changed programming erasing. configuration will take effect with reset read EExNVR.
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Freescale Semiconductor, Inc. Application Note EEPROM Timebase Divider Initialization
EEPROM actually FLASH cell surrounded logic state machine. state machine requires constant timebase with period apply high voltage with right timing during erase program operations. constant timebase properly, memory cells over-programmed permanently damaged. Motorola cannot guarantee EEPROM program erase operations this case. generate this constant timebase, clock divider value (EExDIV value) EEPROM timebase divider registers (EExDIVH EExDIVL). Follow these steps initialize timebase divider value: reference clock source selected. EEDIVCLK CONFIG-2 register determines clock source. (Refer Configuration Register EEPROM Timebase Divider Control Registers). options clock source are: CGMXCLK (output crystal oscillator circuit) System clock
Freescale Semiconductor, Inc.
NOTE:
recommended frequency range reference clock MHz. EExDIV calculated derive EExDIV value that matches user's application. formula: EExDIV [Reference Frequency(Hz) x10-6) +0.5] Example When reference clock 4.9152 MHz, EExDIV value (hex $AC). Example When reference clock MHz, EExDIV value (hex $118).
NOTE:
Make sure that EExDIV calculated with reference clock source being used.
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Application Note EEPROM Block Protection Security
calculated EExDIV value must EExDIVH EExDIVL using methods: Program EExDIV value EExDIVHNVR EExDIVLNVR then reset microcontroller. this method, programmed value loaded EExDIVH EExDIVL reset. Write calculated EExDIV value EExDIVH EExDIVL. this method, written value held registers until next reset occurs.
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EEPROM Block Protection Security
MC68HC908AS60A/AZ60A special program/erase protection feature which prevents program/erase access certain memory locations. This called block protection controlled EEBPx bits EExNVR registers. There also special security feature this EEPROM which designates bytes that permanently secured. These addresses $06F0-$06FF $08F0-$08FF. Once EEPRTCT cleared first time, values these bytes stored permanently. They read, programmed erased. When EEPRTCT programmed Programming erasing secured locations (EEPROM-2: $06F0-$06FF EEPROM-1: $08F0-$08FF) disabled permanently. protected locations read normal. Programming erasing EExNVR disabled permanently. unprotected locations (EEPROM-2: $0600-$06EF, $0700-$07FF EEPROM-1: $0800-$09EF, $0900-$09FF), bulk block erase modes disabled. Single byte erase program modes available. However, locations partially entirely protected EEPBx bits, protected block cannot erased programmed.
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Freescale Semiconductor, Inc. Application Note
Table EEPROM Protection Security Features
Address Range Covered (EEPROM-1 EEPROM-2) $0800-$087F $0600-$067F EEBP0 EEBP0 $0880-$08EF $0680-$06EF EEBP1 EEBP1 $08F0-$08FF $06F0-$06FF EEBP1 EEBP1 $0900-$097F $0700-$077F EEBP2 EEBP2 $0980-$09FF $0780-$07FF EEBP3 EEBP3 EEPRTCT EEPRTCT
Byte programming available Bulk, block, byte erasing available Protected Byte programming available Bulk, block, byte erasing available Protected Byte programming available Bulk, block, byte erasing available Protected Byte programming available Bulk, block, byte erasing available Protected Byte programming available Bulk, block, byte erasing available Protected
Byte programming available Only byte erasing available Protected Byte programming available Only byte erasing available Protected Secure erasing programming) Byte programming available Only byte erasing available Protected Byte programming available Only byte erasing available Protected
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Standard EEPROM Erase Operation
EEPROM erased byte, block (128 bytes), bulk array (512 bytes) basis. block protection register shows desired erase region protected, erasing will fail. Therefore, first ensure that block protection feature disabled relevant addresses. This EEPROM erase operation compatible with MC68HC908AS60/AZ60 EEPROM erase operation. flowchart standard EEPROM erase operation included Figure Clear/set EERAS1 EERAS0 select byte/block/bulk erase, EELAT EExCR.
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Application Note AUTO Mode EEPROM Erase Operation
Write data EEPROM location. byte erase, this should address erase. block bulk erase, this address within block array erase. EEPGM bit. Wait time, tEEBYTE/tEEBLOCK/tEEBULK, erase byte/block/whole array. Clear EEPGM bit. Wait time, tEEFPV, erasing voltage fall.
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Clear EELAT bit. Repeat steps more EEPROM byte/block/bulk erasing.
AUTO Mode EEPROM Erase Operation
EEPROM erased byte, block (128 bytes), bulk array (512 bytes) basis. block protection register shows desired erase region protected, erasing will fail. Therefore, first ensure that block protection feature disabled relevant addresses. this EEPROM memory, another erase operation mode provided. called AUTO mode. When AUTO mode selected, erase cycle terminated internal timer, which polls EEPGM EExCR register. Therefore, fixed delay times required AUTO mode. flowchart AUTO mode EEPROM erase operation included Figure Clear/set EERAS1 EERAS0 select byte/block/bulk erase, EELAT AUTO EExCR. Write data EEPROM location. byte erase, this should address erase. block bulk erase, this address within block array erase. EEPGM bit. Poll EEPGM until cleared internal timer. Clear EELAT bit. Repeat steps more EEPROM byte/block/bulk erasing.
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Freescale Semiconductor, Inc. Application Note
STANDARD ERASE
AUTO ERASE
STEP EERAS1 EERAS0 ERASE SIZE EELAT STEP WRITE DATA EEPROM ADDRESS WITHIN RANGE ERASED STEP EEPGM STEP WAIT TIME tEEBYTE/tEEBLOCK/tEEBULK STEP CLEAR EEPGM STEP WAIT TIME tEEFPV STEP CLEAR EELAT
STEP EERAS1 EERAS0 ERASE SIZE EELAT AUTO BITS STEP WRITE DATA EEPROM ADDRESS WITHIN RANGE ERASED STEP EEPGM
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STEP EEPGM CLEARED? STEP CLEAR EELAT
ERASE OPERATION COMPLETE
ERASE OPERATION COMPLETE
Figure EEPROM Erasing Algorithm Flowcharts
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Application Note Standard EEPROM Program Operation
Standard EEPROM Program Operation
Follow next procedure program byte EEPROM. Ensure that block protection feature disabled byte programmed. This EEPROM program operation compatible with MC68HC908AS60/AZ60 EEPROM program operation. flowchart this programming algorithm shown Figure
Freescale Semiconductor, Inc.
NOTE:
byte must erased before programming. Clear EERAS1 EERAS0 EELAT EExCR. Write desired data byte desired EEPROM address. EEPGM bit. Wait time, tEEPGM, program byte. Clear EEPGM bit. Wait time, tEEFPV, programming voltage fall. Clear EELAT bit. Repeat steps program additional bytes EEPROM arrays.
AUTO Mode EEPROM Program Operation
Follow next procedure program byte EEPROM using AUTO feature. Ensure that block protection feature disabled byte programmed. this EEPROM memory, another program operation provided. called AUTO mode. When AUTO mode selected, program cycle terminated internal timer, which polls EEPGM EExCR register. Therefore, fixed delays required with AUTO mode operation. flowchart this programming algorithm shown Figure
NOTE:
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Freescale Semiconductor, Inc. Application Note
Clear EERAS1 EERAS0 EELAT AUTO EExCR. Write desired data byte desired EEPROM address. EEPGM bit. Poll EEPGM until cleared internal timer. Clear EELAT bits. Repeat steps program additional bytes EEPROM array.
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STANDARD PROGRAM
AUTO PROGRAM
STEP CLEAR EERAS1 EERAS0 EELAT STEP WRITE DATA BYTE EEPROM ADDRESS STEP EEPGM STEP WAIT TIME tEEPGM STEP CLEAR EEPGM
STEP CLEAR EERAS1 EERAS0 EELAT AUTO STEP WRITE DATA BYTE EEPROM ADDRESS STEP EEPGM
STEP EEPGM CLEARED? STEP CLEAR EELAT
STEP WAIT TIME tEEFPV STEP CLEAR EELAT
PROGRAM OPERATION COMPLETE
PROGRAM OPERATION COMPLETE
Figure EEPROM Programming Algorithm Flowcharts
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Application Note Selective Programming
Selective Programming
each programming cycle, eight bits EEPROM memory programmed. possible program multiple bits same time. However, same programmed twice unless entire byte been erased first. This means that same byte location programmed eight times long individual written more than once. This referred selective programming. acceptable sequence Table shows same byte used eight program cycles without erase. Table Selective Programming
Acceptable Sequence Operation Erase Write Write Write Write Write Write Write Write Erase Program Data 1111:1110 1111:1101 1111:1011 1111:0111 1110:1111 1101:1111 1011:1111 0111:1111 Value Memory 1111:1111 1111:1110 1111:1100 1111:1000 1111:0000 1110:0000 1100:0000 1000:0000 0000:0000 1111:1111 Unacceptable Sequence Operation Erase Write Write Write Write Program Data 1111:1110 1111:1001 1110:1111 1101:1000 Value Memory 1111:1111 1111:1110 1111:1000 1110:1000 Unknown
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EEPROM memory lifetime guaranteed 10-K read/write cycles. However, using selective programming extends life cycle memory 8-fold since each only programmed 10-K times. This allows user program single byte 80-K times. programmed more than once before byte erased, Motorola cannot guarantee proper operation EEPROM array.
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Freescale Semiconductor, Inc. Application Note Practical Considerations Programming/Erasing
ensure successful programming erasing FLASH and/or EEPROM MC68HC908AS60A/AZ60A, user should consider following suggestions: Provide good ground. Provide clean constant clock during program erase operations. Filter signals leaving noisy environment. microcontroller programmed erased socket, ensure that pins making good electrical contact. Provide electrically noise-free environment MCU. supply should filtered within specification limits. Decoupling capacitors should placed very close VDD/VSS pairs. high current switching activity general vicinity should disabled during programming.
Freescale Semiconductor, Inc.
Evaluating Delay Times Sample Code
FLASH EEPROM algorithms include specific wait steps. These delay times defined MC68HC908AS60A/AZ60A specification must considered when utilizing algorithms. ensure that each wait step meets specification, delay times have evaluated. delays sample code provided this application note were evaluated confirmed meet specification using general port pin. port initialized with high output signal. Just before entering delay, port toggled held until delay. actual delay times shown Table Table Table were periods measured oscilloscope. toggle port pin, instructions BSET, BCLR, were used. sample code also includes instructions used delay time evaluation.
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Application Note Evaluating Delay Times Sample Code
Table FLASH Erase Delay Times
Name Delay tNVS tERASE tNVH Specified Duration Calculated Delay Time(1) 10.6 1.01 4.01 Actual Delay Time 12.24 E1)(3) 1.012 7.32 4.02 102.8 3.66 Delta(2) 1.64 1.62 1.66
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tMERASE tNVHL tRCV
Delay time calculated dividing number cycles delay speed 2.4576 MHz. Most delta times around Since instructions BSET require four internal cycles, this additional time comes from execution time instruction. cycles 1.627 2.4576 These times refer measured delays based running attached sample code. that code, points which measurements were taken defined these markers.
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Freescale Semiconductor, Inc. Application Note
Table FLASH Program Delay Times
Name Delay tNVS tPGS Specified Duration Calculated Delay Time(1) 10.6 30.5 µs(4) Actual Delay Time 12.24 E7)(3) 7.34 32.2 32.9 (S10 E10_1) 32.8 (S10 E10_2) 7.32 (S11 E11) (S12 E12) Delta(2) 1.64 1.64
Freescale Semiconductor, Inc.
tPROG
µs-40
31.3 µs(5)
31.3 µs(6)
1.62 1.60
tNVH tRCV
Delay time calculated dividing number cycles delay speed 2.4576 MHz. Most delta times around Since instructions BSET have require four internal cycles, this additional time comes from execution time instruction. cycles 1.627 2.4576 These times refer measured delays based running attached sample code. that code, points which measurements were taken defined these markers. byte programmed last byte being programmed. FLASH array-1, byte programmed last byte being programmed. FLASH array-2, byte programmed last byte being programmed.
Table EEPROM Standard Sequence Delay Times
Name Delay tEEBYTE tEEBLOCK tEEBULK tEEPGM tEEFPV Specified Duration Calculated Delay Time(1) Actual Delay Time 10.4 102.8 Delta
10.01
0.39
Delay time calculated dividing number cycles delay speed 2.4576 MHz.
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Application Note FLASH Frequently Asked Questions
FLASH Frequently Asked Questions
These questions answers designed help user with frequent concerns.
Question
cannot program/erase FLASH memory all. What should consider make program/erase code work? Check following: each step programming algorithm erasing algorithm) performed right order? sequence program erase operations interlocked hardware only prescribed order these operations will allow erase/program operations. However, other non-FLASH operations occur between steps shown. memory block where want program/erase unprotected? block protect feature FLASH present prevent unintentional programming erasing. block protect bits must cleared such that memory erased programmed unprotected. only override block protection apply voltage during erase program algorithms. (Refer FLASH Erase Operations.) delay times such tPROG, tERASE, tMERASE, tNVS, etc., within specification? Timing critical ensure proper FLASH operation. Delay times that long short alter FLASH performance point where does work reliable. Motorola does guarantee FLASH performance timing requirements being adhered correct FLASH register being written enable erase program? MC68HC908AS60A/AZ60A FLASH arrays with separate sets control block protect registers. Make sure appropriate register being addressed. Refer FLASH Block Protection.
Answer
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Freescale Semiconductor, Inc. Application Note
enabled? enabled, address $FFFF written periodically (with value) prevent reset. However, this feeding process during program/erase operation cause unintentional FLASH programming erasing because address $FFFF exists FLASH. avoid issues, make sure that selected period long enough that feeding process performed during program/erase operation disable entirely during this operation.
Freescale Semiconductor, Inc.
NOTE:
always enabled RESET disabled modifying "write-once" CONFIG-1 register. Refer FLASH Program Operation. Motorola's recommended programming algorithm erasing algorithm) used your code? recommended programming algorithm ensures that FLASH programmed sufficient data retention with minimum program time. following this algorithm lead overprogramming, which risks program disturb.
Question
wanted erase only vector locations using page erase operation, block protection registers were also erased. anything wrong? block protect registers vector locations same page. MC68HC908AS60A/AZ60A, programming erasing block protect registers protected. MC68HC908AS60/AZ60, this operation required high voltage pin). Therefore, block protect registers also erased when vector locations erased. other FLASH locations must protected, have reprogram block protect register after vector erasing completed.
Answer
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Application Note FLASH Frequently Asked Questions
Question Answer
What FLASH charge pump? charge pump dynamic (clocked) circuit which generates high voltages internally FLASH program erase nonvolatile memory. Users have access these voltages.
Question
MC68HC908AS60A/AZ60A FLASH programs bytes) time. always have program entire row? necessary program entire row. Addresses which programmed left they were before programming started. However, before reprogramming additional bytes this row, entire page must erased.
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Answer
Question
During program/erase process, execute interrupt service include additional steps? Unrelated (non-FLASH) steps included between steps program/erase algorithms long sequence steps remains consistent. However, interrupt service routines cause errors program erase timing lead corrupt missing data FLASH. Motorola does recommend interrupts during program erase operations.
Answer
NOTE:
Make certain enter stop wait mode during program erase operation. High voltage exposed cells extended period cause permanent damage.
Question
executing program/erase code memory arrays. same array programmed/erased?
Answer
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Freescale Semiconductor, Inc. Application Note
Question While running program/erase code memory arrays, other memory array programmed/erased? Yes. MC68HC908AS60A/AZ60A FLASH memory arrays. array used executing code while programming/erasing other.
Answer
Question
program/erase both FLASH arrays same time? Each array does have separate charge pump address decode logic does allow more than programmed time.
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Answer
Question
When writing bytes data FLASH memory programming, does order written data matter? long bytes written within row, data latched programming operation.
Answer
Question
Does programming erasing FLASH block protect registers (FLxBPRs) require pin? FLxBPRs programed erased without pin. Refer FLASH Block Protection.
Answer
Question
want perform both page mass erase operations using minimum mass erase time (tMERASE) minimum mass high voltage hold time (tNVHL) since these delays cover page delays (tERASE tNVH). Does page operation cause problems using mass delays? there erase disturb. However, reduce endurance FLASH memory. Motorola recommends using minimum time allowed both page mass erase operations.
Answer
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Application Note FLASH Frequently Asked Questions
Question
sending external data into MC68HC908AS60A/AZ60A programming. speed this programming process? Excluding data download time, takes about seconds program Kbytes FLASH. data transferred higher communication baud rate parallel manner, overall programming time reduced. ideal situation would fast parallel transfer data during delay times associated with programming algorithm. program FLASH with 2-MHz frequency, read FLASH with 8-MHz frequency without problems? Yes. FLASH will meet specifications, including data retention performance, FLASH programmed/erased used within specification limits. program/erase operation successful monitor mode. FLASH memory protected monitor mode make difficult unauthorized users view memory contents. Before programming/erasing FLASH, security feature part must "broken" view FLASH contents. When attempt break security fails, FLASH addressed during reads invalid data will observed. Refer monitor section, which describes break security, MC68HC908AZ60A MC68HC908AS60A Technical Data, Motorola document order number MC68HC908AZ60A/D. have failed break security monitor mode. execute mass erase erase security? Yes. Mass erase only FLASH operation allowed after failing break security monitor mode. When mass erase operation executed, address specified step sequence (refer FLASH Mass Erase Algorithm) must address FLASH block protect register. Make sure block protect feature asserted override mass erase device.
Answer
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Question
Answer
Question Answer
Question
Answer
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Freescale Semiconductor, Inc. Application Note
Question monitor mode, tell break security been successful? security check unsuccessful, memory reads will return same data every byte read instead code data expected.
Answer
Question
need confirm memory contents after programming FLASH? recommended that code used program FLASH also include verification step ensure integrity data programmed into FLASH.
Freescale Semiconductor, Inc.
Answer
Question
block memory FLASH array protected programming block protect register. When execute mass erase operation without applying high voltage pin, unprotected block erased? When FLASH array partially protected, mass erase cannot performed unless high voltage placed IRQ.
Answer
NOTE:
When high voltage placed pin, block protection register ignored entire memory array will erased mass erase operation executed.
Question Answer
What expected lifetime FLASH memory? minimum program/erase endurance data retention lifetime FLASH memory conditions found MC68HC908AZ60A MC68HC908AS60A Technical Data book, Motorola document order number MC68HC908AZ60A/D.
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Application Note FLASH Frequently Asked Questions
Question Answer
What steps take prolong life FLASH memory? FLASH memory finite program/erase durability finite data retention lifetime. However, specification shows minimum lifetime considering worst case conditions applied part. general, FLASH will last longer used moderate temperatures (0-70oC) program/erase cycles kept minimum.
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Question
program/erase FLASH maximum temperature limits continuously specified lifetime part? Yes. program erase cycle durability specified 10-K maximum each. However, exceeding that value recommended. FLASH read continuously over life device.
Answer
Question Answer
What modes operation cause most noise? Program erase modes cause significant amount (electromagnetic interference) power supply noise high transient current demand charge pump. High accuracy (analog-to-digital) conversions possible while FLASH programming erasing.
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Freescale Semiconductor, Inc. Application Note EEPROM Frequently Asked Questions
These questions answers designed help user with frequent concerns. Question cannot program/erase EEPROM memory all. What should consider make program/erase code work? Check following: program correct divider values both EExDIV nonvolatile high register (EExDIVHNVR) EExDIV nonvolatile register (EExDIVLNVR)? program them, write correct divider values both EExDIV divider high register (EExDIVH) EExDIV divider register (EExDIVL) before executing erase program algorithm operation? program erase EEPROM, EEPROM control requires constant timebase drive internal timer. proper divider values initialized divider registers, EEPROM erase and/or program operation performed properly. correct divider value calculated formula Configuration Register EEPROM Timebase Divider Control Registers. There ways correct divider values. them program divider value EExDIVHNVR EExDIVLNVR registers. other write value EExDIVH EExDIVL registers temporarily before programming and/or erasing operations. select correct EEPROM reference clock source? EEPROM reference clock source either CGMXCLK system clock. selection this reference clock source defined EEDIVCLK configuration register (CONFIG-2). divider value will changed depending which reference clock source select. Make sure divider value calculated using correct reference clock speed.
Answer
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NOTE:
CONFIG-2 "write-once" register EEDIVCLK CGMXCLK reset.)
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Application Note EEPROM Frequently Asked Questions
recommended programming erasing algorithms your code? EEPROM consists FLASH memory surrounded logic state machine. Motorola's recommended programming algorithm ensures that EEPROM programmed sufficient data retention minimum program time. Motorola does guarantee performance EEPROM recommended algorithms followed. each step programming erasing algorithms performed right order? sequence program erase operations interlocked hardware only prescribed order these operations occur. However, other non-EEPROM operations occur between steps shown. memory block where want program/erase unprotected? block protect feature EEPROM present prevent unintentional programming erasing. block protect bits must cleared such that memory erased programmed unprotected. delay times such tEEBYTE, tEEBULK, tEEBLOCK, tEEFPV, etc., within specification? Timing critical ensure proper EEPROM operation. Delay times that long short alter EEPROM performance point where does work reliable. Motorola does guarantee EEPROM performance wrong delay times used. correct EEPROM register being written enable erase program? MC68HC908AS60A/AZ60A EEPROM arrays with separate sets control block protect registers. Make sure appropriate register being addressed.
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Question Answer
need constant timebase? EEPROM actually FLASH cell surrounded logic state machine. state machine requires accurate clock source applying high voltage during erase program operations.
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Freescale Semiconductor, Inc. Application Note
Question Answer What benefit using AUTO mode? When AUTO EEPROM programming erasing algorithms, programming erasing time much less than when standard EEPROM algorithms. Whenever programming erasing done, EEPGM automatically cleared, eliminating wait fixed delay time. Furthermore, since delay time necessary, delay routine required your code.
Freescale Semiconductor, Inc.
Question
During program/erase process, execute interrupt service include additional steps? Unrelated (non-EEPROM) steps included between steps program/erase algorithms long sequence steps remains consistent. However, interrupt service routines cause errors program erase timing lead corrupt missing data EEPROM. Motorola does guarantee performance EEPROM interrupts masked during program erase operation.
Answer
Question Answer
program each same EEPROM location successively? However, same byte location successively programmed using selective programming. Refer Selective Programming.
Question
programmed EExNVR register un-protect EEPROM blocks, blocks still protected? reset part read EExNVR after register programmed? Since configuration value loaded automatically EExACR register, resetting reading EExNVR required configuration.
Answer
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Application Note EEPROM Frequently Asked Questions
Question
When EEPRTCT EEPROM nonvolatile register (EExNVR) programmed with zero, does affect unsecured locations? (Secured locations EEPROM-1: $800-$8EF EEPROM2: $900-$9EF.) Once EEPRTCT cleared, block bulk erase operations disabled. However, byte erase byte program operations still enabled. Therefore, erase and/or program unsecured locations locations protected block protect register.
Answer
Freescale Semiconductor, Inc.
Question
charge pump used both EEPROM arrays? charge pump also shared with FLASH? Each array separate charge pump address decode logic does allow other array programmed erased time. FLASH charge pump.
Answer
Question
need confirm memory contents after programming EEPROM? recommended that code used program EEPROM also include verification step ensure integrity data programmed.
Answer
Question Answer
What expected lifetime EEPROM memory? minimum program/erase endurance data retention lifetime EEPROM memory conditions found MC68HC908AZ60A MC68HC908AS60A Technical Data, Motorola document order number MC68HC908AZ60A/D.
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Freescale Semiconductor, Inc. Application Note
Question Answer What steps take prolong life EEPROM memory? EEPROM memory finite program/erase durability finite data retention lifetime. However, specification quotes minimum guaranteed lifetime considering worst case conditions applied part. general, EEPROM array will last longer program/erase cycling kept minimum temperature kept nominal level (0-70oC).
Freescale Semiconductor, Inc.
Question
program/erase EEPROM maximum temperature limits specified life part? Yes. Program erase cycle durability specified 10-K minimum. However, exceeding that value recommended. Reading EEPROM occur continuously over life product.
Answer
FLASH Assembly Source Code Flowcharts
main routines SSTerase.mrt SSTprog.mrt initialize device erasing programming operations. SSTerase.mrt specifies size location erase block before calling FlashErase subroutine which follows algorithm listed this application note. SSTprog.mrt fills data buffer with values program, specifies location start programming, defines number bytes program before jumping ProgRow subroutine. SSTprog.mrt also includes verification step after programming completed. FlashErase ProgRow subroutines follow flowcharts shown Figure Figure closely. Flowcharts also included WriteFLCR subroutine which used clear various bits FLxCR registers ms_delay subroutine which generates delays greater than millisecond.
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Application Note FLASH Assembly Source Code Flowcharts
flowcharts SSTerase.mrt, SSTprog.mrt, FlashErase, ProgRow, WriteFLCR, ms_delay Figure Figure Figure Figure Figure Figure respectively.
SSTerase.mrt
DISABLE ENABLE
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LOAD FLASH ADDRESS WITHIN BLOCK ADDRESS RANGE ERASED INTO FLASH_addr
PAGE MASS ERASE ACCUMULATOR
CALL FlashErase ERASE PAGE ARRAY
Figure FLASH Erasing Main Routine Flowchart
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Freescale Semiconductor, Inc. Application Note
SSTprog.mrt
DISABLE ENABLE
LOAD DATA BUFFER WITH DATA PROGRAM (MAXIMUM BYTES)
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LOAD BUFFER STARTING ADDRESS INTO Buffer_addr
NUMBER BYTES PROGRAM size
LOAD FLASH PROGRAMMING START ADDRESS INTO FLASH_addr
CALL ProgRow PROGRAM
VERIFY PROGRAMMED DATA AGAINST BUFFER DATA
DATA MATCH? PROGRAMMING FAILURE PROGRAMMING SUCCESS
Figure FLASH Programming Main Routine Flowchart
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Application Note FLASH Assembly Source Code Flowcharts
FlashErase (SSTflash.srt)
DISABLE INTERRUPTS
PAGE ERASE MASS ERASE? PAGE ERASE STEP CALL ms_delay WAIT tERASE STEP CALL WriteFLCR CLEAR ERASE STEP WAIT TIME tNVH
STEP CALL WriteFLCR ERASE STEP
MASS ERASE STEP CALL ms_delay WAIT tMERASE STEP CALL WriteFLCR CLEAR ERASE STEP WAIT TIME tNVHL
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READ FLASH BLOCK PROTECT REGISTERS STEP WRITE FLASH_addr WITH DATA VALUE STEP WAIT TIME tNVS STEP CALL WriteFLCR HVEN
STEP CALL WriteFLCR CLEAR HVEN STEP WAIT TIME tRCV
ENABLE INTERRUPTS
RETURN
Figure Subroutine FlashErase Flowchart
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Freescale Semiconductor, Inc. Application Note
ProgRow (SSTflash.srt)
DISABLE INTERRUPTS STEP CALL WriteFLCR STEP READ FLASH BLOCK PROTECT REGISTERS STEP WAIT TIME tPROG COPY DATA BYTE FLASH_addr
STEP
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STEP WRITE FLASH_addr WITH DATA VALUE STEP WAIT TIME tNVS STEP CALL WriteFLCR HVEN STEP WAIT TIME tPGS STEP WAIT TIME tNVH STEP CALL WriteFLCR CLEAR HVEN STEP WAIT TIME tRCV STEP CALL WriteFLCR CLEAR STEP BYTES PROGRAMMED? (size DECREMENT size
ENABLE INTERRUPTS
RETURN
Figure Subroutine ProgRow Flowchart
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Application Note FLASH Assembly Source Code Flowcharts
WriteFLCR (SSTflash.srt)
FLASH_addr FLASH-1 ($8000)?
CLEAR FL1CR
CLEAR FL2CR
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RETURN
Figure Subroutine WriteFLCR Flowchart
ms_delay (SSTflash.srt)
GENERATE MILLISECOND DELAY TIME DEPENDING VALUE times
RETURN
Figure Subroutine Delay Flowchart
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Freescale Semiconductor, Inc. Application Note FLASH Assembly Source Code
FLASH Memory Erasing MC68HC908AS60A/AZ60A File Name: SSTerase.mrt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 06/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr Subroutine Called: FlashErase Full Functional Description Routine Design: SSTerase.mrt main routine that demonstrates erase FLASH memory MC68HC908AS60A MC68HC908AZ60A. memory erased per-page (128 bytes) basis entire array erased time (mass erase.) Motorola reserves right make changes without further notice product herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product, circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts.* Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death* occur. Should Buyer purchase Motorola products such intended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses,
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Application Note FLASH Assembly Source Code
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reasonable attorney fees arising directly indirectly, any* claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent* regarding design manufacture part. Motorola Motorola symbol registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. ***** Program Specific Equates ***** masserase. %00000100 pageerase. %00000000 ***** Include Files ***** NOLIST $INCLUDE "H908AS60A.frk" ;Equates registers bits MC68HC908AS60A ram1 $INCLUDE "SSTflash.var" ;RAM variable definitions LIST ***** Main Routine ***** ram2 Start: #$71,config-1 ;Turn COP, leave ldhx sthx #$8045 FLASH_addr #pageerase. FlashErase ;Any address within page array will erased ;Load address FLASH_addr ;Select "PAGE" "MASS" erase with Mass ;Erase area FLASH including specified address
***** Subroutine Body Includes Section ***** $INCLUDE "SSTflash.srt" ;SST FLASH subroutines
FLASH Memory Programming MC68HC908AS60A/AZ60A File Name: SSTprog.mrt Copyright Motorola 2001 Current Revision: Current Release Level:
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Freescale Semiconductor, Inc. Application Note
Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr, Buffer_addr, data, size Subroutine Called: ProgRow Full Functional Description Routine Design: SSTprog.mrt main routine programming operation. demonstrates programming algorithm that minimizes amount time needed program FLASH memory MC68HC908AS60A MC68HC908AZ60A. consists consecutive bytes FLASH memory within specified address ranges.* ***** Include Files ***** NOLIST $INCLUDE "H908AS60A.frk" ;Equates registers bits MC68HC908AS60A ram1 $INCLUDE "SSTflash.var" ;RAM variable definitions LIST ***** Main Routine ***** ram2 Start: #$71,config-1 ;Turn COP, leave ldhx #$0000 Data_load: data,x ;Fill buffer, bytes data, inca values program into FLASH (ie. 01,02,03,.,3E,3F,40) cphx #!64 Data_load ldhx sthx ldhx sthx #data Buffer_addr #!64 size #$8040 FLASH_addr ProgRow ;Load Buffer_addr with start address buffer ;Set number bytes program ;Load FLASH_addr with programming start address ;Program
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Application Note FLASH Assembly Source Code
Verify: ldhx sthx ldhx sthx Verify_Loop: sthx ldhx #!64 size #data Buffer_addr #$8040 FLASH_addr FLASH_addr Buffer_addr Error size Success Buffer_addr FLASH_addr Verify_Loop
;After desired block programmed, verify programmed data highly recommended
;Read data from FLASH location
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sthx ldhx Success:
;Compare data with data buffer ;When data correct, branch Error bytes programmed correctly, branch Success
Programming Successful program Error: Programming Failed Take appropriate action ***** Subroutine Body Includes Section ***** $INCLUDE "SSTflash.srt" ;SST FLASH subroutine
FLASH Memory Programming Erasing MC68HC908AS60A/AZ60A File Name: SSTflash.var Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2000 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Used (Bytes):
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Freescale Semiconductor, Inc. Application Note
Description: variable definitions SSTprog.mrt SSTerase.mrt ***** Variables ***** FLASH_addr Address FLASH memory erase program Buffer_addr Address data buffer data data bytes that will programmed size byte storage byte number contained times byte which delay time will determined temp byte temporary storage
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FLASH Memory Program Erase Subroutines MC68HC908AS60A/AZ60A* File Name: SSTflash.srt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Revision History: Rev. Delay time evaluation code added Module Size (Bytes): FlashErase ProgRow WriteFLCR ms_delay Stack Space Used (Bytes): FlashErase ProgRow WriteFLCR ms_delay Used (Bytes): FlashErase ProgRow WriteFLCR ms_delay Global Variable(s) Used: FlashErase FLASH_addr
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Application Note FLASH Assembly Source Code
ProgROW FLASH_addr, Buffer_addr data, size WriteFLCR FLASH_addr ms_delay None Submodule(s) Called: EraseRoutine WriteFLCR, ms_delay Prog8Bytes WriteFLCR WriteFLCR None ms_delay None Calling Sequence: FlashErase, ProgRow WriteFLCR, ms_delay Entry Label: FlashErase, ProgRow, WriteFLCR, ms_delay Entry Conditions: FlashErase bytes address defined FLASH_addr Mass definition passed accumulator ProgRow bytes address defined FLASH_addr bytes address defined Buffer_addr Maximum programming bytes located variables data byte defined SIZE WriteFLCR bytes address defined FLASH_addr FLCR (FLASH Control Register) definition passed accumulator ms_delay Delay valiable passed times Number Exit Points: Exit Label: FlashErase FlashErase_End ProgRow ProgRow_End WriteFLCR WriteFLCR_End ms_delay ms_delay_End Exit Conditions: FlashErase None ProgRow None WriteFLCR None ms_delay None Full Functional Description Subroutine: SSTflash.srt consists primary subroutines called FlashErase ProgRow. These demonstrate FLASH erasing programming algorithms, respectively. routines also call other subroutines WriteFLCR ms_delay. Since delay times must precisely successful FLASH programming erasing, additional software added measure delay times. This code included comments throughout file. recommended that user verify delay times before using this software production. Note: Each delay time related FLASH program erase operations calculated with speed 2.4576MHz.
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Freescale Semiconductor, Inc. Application Note
***** FLASH Erase Subroutine ***** FlashErase: Delay Time Evaluation Initialize Port output high bset 3,PTD ;Set Port bset 3,DDRD ;Select output Port ;Disable interrupts ldhx FLASH_addr ;Load starting address area erased registers temp ;Store value accumulator temp #erase. ;Step ERASE WriteFLCR MASS set, MASS erase will performed MASS clear, PAGE erase will performed fl1bpr ;Step Read from block protect fl2bpr registers ;Step Write FLASH address within area address range erased with data value Delay Time tNVS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port dbnza ;Step Wait time tNVS cycles cycles (10.6us)
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Delay Evaluation: Point bset 3,PTD ;Set Port #hven. WriteFLCR ;Step HVEN
brset MASS,temp,MASS_Erase MASS erase, jump MASS_Erase PAGE_Erase: ;PAGE Erase Delay Time tERASE Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port times ms_delay ;Step Wait time tERASE (1.0ms)
Delay Evaluation: Point
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Application Note FLASH Assembly Source Code
bset
3,PTD
;Set Port
#erase. ;Step Clear ERASE WriteFLCR Delay Time tNVH Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port dbnza ;Step Wait time tNVH cycles cycles (5.7us)
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Delay Evaluation: Point bset 3,PTD ;Set Port Step9 MASS_Erase: ;MASS Erase Delay Time tMERASE Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port times ms_delay ;Step Wait time tMERASE (4.0ms)
Delay Evaluation: Point bset 3,PTD ;Set Port #erase. ;Step Clear ERASE WriteFLCR Delay Time tNVHL Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port #$52 dbnza ;Step Wait time tNVHL cycles cycles (101us)
Delay Evaluation: Point bset 3,PTD ;Set Port Step9: #hven. ;Step Clear HVEN WriteFLCR Delay Time tRCV Evaluation (Time between points Measure level period Port using scope
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Freescale Semiconductor, Inc. Application Note
Delay Evaluation: Point bclr 3,PTD ;Clear Port dbnza ;Step Wait time tRCV cycles cycles (2.0us)
Delay Evaluation: Point bset 3,PTD ;Set Port #$00 fl1cr ;Clear bits Flash Control fl2cr registers ;Enable interrupts FlashErase_End: ***** FLASH Programming Subroutine ***** ProgRow: Delay Time Evaluation Initialize Port output high bset 3,PTD ;Set Port bset 3,DDRD ;Select output Port interrupts allowed during programming ldhx FLASH_addr ;Load address page programmed registers #pgm. ;Step WriteFLCR fl1bpr ;Step Read from block protect fl2bpr registers ;Step Write FLASH address with data within address range desired. Delay Time tNVS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port dbnza ;Step Wait time tNVS cycles cycles (10.6us)
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Delay Evaluation: Point bset 3,PTD ;Set Port #hven. ;Step HVEN WriteFLCR Delay Time tPGS Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point
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Application Note FLASH Assembly Source Code
bclr
3,PTD
;Clear Port ;Step Wait time tPGS cycles cycles (5.7us)
dbnza
Delay Evaluation: Point bset 3,PTD ;Set Port Copy_Loop: ldhx
Buffer_addr
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sthx Buffer_addr ldhx FLASH_addr ;-;- tPROG defined total time from writing data byte writing next data byte. (labelled below). last byte programmed, tPROG defined time from writing data byte ("A") clearing WriteFLCR routine). Both these loops should executed time between byte-to-next-byte time cycles (30.5 us). byte-to-PGM time cycles (31.3 us). ;-sta ;Write Data Byte ("A") Delay Time byte-to-next-byte Evaluation (one loop period starting from point point Measure level period Port using scope Delay Evaluation: Point ;Complement Port Delay Time byte-to-PGM Evaluation (Time between points E10_1 time between points E10_2) Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port #$0d dbnza sthx size Copy_End FLASH_addr ;Step Delay, part tPROG
;Step Copy byte data from buffer appropriate FLASH location ;Increment Buffer_addr next byte write
;Step Repeat step until bytes within programmed ;Increment FLASH_addr next byte write
Copy_Loop Copy_End: dbnza
;Step Delay, part tPROG
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Freescale Semiconductor, Inc. Application Note
#pgm. ;Step Clear WriteFLCR Delay Time tNVH Evaluation (Time between points E11) Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port dbnza ;Step Wait time tNVH cycles cycles (5.7us)
Delay Evaluation: Point bset 3,PTD ;Set Port
Freescale Semiconductor, Inc.
#hven. ;Step Clear HVEN WriteFLCR Delay Time tRCV Evaluation (Time between points E12) Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port sthx FLASH_addr ;Step Wait time tRCV cycles cycles (2.4us) ;Point next address FLASH_addr
Delay Evaluation: Point bset 3,PTD ;Set Port ;Clear interrupt mask return ProgRow_End: ***** Write FLASH Control Register ***** This routine determines whether flcr1 flcr2 should written which bit(s) flcr clear based accumulator value Flash address specified FLASH_addr. Initializations required: bit(s) accumulator making bit(s) flcr clear Load FLASH_addr registers Values returned: None WriteFLCR: cphx #flash-1 FLASH_addr Flash-1 array, Array1 jump Array1 fl2cr fl2cr ;Write fl2cr register
Delay Evaluation: Point E10_2
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Application Note FLASH Assembly Source Code
bset
3,PTD WriteFLCR_End
;Set Port
Array1: fl1cr fl1cr WriteFLCR_End: ;Write fl1cr register
Delay Evaluation: Point E10_1 bset 3,PTD ;Set Port ***** Delay Routine ***** This routine generates unit millisecond delay depending value "times". example times=1, delay time 1ms. Delay times Frequency (2459 times 2.4578MHz Initializations required: value "times" Values returned: None ms_delay: #!245 cyc. ms_loop: deca cyc. #$FF cyc. #$FF cyc. #$FF cyc. ms_loop cyc. times cyc. ms_delay cyc. ms_delay_End: cyc.
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Freescale Semiconductor, Inc. Application Note Standard EEPROM Assembly Source Code Flowcharts
main routine EEPROM.mrt initializes device erasing programming operations. sets clock source timebase divider EEPROM memory specifies value location programmed. routine then performs EEPROM erase program operations calling EEPROMroutine twice.
Freescale Semiconductor, Inc.
EEPROMroutine subroutine follows flowcharts that shown Figure Figure closely. Flowcharts also included WriteEECR subroutine which used clear various bits EExCR registers ms_delay subroutine which generates delays greater than millisecond. flowcharts EEPROM.mrt, EEPROMroutine.mrt, WriteEECR ms_delay Figure Figure Figure Figure respectively.
EEPROM.mrt
DISABLE ENABLE
LOAD byteerase, blockerase, bulkerase ACCUMULATOR
EEPROM TIMEBASE DIVIDER, WRITE PROPER VALUES EExDIVH EExDIVL (See Note)
CALL EEPROMroutine ERASE EEPROM
STORE BYTE DATA DATA BUFFER
LOAD byteprogram ACCUMULATOR
LOAD SELECTED EEPROM ADDRESS INTO EEPROM_addr
CALL EEPROMroutine PROGRAM EEPROM
Note: proper values have been programmed EExDIVHNVR EExDIVLNVR, this step necessary.
Figure Standard EEPROM Main Routine Flowchart
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Application Note Standard EEPROM Assembly Source Code Flowcharts
EEPROMroutine (EEPROM.srt) STEP DISABLE INTERRUPTS STEP CALL WriteEECR EERAS0/EERAS1 BITS EELAT STEP STEP CALL WriteEECR CLEAR EELAT CALL WriteEECR CLEAR EEPGM STEP WAIT TIME tEEFPV
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COPY DATA BYTE FROM BUFFER EEPROM_addr STEP CALL WriteEECR EEPGM STEP CALL ms_delay WAIT tEEPGM/tEEBYTE/tEEBLOCK/tEEBULK
CLEAR BITS EExCR
ENABLE INTERRUPTS
RETURN
Figure Subroutine EEPROMroutine Flowchart
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Freescale Semiconductor, Inc. Application Note
WriteEECR (EEPROM.srt)
EEPROM_addr EE2DIVHNVR ($FF70)?
EEPROM_addr EEPROM-1 ($0800)?
Freescale Semiconductor, Inc.
CLEAR EE1CR
CLEAR EE2CR
RETURN
Figure Subroutine WriteEECR Flowchart
ms_delay (EEPROM.srt)
GENERATE MILLISECOND DELAY TIME DEPENDING VALUE times
RETURN
Figure Subroutine ms_delay Flowchart
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Application Note Standard EEPROM Assembly Source Code
Standard EEPROM Assembly Source Code
EEPROM Programming Erasing MC68HC908AS60A/AZ60A File Name: EEPROM.mrt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: EEPROM_addr, data Subroutine Called: EEPROMroutine Full Functional Description Routine Design: EEPROM.mrt main routine EEPROM programming erasing operations. demonstrates programming erasing algorithms MC68HC908AS60A MC68HC908AZ60A. Note: this code, CGMXCLK used EEPROM reference clock source frequency 4.9152MHz ***** Program Specific Equates ***** byteprogram. %00000100 ;Select byte program EELAT byteerase. %00001100 ;Select byte erase EELAT blockerase. %00010100 ;Select block erase EELAT bulkerase. %00011100 ;Select bulk erase EELAT ***** Include Files ***** NOLIST $INCLUDE "H908AS60A.frk" ;Equates registers bits MC68HC908AS60A ram1 $INCLUDE "EEPROM.var" ;RAM variable definitions LIST ***** Main Routine ***** ram2
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Freescale Semiconductor, Inc. Application Note
Start: ldhx sthx #$71,config-1 #$80 EE1DIVH EE2DIVH #$AC EE1DIVL EE2DIVL #$AA data #$0676 EEPROM_addr #byteerase. EEPROMroutine #byteprogram. EEPROMroutine ;Turn COP, leave ;For setting constant timebase 35us write EExDIVH EExDIVL, respectively Note: EExDIVHNVR EExDIVLNVR registers programmed with proper values, this step necessary ;Write data buffer ;Load EEPROM_addr with address where byte should erased programmed ;Select Byte, Block Bulk Erase ;Erase selected erase size ;Select Byte Program ;Program byte
Freescale Semiconductor, Inc.
***** Subroutine Body Includes Section ***** $INCLUDE "EEPROM.srt" ;EEPROM subroutines
EEPROM Programming Erasing MC68HC908AS60A/AZ60A File Name: EEPROM.var Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Used (Bytes): Description: variable definitions EEPROM.mrt.
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Application Note Standard EEPROM Assembly Source Code
***** Variables ***** EEPROM_addr Address EEPROM memory erase program data ;data byte that will programmed times byte which delay time will specified
EEPROM Program Erase Subroutine MC68HC908AS60A/AZ60A File Name: EEPROM.srt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 5/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Revision History: Rev. Delay time evaluation code added Module Size (Bytes): EEPROMroutine WriteEECR ms_delay Stack Space Used (Bytes): EEPROMroutine WriteEECR ms_delay Used (Bytes): EEPROMroutine WriteEECR ms_delay Global Variable(s) Used: EEPROMroutine EEPROM_addr, data WriteEECR EEPROM_addr ms_delay None Submodule(s) Called: EEPROMroutine WriteEECR, ms_delay WriteEECR None ms_delay None Calling Sequence: EEPROMroutine, WriteEECR Entry Label: EEPROMroutine, WriteEECR, ms_delay Entry Conditions: EEPROMroutine bytes address defined EEPROM_addr programming byte located variable data (the
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Freescale Semiconductor, Inc. Application Note
erasing operation required) WriteEECR bytes address defined EEPROM_addr EECR (EEPROM Control Register) definition passed accumulator ms_delay Delay valiable passed times Number Exit Points: Exit Label: EEPROMroutine EEPROMroutine_End WriteEECR WriteEECR_End ms_delay ms_delay Exit Conditions: EEPROMroutine None WriteEECR None ms_delay None Full Functional Description Subroutine: EEPROM.srt consists three subroutines: EEPROMroutine, WriteEECR ms_delay. EEPROMroutine demonstrates EEPROM erasing programming. WriteEECR allows user clear bits EExCR registers. Since delay times must precisely successful EEPROM programming erasing, additional software added measure delay times. This code included comments throughout file. recommended that user verify delay times before using this software production. ***** EEPROM Program Erase Subroutine ***** EEPROMroutine: Delay Time Evaluation Initialize Port output high bset 3,PTD ;Set Port bset 3,DDRD ;Select output Port ;Disable interrupts WriteEECR ;Step EERAS0, EERAS1 desired operation EELAT data ;Step Write desired data ldhx EEPROM_addr appropriate EEPROM location #eepgm. ;Step EEPGM WriteEECR Delay Time tEEBYTE/tEEBULK/tEEBLOCK/tEEPGM Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port #!10 ;Step Wait time
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Application Note Standard EEPROM Assembly Source Code
times ms_delay
tEEBYTE/tEEBULK/tEEBLOCK/tEEPGM (all
Delay Evaluation: Point bset 3,PTD ;Set Port #eepgm. ;Step Clear EEPGM WriteEECR Delay Time tEEFPV Evaluation (Time between points Measure level period Port using scope Delay Evaluation: Point bclr 3,PTD ;Clear Port
Freescale Semiconductor, Inc.
#$52 dbnza
;Step Wait time tEEFPV (101us) cycles cycles
Delay Evaluation: Point bset 3,PTD ;Set Port #eelat. ;Step Clear EELAT WriteEECR #$00 ;Clear bits EExCR EE1CR EE2CR ;Enable interrupts EEPROMroutine_End: ***** Write EEPROM Control Register ***** This routine determines whether EE1CR EE2CR should written which bit(s) EExCR clear based accumulator value EEPROM address specified EEPROM_addr. Initializations required: bit(s) accumulator making bit(s) EExCR clear Load EEPROM_addr registers Values returned: None WriteEECR: cphx #EE2DIVHNVR address $FF70, branch EEPROM2 EEPROM2 cphx #eeprom-1 address $0800, write EEPROM1 EEPROM1 EEPROM2: EE2CR ;Write EE2CR register EE2CR WriteEECR_End EEPROM1: EE1CR ;Write EE1CR register EE1CR WriteEECR_End:
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Freescale Semiconductor, Inc. Application Note
***** Delay Routine ***** This routine generates unit millisecond delay depending value "times". example times=1, delay time 1ms. Delay times Frequency (2459 times 2.4578MHz Initializations required: value "times" Values returned: None ms_delay: #!245 cyc. ms_loop: deca cyc. #$FF cyc. #$FF cyc. #$FF cyc. ms_loop cyc. times cyc. ms_delay cyc. ms_delay_End: cyc.
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Application Note EEPROM AUTO Mode Source Code Flowcharts
EEPROM AUTO Mode Source Code Flowcharts
main routine AutoEEPROM.mrt initializes device erasing programming operations. sets clock source timebase divider EEPROM memory specifies value location programmed. routine then performs EEPROM erase program operations calling AUTOroutine twice.
Freescale Semiconductor, Inc.
AUTOroutine subroutine follow flowcharts shown Figure Figure closely. Flowcharts also included WriteEECR subroutine which used clear various bits EExCR registers. flowcharts AutoEEPROM.mrt, AUTOroutine.mrt, WriteEECR Figure Figure Figure respectively.
AutoEEPROM.mrt
DISABLE ENABLE
LOAD byteerase, blockerase, bulkerase ACCUMULATOR
EEPROM CLOCK SOURCE TIMEBASE DIVIDER: CONFIG2, EExDIVH, EExDIVL (See Note)
CALL AUTOroutine ERASE EEPROM
STORE BYTE DATA DATA BUFFER
LOAD byteprogram ACCUMULATOR
LOAD SELECTED EEPROM ADDRESS INTO EEPROM_addr
CALL AUTOroutine PROGRAM EEPROM
Note: proper values have been programmed EExDIVHNVR EExDIVLNVR, this step necessary.
Figure EEPROM AUTO Mode Main Routine
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Freescale Semiconductor, Inc. Application Note
AUTOroutine (AutoEEPROM.srt)
DISABLE INTERRUPTS
STEP CALL WriteEECR EERAS0/EERAS1 BITS, EELAT BIT, AUTO STEP
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COPY DATA BYTE FROM BUFFER EEPROM_addr STEP CALL WriteEECR EEPGM
STEP EEPGM EExCR STILL SET? STEP CALL WriteEECR CLEAR EELAT
CLEAR BITS EExCR
ENABLE INTERRUPTS
RETURN
Figure Subroutine AutoEEPROM Flowchart
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Application Note EEPROM AUTO Mode Source Code Flowcharts
WriteEECR (EEPROM.srt)
EEPROM_addr EE2DIVHNVR ($FF70)?
EEPROM_addr EEPROM-1 ($0800)?
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CLEAR EE1CR
CLEAR EE2CR
RETURN
Figure Subroutine WriteEECR Flowchart
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Freescale Semiconductor, Inc. Application Note EEPROM AUTO Mode Assembly Source Code
EEPROM AUTO Programming Erasing MC68HC908AS60A/AZ60A File Name: AutoEEPROM.mrt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Revision History: Rev. EELAT AUTO bits same timing Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: EEPROM_addr, data Subroutine Called: AutoRoutine Full Functional Description Routine Design: AutoEEPROM.mrt main routine EEPROM programming erasing operations using AUTO mode. demonstrates AUTO programming erasing MC68HC908AS60A MC68HC908AZ60A.* Note: this code, internal clock used EEPROM reference clock source frequency 2.4576MHz. ***** Program Specific Equates ***** auto_byteprogram. %00000110 ;Select byte program, EELAT AUTO bits auto_byteerase. %00001110 ;Select byte erase, EELAT AUTO bits auto_blockerase. %00010110 ;Select block erase, EELAT AUTO bits auto_bulkerase. %00011110 ;Select bulk erase, EELAT AUTO bits ***** Include Files ***** NOLIST $INCLUDE "H908AS60A.frk" ;Equates registers bits MC68HC908AS60A
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Application Note EEPROM AUTO Mode Assembly Source Code
ram1 $INCLUDE "AutoEEPROM.var" ;RAM variable definitions LIST ***** Main Routine ***** ram2 Start: #$71,config-1 ;Turn COP, leave ldhx sthx #$98 config-2 #$80 EE1DIVH EE2DIVH #$56 EE1DIVL EE2DIVL #$55 data #$0634 EEPROM_addr #auto_bulkerase. AutoRoutine ;Select clock reference clock source ;For setting constant timebase 35us write EExDIVH EExDIVL, respectively Note: EExDIVHNVR EExDIVLNVR registers programmed with proper values, this step necessary ;Write data buffer
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;Load EEPROM_addr with address where byte should erased programmed ;Select Bulk, Block Byte Erase ;Erase selected EEPROM size using AUTO Mode
#auto_byteprogram. AutoRoutine ;Select Byte Program ;Program byte using AUTO Mode
***** Subroutine Body Includes Section ***** $INCLUDE "AutoEEPROM.srt" ;Auto EEPROM subroutines
EEPROM AUTO Programming Erasing MC68HC908AS60A/AZ60A File Name: AutoEEPROM.var Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2000 Current Release Written Adeela Gill Kazue Kikuchi
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Freescale Semiconductor, Inc. Application Note
Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Used (Bytes): Description: variable definitions AutoEEPROM.mrt. ***** Variables ***** EEPROM_addr Address EEPROM memory erase program data ;one data byte that will programmed
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EEPROM AUTO Program Erase Subroutine MC68HC908AS60A/AZ60A File Name: AutoEEPROM.srt Copyright Motorola 2001 Current Revision: Current Release Level: Current Revision Release Date: 6/21/2001 Current Release Written Adeela Gill Kazue Kikuchi Motorola Applications Engineering Austin, Assembled Under: CASM08Z (P&E Microcomputer Systems, Inc.) Ver.: 3.16 Part Family Software Routine Works With: HC08 Revision History: Rev. AUTO Step Module Size (Bytes): AutoRoutine WriteEECR Stack Space Used (Bytes): AutoRoutine WriteEECR Used (Bytes): AutoRoutine WriteEECR Global Variable(s) Used: AutoRoutine EEPROM_addr, data WriteEECR EEPROM_addr Submodule(s) Called: AutoRoutine WriteEECR WriteFLCR None Calling Sequence: AutoRoutine, writeEECR
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Application Note EEPROM AUTO Mode Assembly Source Code
Freescale Semiconductor, Inc.
Entry Label: AutoRoutine, WriteEECR Entry Conditions: AutoRoutine bytes address defined EEPROM_addr programming byte located variable data (the erasing operation required) WriteEECR bytes address defined EEPROM_addr EECR (EEPROM Control Register) definition passed accumulator Number Exit Points: Exit Label: AutoRoutine AutoRoutine_End WriteEECR WriteEECR_End Exit Conditions: AutoRoutine None WriteEECR None Full Functional Description Subroutine: AutoEEPROM.srt contains primary subroutine called AutoRoutine.* This demonstrates EEPROM erasing programming AUTO mode.* routine also calls another subroutine WriteEECR. ***** EEPROM AUTO Program Erase Subroutine ***** AutoRoutine: ;Disable interrupts WriteEECR ;Step EERAS0, EERAS1 desired operation, EELAT AUTO data ;Step programming, copy byte ldhx EEPROM_addr data from buffer appropriate EEPROM location Clear_EEPGM1: Clear_EEPGM2: #eepgm. WriteEECR EE1CR #$01 Clear_EEPGM1 EE2CR #$01 Clear_EEPGM2 #eelat. WriteEECR ;Step EEPGM
;Step Wait until EEPGM cleared Checks included both EEPGM registers since programmed byte could either array
;Step Clear EELAT
#$00 EE1CR EE2CR AutoRoutine_End:
;Clear bits EExCR
;Enable interrupts
AN2156 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
***** Write EEPROM Control Register ***** This routine determines whether EE1CR EE2CR should written which bit(s) EExCR clear based accumulator value EEPROM address specified EEPROM_addr. Initializations required: bit(s) accumulator making bit(s) EExCR clear Load EEPROM_addr registers Values returned: None WriteEECR: cphx #EE2DIVHNVR address $FF70, branch EEPROM2 EEPROM2 cphx EEPROM2: EEPROM1: WriteEECR_End: EE1CR EE1CR ;Write EE1CR register EE2CR EE2CR WriteEECR_End ;Write EE2CR register #eeprom-1 EEPROM1 address $0800, write EEPROM1
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
Motorola, Inc., 2001
AN2156/D More Information This Product, www.freescale.com

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