AN2150 Converting HC08AZ32 Code HC08AZ32A Tracy McHenry Syst
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AN2150
Converting HC08AZ32 Code HC08AZ32A
Tracy McHenry Systems Engineering East Kilbride, Scotland.
Freescale Semiconductor, Inc.
Introduction
purpose this document help customers convert 0.65µ HC08AZ32 codes 0.5µ HC08AZ32A. highlights differences between devices provides step step guide converting HC08AZ32 codes HC08AZ32A. This application note also applicable code conversions from HC08AB32 HC08AB32A, HC08AB24 HC08AB24A, HC08AZ16 HC08AZ16A HC08AZ24 HC08AZ24A. However, applicable code conversions from HC08AB16 HC08AB16A. main change EEPROM module. EEPROM made from technology. Read operations remain unchanged, however, program erase operations super-set present algorithm. EEPROM contains registers that must correctly before attempt made program erase EEPROM. registers required provide EEPROM with constant timebase 35µs from user's oscillator frequency. HC08AZ32A EEPROM also supports option that enables significantly faster programming/erasing EEPROM. Appendix shows recommended algorithms program erase operations.
Motorola, Inc., 2001
More Information This Product, www.freescale.com
Application Note
very important spend time gaining familiarity with EEPROM changes essential that EEPROM module correctly before program erase operations called. Failure could cause premature wear EEPROM could result improper programming/erasing EEPROM. Also, care should taken over settings registers. polarity several bits MORA register been changed. Extra bits available MORB which also address, $FE09. register changes have been made align HC08AZ32A other HC(9)08 A-family devices.
Freescale Semiconductor, Inc.
Major differences between HC08AZ32 HC08AZ32A
This section describes differences between HC08AZ32 HC08AZ32A. Each affected module listed along with summary changes.
Mask Option Register
polarity several bits this register changed align HC08AZ32A with other HC08AS family devices. Bit-2, COPRS Rate Select determine timeout period selected enables short timeout period 8176 cycles. Bit-4, LVIPWR Power enable (previously LVIPWRD) selected enables module power. Bit-5, LVIRST reset enable (previously LVIRSTD) selected enables reset signal from module. Bits 0,1, remain unchanged. However, HC08AZ32 device errata bit-6 longer applicable ROMSEC will enable security HC08AZ32A.
AN2150 Major differences between HC08AZ32 HC08AZ32A More Information This Product, www.freescale.com Motorola
Application Note
Mask Option Register
This register located address $FE09 (previously $003F) bits activated. Bit-3, AZ32A device indicator (silicon hard bit), which identifies A-suffix silicon. this then HC08AZ32A silicon. Bit-4, EEMONSEC EEPROM Read Protection Monitor Mode bit. When selected entire EEPROM array cannot accessed monitor mode unless valid security code entered. Bit-7, EEDIVCLK EEPROM Timebase Divider Clock Select which selects reference clock source EEPROM timebase divider. Selected means that clock (possibly PLL) drives EEPROM time base divider. selects CGMXCLK instead.
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EEPROM
HC08AZ32A EEPROM made from technology; however, basic programming erase operations remain unchanged. polarity same; programmed state logic erased state logic HC08AZ32A EEPROM requires constant timebase source program erase operations. clock source that required drive EEDIV clock divider input must first selected using bit-7 introduced onto MORB register address $FE09. Secondly, divide ratio from this source programming 11bit time base pre-scalar into registers, EEDIVH EEDIVL. These registers must programmed with proper value before starting EEPROM erase programming steps. function divider provide constant clock source with period 35µs (within 2µs) internal timer related EEPROM circuits proper program erase operations. recommended frequency range reference clock 250KHz 16MHz.
AN2150 Motorola Major differences between HC08AZ32 HC08AZ32A More Information This Product, www.freescale.com
Application Note
EEDIV value calculated following formula: EEDIV= INT[Reference Frequency(Hz) x10-6 0.5] result rounded down nearest integer value. example, Reference Frequency 4.9152MHz, EEDIV value above formula will 172. examine time base output divider, Reference Frequency divided calculated EEDIV value (172), which equals 28.577KHz frequency 34.99µs period. user must exercise caution when setting divide ratio EEDIVH EEDIVL volatile registers. They have duplicate nonvolatile registers, EEDIVHNVR EEDIVLNVR whose contents loaded into EEDIVH EEDIVL upon reset. However, user should remember correctly EEDIVH EEDIVL registers before attempting program EEDIVHNVR EEDIVLNVR non-volatile registers. user options listed below. Option Write required divider value into EEDIVH EEDIVL. Call EEPROM programming routine program EEDIVHNVR EEDIVLNVR with divider value that user would like downloaded into EEDIVH EEDIVL every time device reset. Option user's initialisation routine that called every time device reset before EEPROM program erase operations attempted, write required divider value into EEDIVH EEDIVL Ignore non-volatile EEDIVHNVR EEDIVLNVR registers. After reset, initialisation routine will executed required divider value will written into EEDIVH EEDIVL. This will overwrite default value that downloaded upon reset from EEDIVHNVR EEDIVLNVR.
Freescale Semiconductor, Inc.
AN2150 Major differences between HC08AZ32 HC08AZ32A More Information This Product, www.freescale.com Motorola
Application Note
EEDIVH EEDIVL registers shown below should also noted that Bit-7, EEDIVSECD, EEDIVH (and EEDIVHNVR) controls EEPROM security. this programmed after system reset security feature permanently enabled divider value EEDIV registers cannot changed.
EEDIVH $FE1A
Reset:
Bit-7
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EEDIVSECD
EEDIVHNVR
EEDIV10
EEDIVHNVR
EEDIV9
EEDIVHNVR
EEDIV8
EEDIVHNVR
EEDIVL $FE1B
Reset:
Bit-7
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EEDIV2
EEDIV1
EEDIV0
EEDIVLNVR EEDIVLNVR EEDIVLNVR EEDIVLNVR EEDIVLNVR EEDIVLNVR EEDIVLNVR EEDIVLNVR
NOTE:
result EEDIV clock described above, (EEBCLK) EEPROM control register (EECR) longer used. other main difference HC08AZ32A EEPROM inclusion EEPROM control register (EECR) AUTO function. Setting bit-1 (previously unused) that register enables AUTO function. AUTO function allows logic automatically optimum programming erasing time EEPROM. Using AUTO function means that user does need wait normal minimum specified programming erasing time. After setting EEPGM normal, user only poll that again, waiting clear indicating that programming erasing complete.
AN2150 Motorola Major differences between HC08AZ32 HC08AZ32A More Information This Product, www.freescale.com
Application Note
Finally, HC08AZ32A special feature that designates bytes addresses from $08F0 $08FF permanently secured. This security option enabled programming EEPRTCT EEPROM Non-Volatile Register (EENVR, address $FE1C)) logic Once EEPRTCT programmed first time programming erasing secured locations $08F0 $08FF permanently disabled. Secured locations $08F0 $08FF can, however, read normal. Programming erasing EENVR permanently disabled bulk block erase operations disabled unprotected locations ($0800-$08EF $0900-$09FF). Single byte program erase operations still available locations $0800-$08EF $0900-$09FF bytes that protected EEPROM Block Protect, EEPBx, bits EENVR.
Freescale Semiconductor, Inc.
NOTE:
Once armed, protect option permanently enabled. Consequently, functions EENVR will remain state they were immediately before security enabled.
Analogue Digital Converter
user longer required select 15-channels versus 8-channels submission. Every HC08AZ32A will configured with 15channel analog digital converter.
CAUTION:
pins used channels share their functions with timer clock inputs well general purpose I/O. Therefore, channels using TACLK TBCLK pins clock inputs 16-bit timers.
Timer Interface Module
TIMA channel timer (previously channel). Additional vectors located $FFCC $FFCF which used area.
AN2150 Major differences between HC08AZ32 HC08AZ32A More Information This Product, www.freescale.com Motorola
Application Note
result extra timer channels described above total amount bytes available 32,256 bytes (previously 32,272 bytes). HC08AZ32A located addresses $8000 $BFFF $C000 $FDFF.
Monitor
Increased size bytes functionality remains unchanged. HC08AZ32 bytes located $FE20 $FEFF HC08AZ32A bytes located $FE20 $FF5F
Freescale Semiconductor, Inc.
Step step Guide
flowchart shown figure step step checklist user through should ensure differences between HC08AZ32 HC08AZ32A have been considered before submitting code.
AN2150 Motorola Step step Guide More Information This Product, www.freescale.com
Application Note
Polarity change MORA register. Check bits
Check reads MORB located address $FE09. Also, MORB bits available user requires select polarity them.
Freescale Semiconductor, Inc.
EEPROM requires EEDIV registers initialisation routine before EEPROM program erase operations called. Take care about bit-7 which programmed (logic enables security will lock this register.
EEPROM option (which recommended)
AUTO feature, located EECR register ($FE1D). After setting EEPGM bit, poll AUTO until clears Once EEPGM until clears Once clear EEPROM been programmed/erased
every HC08AZ32A configured with 15-channel analog digital converter. However, changes required using additional channels.
TIMA channel timer with additional vectors located area $FFCC $FFCF. However, changes required using additional channels.
consequence vectors required timer changes total bytes available been reduced bytes from 32,272 32,256 bytes. Therefore, locations $FFCC $FFCF longer available. However, changes required using locations $FFCC $FFCF.
Figure Step Step Conversion Checklist
AN2150 Step step Guide More Information This Product, www.freescale.com Motorola
Application Note
Conclusion
differences discussed above should checked they impact conversion HC08AZ32 code, particular, Mask Option Register changes EEPROM changes. Care should taken when setting EEDIVH, EEDIVL, EEDIVHNVR EEDIVLNVR registers ensure that setting bit-7, EEDIVSECD, does permanently enable EEDIV security feature. This essential EEDIV register values require changed. recommended that required divider value written into EEDIV registers writing EEDIVL first, then EEDIVH, taking care over value written bit-7, EEDIVSECD EEDIVH. Also, important note that EEDIVH EEDIVL registers must written with required divider value before attempting program erase EEPROM (including no-volatile registers) prevent EEPROM from being severely damaged. Finally, user advised read relevant chapters HC08AZ32A specification ensure differences have been fully captured. also advisable gain familiarity with HC908AZ60A emulator device, which uses same EEPROM module.
Freescale Semiconductor, Inc.
AN2150 Motorola
Conclusion More Information This Product, www.freescale.com
Application Note Appendix EEPROM Program Erase Algorithms
Programming
EEPROM programmed such that multiple bits programmed (written logic time. However, user must program more than once before erasing entire byte. That user allowed program logic that already programmed (bit state already logic unprogrammed state logic Programming changes state logic Only valid EEPROM bytes non-protected blocks EENVR programmed. Follow procedure below program byte EEPROM after first ensuring block protect feature address block byte programmed: Clear EERAS1 EERAS0 EELAT EECR. (See note
Freescale Semiconductor, Inc.
NOTE:
using AUTO mode also AUTO during Step Write desired data user EEPROM address. (See note EEPGM bit. (See note step AUTO set. Wait time, EEPGM, program byte. Clear EEPGM bit. Wait time, EEFPV, programming voltage fall. step Poll EEPGM until cleared internal timer. (See note Clear EELAT bits. (See note
AN2150 Appendix EEPROM Program Erase Algorithms More Information This Product, www.freescale.com Motorola
Application Note
NOTE:
EERAS1 EERAS0 must cleared programming. Otherwise, part will erase mode. Setting EELAT configures address data buses latch data programming array. Only data with valid EEPROM address will latched. EELAT set, other writes EECR will allowed after valid EEPROM write. more than valid EEPROM write occurs, last address data will latched overriding previous address data. Once data written desired address, read EEPROM locations other than written location. (Reading EEPROM location returns latched data causes read address latched). EEPGM cannot EELAT cleared nonvalid EEPROM address latched. This ensure proper programming sequence. Once EEPROM set, read EEPROM locations; otherwise, current program cycle will unsuccessful. When EEPGM set, on-board programming sequence will activated. delay time EEPGM cleared AUTO mode less than tEEPGM. However, other MCUs, this delay time different. forward compatibility, software should make dependency this delay time. attempt clear both EEPGM EELAT bits with single instruction will only clear EEPGM. This allow time removal high voltage from EEPROM array.
Freescale Semiconductor, Inc.
AN2150 Motorola
Appendix EEPROM Program Erase Algorithms More Information This Product, www.freescale.com
Application Note Erasing
unprogrammed state logic Erasing changes state programmed (logic logic Only EEPROM bytes nonprotected blocks EENVR erased. following procedure erase byte, block entire EEPROM array: Configure EERAS1 EERAS0 select byte, block bulk erase; EELAT EECR. (See note
Freescale Semiconductor, Inc.
NOTE:
using AUTO mode, also AUTO during Step Byte erase: write data desired address. Block erase: write data address within desired block. Bulk erase: write data address within desired array. (See note EEPGM bit. (See note step AUTO set. Wait time: tEEBYTE byte erase; tEEBLOCK bulk erase; tEEBULK bulk erase. Clear EEPGM bit. Wait time, tEEFPV, erasing voltage fall. step Poll EEPGM until cleared internal timer. (See note Clear EELAT bits. (See note
AN2150 Appendix EEPROM Program Erase Algorithms More Information This Product, www.freescale.com Motorola
Application Note
NOTE:
Setting EELAT configures address data buses latch data erasing array. Only valid EEPROM addresses will latched. EELAT set, other writes EECR will only allowed after valid EEPROM write. more than valid EEPROM write occurs, last address data will latched overriding previous address data. Once data written desired address, read EEPROM locations other than written location. (Reading EEPROM location returns latched data causes read address latched). EEPGM cannot EELAT cleared nonvalid EEPROM address latched. This ensure proper erasing sequence. Once EEPGM set, read EEPROM locations; otherwise, current erase cycle will unsuccessful. delay time EEPGM cleared AUTO mode less than tEEBYTE/t EEBLOCK EEBULK. However, other MCUs, this delay time different. forward compatibility, software should make dependency this delay time. attempt clear both EEPGM EELAT bits with single instruction will only clear EEPGM. This allow time removal high voltage from EEPROM array.
Freescale Semiconductor, Inc.
AN2150 Motorola
Appendix EEPROM Program Erase Algorithms More Information This Product, www.freescale.com
Application Note Memory Characteristics
Characteristic EEPROM Programming Time Byte EEPROM Erasing Time Byte EEPROM Erasing Time Block EEPROM Erasing Time Bulk EEPROM Programming Voltage Discharge Period Number Programming Operations same EEPROM Byte Before Erase
Symbol EEPGM EEBYTE EEBLOCK EEBULK EEFPV
Unit
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EEPROM Write/Erase Cycles Write Time +125 EEPROM Data Retention After 10,000 Write/Erase Cycles EEPROM Programming Maximum Time `AUTO' EEPROM Erasing Maximum Time `AUTO'
10,000
Cycles
Years
Programming byte more times than specified maximum affect data integrity that byte. byte must erased before programmed again.
AN2150 Appendix EEPROM Program Erase Algorithms More Information This Product, www.freescale.com Motorola
Application Note
Freescale Semiconductor, Inc.
AN2150 Motorola
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Application Note
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Motorola, Inc., 2000
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AN2150/D
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